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Электронный компонент: NM93C06LZ

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TL D 11778
NM93C06LZC46LZC56LZC66LZ
256-1024-2048-4096-Bit
Serial
EEPROM
with
Zero
Power
and
Extended
Voltage
(27V
to
55V)
(MICROWIRE
Bus
Interface)
September 1996
NM93C06LZ C46LZ C56LZ C66LZ
256- 1024- 2048- 4096-Bit Serial EEPROM with Zero
Power and Extended Voltage (2 7V to 5 5V)
(MICROWIRE
TM
Bus Interface)
General Description
The NM93C06LZ C46LZ C56LZ C66LZ devices are 256
1024 2048 4096 bits respectively of CMOS non-volatile
electrically erasable memory divided into 16 64 128 256
16-bit registers They are fabricated using National Semi-
conductor's floating-gate CMOS process for high reliability
and low power consumption These memory devices are
available in both SO and TSSOP packages for small space
considerations
The serial interface that operates these EEPROMs is MI-
CROWIRE compatible for simple interface to standard mi-
crocontrollers and microprocessors There are 7 instruc-
tions that control these devices Read Erase Write Enable
Erase Erase All Write Write All and Erase Write Disable
The ready busy status is available on the DO pin to indicate
the completion of a programming cycle
Features
Y
Less than 1 0 mA standby current
Y
2 7V 5 5V operation in all modes
Y
Typical active current of 100 mA
Y
Direct write no erase before program
Y
Reliable CMOS floating gate technology
Y
MICROWIRE compatible serial I O
Y
Self-timed programming cycle
Y
Device status indication during programming mode
Y
40 years data retention
Y
Endurance 10
6
data changes
Y
Packages available 8-pin SO 8-pin DIP 8-pin TSSOP
Block Diagram
TL D 11778 1
TRI-STATE
is a registered trademark of National Semiconductor Corporation
MICROWIRE
TM
is a trademark of National Semiconductor Corporation
C1996 National Semiconductor Corporation
RRD-B30M96 Printed in U S A
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Connection Diagram
Dual-in-Line Package (N)
8-Pin SO (M8) and 8-Pin TSSOP (MT8)
TL D 11778 2
Top View
See NS Package Number
N08E and M08A
Pin Names
Pin
Description
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
V
CC
Power Supply
Ordering Information
Commercial Temperature Range (0 C to
a
70 C)
Order Number
NM93C06LZN NM93C46LZN
NM93C56LZN NM93C66LZN
NM93C06LZM8 NM93C46LZM8
NM93C56LZM8 NM93C66LZM8
NM93C06LZMT8 NM93C46LZMT8
NM93C56LZMT8 NM93C66LZMT8
Extended Temperature Range (
b
40 C to
a
85 C)
Order Number
NM93C06LZEN NM93C46LZEN
NM93C56LZEN NM93C66LZEN
NM93C06LZEM8 NM93C46LZEM8
NM93C56LZEM8 NM93C66LZEM8
NM93C06LZEMT8 NM93C46LZEMT8
NM93C56LZEMT8 NM93C66LZEMT8
Automotive Temperature Range (
b
40 C to
a
125 C)
Order Number
NM93C06LZVN NM93C46LZVN
NM93C56LZVN NM93C66LZVN
NM93C06LZVM8 NM93C46LZVM8
NM93C56LZVM8 NM93C66LZVM8
NM93C06LZVMT8 NM93C46LZVMT8
NM93C56LZVMT8 NM93C66LZVMT8
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2
LOW VOLTAGE (2 7V
s
4 5V) SPECIFICATIONS
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Ambient Storage Temperature
b
65 C to
a
150 C
All Input or Output Voltage
with Respect to Ground
V
CC
a
1 to
b
0 3V
Lead Temperature (Soldering 10 sec )
a
300 C
ESD Rating
2000V
Operating Conditions
Ambient Operating Temperature
NM93C06LZ 46LZ 56LZ 66LZ
0 C to
a
70 C
NM93C06LZE 46LZE 56LZE 66LZE
b
40 C to
a
85 C
NM93C06LZV 46LZV 56LZV 66LZV
b
40 C to
a
125 C
Power Supply (V
CC
) Range
2 7V to 4 5V
DC and AC Electrical Characteristics
Symbol
Parameter
Part Number
Conditions
Min
Max
Units
I
CC1
Operating Current
NM93C06 46 56 66LZ
CS
e
V
IH
SK
e
250 kHz
1
mA
CMOS Input Levels
NM93C06 46 56 66LZE V
1
I
CC3
Standby Current
NM93C06 46 56 66LZ
CS
e
0V
1
m
A
NM93C06 46 56 66LZE V
1
I
IL
Input Leakage
NM93C06 46 56 66LZ
V
IN
e
0V to V
CC
b
100
a
100
nA
NM93C06 46 56 66LZE V
I
OL
Output Leakage
NM93C06 46 56 66LZ
V
IN
e
0V to V
CC
b
100
a
100
nA
NM93C06 46 56 66LZE V
V
IL2
Input Low Voltage
2V
s
V
CC
s
4 5V
b
0 1
0 15 V
CC
V
V
IH2
Input High Voltage
2V
s
V
CC
s
4 5V
0 8 V
CC
V
CC
a
1
V
V
OL2
Output Low Voltage
I
OL
e
10 mA
0 2
V
V
OH2
Output High Voltage
I
OH
e b
10 mA
0 9 V
CC
V
f
SK
SK Clock Frequency
NM93C06 46 56 66LZ
0
250
kHz
NM93C06 46 56 66LZE V
0
250
t
SKH
SK High Time
NM93C06 46 56 66LZ
(Note 2)
1
m
s
NM93C06 46 56 66LZE V
1
t
SKL
SK Low Time
NM93C06 46 56 66LZ
(Note 2)
1
m
s
NM93C06 46 56 66LZE V
1
t
SKS
SK Setup Time
NM93C06 46 56 66LZ
Relative to CS
50
m
s
NM93C06 46 56 66LZE V
50
t
CS
Minimum CS Low Time
NM93C06 46 56 66LZ
(Note 3)
1
m
s
NM93C06 46 56 66LZE V
1
t
CSS
CS Setup Time
NM93C06 46 56 66LZ
Relative to SK
0 2
m
s
NM93C06 46 56 66LZE V
0 2
t
DH
DO Hold Time
Relative to SK
70
ns
t
DIS
DI Setup Time
NM93C06 46 56 66LZ
Relative to SK
0 4
m
s
NM93C06 46 56 66LZE V
0 4
t
CSH
CS Hold Time
Relative to SK
0
m
s
t
DIH
DI Hold Time
Relative to SK
0 4
m
s
t
PD1
Output Delay to ``1''
NM93C06 46 56 66LZ
AC Test
2
m
s
NM93C06 46 56 66LZE V
2
t
PD0
Output Delay to ``0''
NM93C06 46 56 66LZ
AC Test
2
m
s
NM93C06 46 56 66LZE V
2
t
SV
CS to Status Valid
NM93C06 46 56 66LZ
AC Test
1
m
s
NM93C06 46 56 66LZE V
1
t
DF
CS to DO
NM93C06 46 56 66LZ
AC Test
0 4
m
s
in TRI-STATE
NM93C06 46 56 66LZE V
CS
e
V
IL
0 4
t
WP
Write Cycle Time
NM93C06 46 56 66LZ
V
CC
e
2 7V
15
ms
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3
STANDARD VOLTAGE (4 5V
s
V
CC
s
5 5V) SPECIFICATIONS
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Ambient Storage Temperature
b
65 C to
a
150 C
All Input or Output Voltage
with Respect to Ground
V
CC
a
1 to
b
0 3V
Lead Temperature (Soldering 10 sec )
a
300 C
ESD Rating
2000V
Operating Conditions
Ambient Operating Temperature
NM93C06LZ 46LZ 56LZ 66LZ
0 C to
a
70 C
NM93C06LZE 46LZE 56LZE 66LZE
b
40 C to
a
85 C
NM93C06LZV 46LZV 56LZV 66LZV
b
40 C to
a
125 C
Power Supply (V
CC
) Range
4 5V to 5 5V
DC and AC Electrical Characteristics
4 5V
s
V
CC
s
5 5V
Symbol
Parameter
Part Number
Conditions
Min
Max
Units
I
CC1
Operating Current
NM93C06 46 56 66LZ
CS
e
V
IH
SK
e
1 MHz
2
mA
CMOS Input Levels
NM93C06 46 56 66LZE V
SK
e
1 MHz
2
I
CC2
Operating Current
NM93C06 46 56 66LZ
CS
e
V
IH
SK
e
1 MHz
3
mA
TTL Input Levels
NM93C06 46 56 66LZE V
3
I
CC3
Standby Current
NM93C06 46 56 66LZ
CS
e
0V
50
m
A
NM93C06 46 56 66LZE V
50
I
IL
Input Leakage
NM93C06 46 56 66LZ
V
IN
e
0V to V
CC
b
2 5
2 5
nA
NM93C06 46 56 66LZE V
b
10
10
I
OL
Output Leakage
NM93C06 46 56 66LZ
V
IN
e
0V to V
CC
b
2 5
2 5
nA
NM93C06 46 56 66LZE V
b
10
10
V
IL
Input Low Voltage
b
0 1
0 8
V
V
IH
Input High Voltage
2
V
CC
a
1
V
V
OL1
Output Low Voltage
NM93C06 46 56 66LZ
I
OL
e
2 1 mA
0 4
V
NM93C06 46 56 66LZE V
I
OH
e
2 1 mA
0 4
V
OH1
Output High Voltage
I
OL
e b
400 mA
2 4
V
V
OL2
Output Low Voltage
NM93C06 46 56 66LZ
I
OL
e
10 mA
0 2
V
NM93C06 46 56 66LZE V
V
OH2
Output High Voltage
I
OH
e b
10 mA
0 9 V
CC
V
f
SK
SK Clock Frequency
NM93C06 46 56 66LZ
0
1
MHz
NM93C06 46 56 66LZE V
0
1
t
SKH
SK High Time
NM93C06 46 56 66LZ
250
ns
NM93C06 46 56 66LZE V
300
t
SKL
SK Low Time
NM93C06 46 56 66LZ
250
ns
NM93C06 46 56 66LZE V
250
t
CS
Minimum CS Low Time
NM93C06 46 56 66LZ
(Note 3)
250
ns
NM93C06 46 56 66LZE V
250
t
CSS
CS Setup Time
NM93C06 46 56 66LZ
Relative to SK
50
ns
NM93C06 46 56 66LZE V
50
t
DH
DO Hold Time
Relative to SK
70
ns
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STANDARD VOLTAGE (4 5V
s
V
CC
s
5 5V) SPECIFICATIONS
(Continued)
DC and AC Electrical Characteristics
V
CC
e
5 0V
g
10% unless otherwise specified (Continued)
Symbol
Parameter
Part Number
Conditions
Min
Max
Units
t
DIS
DI Setup Time
NM93C06 46 56 66LZ
Relative to SK
100
ns
NM93C06 46 56 66LZE V
200
t
CSH
CS Hold Time
Relative to SK
0
ns
t
DIH
DI Hold Time
Relative to SK
20
ns
t
PD1
Output Delay to ``1''
NM93C06 46 56 66LZ
AC Test
500
ns
NM93C06 46 56 66LZE V
500
t
PD0
Output Delay to ``0''
NM93C06 46 56 66LZ
AC Test
500
ns
NM93C06 46 56 66LZE V
500
t
SV
CS to Status Valid
NM93C06 46 56 66LZ
AC Test
500
ns
NM93C06 46 56 66LZE V
500
t
DF
CS to DO in TRI-STATE
NM93C06 46 56 66LZ
AC Test
100
ns
NM93C06 46 56 66LZE V
CS
e
V
IL
100
t
WP
Write Cycle Time
10
ms
AC Test Conditions
Output Load 1 TTL Gate and C
L
e
100 pF
V
CC
Range
AC Test Conditions
4 5V
k
V
CC
k
5 5V
Input Pulse Levels
0 8V and 2 0V
Timing Measurement Level (V
IL
V
IH
)
0 9V and 1 9V
Timing Measurement Level (V
OL
V
OH
) 0 8V and 2 0V
(TTL Load Condition
I
OL
e
2 1 mA I
OH
e b
0 4 mA)
2 7V
k
V
CC
k
4 5V
Input Pulse Levels
0 3V and 0 8 V
CC
Timing Measurement Level (V
IL
V
IH
)
0 4V and 1 6V
Timing Measurement Level (V
OL
V
OH
) 0 8V and 1 6V
(CMOS Load Condition
I
OL
e
10 mA I
OH
e b
10 mA)
Capacitance
T
A
e
25 C f
e
1 MHz
Symbol
Test
Max
Units
C
OUT
Output Capacitance
5
pF
C
IN
Input Capacitance
5
pF
Note 1
Stress above those listed under ``Absolute Maximum Ratings'' may cause permanent damage to the device This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability
Note 2
Minimum V
CC
requirements All functional modes are guaranteed to full operation at V
CC
t
2V except the bulk programming op-codes ERAL and WRAL
These are regarded as test mode commands and are only guaranteed to V
CC
t
2 5V
Note 3
CS must be brought low for a minimum of 1 t
CS
between consecutive instruction cycles
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Functional Description
The NM93C06 C46 C56 C66LZ devices have 7 instruc-
tions as described below Note that the MSB of any instruc-
tion is a ``1'' and is viewed as a start bit in the interface
sequence For the C06LZ and C46LZ the next 8 bits carry
the op code and the 6-bit address for register selection For
the C56LZ and C66LZ the next 10 bits carry the op code
and the 8-bit address for register selection
Read (READ)
The READ instruction outputs serial data on
the DO pin After the READ instruction is received the in-
struction and address are decoded followed by data trans-
fer from the selected memory register into a serial-out shift
register A dummy bit (logical 0) precedes the 16-bit data
output string Output data changes are initiated by a low to
high transition of the SK clock
Erase Write Enable (EWEN)
When V
CC
is applied to the
part it powers up in the Erase Write Disable (EWDS) state
Therefore all programming modes must be preceded by an
Erase Write Enable (EWEN) instruction Once an Erase
Write Enable instruction is executed programming remains
enabled until an Erase Write Disable (EWDS) instruction is
executed or until V
CC
is removed from the part
Erase (ERASE)
The ERASE instruction will program all bits
in the specified register to the logical ``1'' state CS is
brought low following the loading of the last address bit
This falling edge of the CS pin initiates the self-timed pro-
gramming cycle
The DO pin indicates the READY BUSY status of the chip
DO
e
logical ``0'' indicates that programming is still in prog-
ress DO
e
logical ``1'' indicates that the register at the
address specified in the instruction has been erased and
the part is ready for another instruction
Write (WRITE)
The WRITE instruction is followed by 16
bits of data to be written into the specified address After the
last bit of data is put on the data-in (DI) pin CS must be
brought low before the next rising edge of the SK clock
This falling edge of CS initiates the self-timed programming
cycle The DO pin indicates the READY BUSY status of the
chip if CS is brought high after a minimum of 250 ns (t
CS
)
DO
e
logical 0 indicates that programming is still in prog-
ress DO
e
1 indicates that the register at the address
specified in the instruction has been written with the data
pattern specified in the instruction and the part is ready for
another instruction
Erase All (ERAL)
The ERAL instruction will simultaneously
program all registers in the memory array and set each bit to
the logical ``1'' state The Erase All cycle is identical to the
ERASE cycle except for the different op code As in the
ERASE mode the DO pin indicates the READY BUSY
status of the chip The ERASE ALL instruction is not re-
quired see note below
Write All (WRAL)
The WRAL instruction will simultaneous-
ly program all registers with the data pattern specified in the
instruction As in the WRITE mode the DO pin indicates the
READY BUSY status of the chip
Erase Write Disable (EWDS)
To protect against acciden-
tal data disturb the (EWDS) instruction disables all pro-
gramming modes and should follow all programming opera-
tions Execution of a READ instruction is independent of
both the EWEN and EWDS instructions
Note
The NM93C06 C46 C56 C66LZ devices do not require an ``ERASE''
or ``ERASE ALL'' prior to the ``WRITE'' or ``WRITE ALL'' instructions
Instruction Set for the NM93C06LZ and NM93C46LZ
Instruction
SB
Op Code
Address
Data
Comments
READ
1
10
A5 A0
Read data stored in memory at specified address
EWEN
1
00
11XXXX
Write enable must precede all programming modes
EWDS
1
11
A5 A0
Erase register A5 A4 A3 A2 A1 A0
WRITE
1
01
A5 A0
D15 D0
Writes register
ERAL
1
00
10XXXX
Erases all registers
WRAL
1
00
01XXXX
D15 D0
Writes all registers
EWDS
1
00
00XXXX
Disables all programming instructions
Instruction Set for the NM93C56LZ and NM93C66LZ
Instruction
SB
Op Code
Address
Data
Comments
READ
1
10
A7 A0
Read data stored in memory at specified address
EWEN
1
00
11XXXXXX
Write enable must precede all programming modes
EWDS
1
11
A7 A0
Erase selected register
ERAL
1
00
10XXXXXX
Erases all registers
WRITE
1
01
A7 A0
D15 D0
Write register if address is unprotected
WRAL
1
00
01XXXXXX
D15 D0
Writes all registers
EWDS
1
00
00XXXXXX
Disables all programming instructions
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Timing Diagrams
Synchronous Data Timing
TL D 11778 3
t
SKS
is not needed if DI
e
V
IL
when CS is going active (HIGH)
READ
TL D 11778 4
Address bits A5 and A4 become ``don't care'' for NM93C06LZ
Address bit A7 becomes a ``don't care'' for NM93C56LZ
EWEN
TL D 11778 5
The NM93C56LZ and NM93C66LZ require a minimum of 11 clock cycles The NM93C06LZ and NM93C46LZ require a minimum of 9 clock cycles
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Timing Diagrams
(Continued)
EWDS
TL D 11778 6
The NM93C56LZ and NM93C66LZ require a minimum of 11 clock cycles The NM93C06LZ and NM93C46LZ require a minimum of 9 clock cycles
WRITE
TL D 11778 7
Address bits A5 and A4 become ``don't care'' for NM93C06LZ
Address bit A7 becomes a ``don't care'' for NM93C56LZ
WRAL
TL D 11778 8
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Timing Diagrams
(Continued)
ERASE
TL D 11778 9
Address bits A5 and A4 become ``don't care'' for NM93C06LZ
Address bit A7 becomes a ``don't care'' for NM93C56LZ
ERAL
TL D 11778 10
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Physical Dimensions
inches (millimeters) unless otherwise noted
Molded Small Out-Line Package (M8)
NS Package Number M08A
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Note Unless otherwise specified
1 Reference JEDEC Registration M0-153 Variation AA Dated 7 93
8-Pin Molded TSSOP JEDEC (MT8)
NS Package Number MTC08
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11
NM93C06LZC46LZC56LZC66LZ
256-1024-2048-4096-Bit
Serial
EEPROM
with
Zero
Power
and
Extended
Voltage
(27V
to
55V)
(MICROWIRE
Bus
Interface)
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
8-Lead Molded Dual-In-Line Package (N)
NS Package Number N08E
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein
1 Life support devices or systems are devices or
2 A critical component is any component of a life
systems which (a) are intended for surgical implant
support device or system whose failure to perform can
into the body or (b) support or sustain life and whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system or to affect its safety or
with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
National Semiconductor
National Semiconductor
National Semiconductor
National Semiconductor
Corporation
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Japan Ltd
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Fax 81-043-299-2408
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Tel (852) 2737-1600
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Italiano
Tel a49 (0) 180-534 16 80
Fax (852) 2736-9960
National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications