MM58342
High Voltage Display Driver
General Description
The MM58342 is a monolithic MOS integrated circuit utilizing
CMOS metal gate low threshold P- and N-channel devices. It
is available both in 28-pin molded dual-in-line packages or
as dice. The MM58342 is particularly suited for driving high
voltage (35V max) vacuum fluorescent (VF) displays (e.g., a
20-digit alphanumeric or dot matrix display).
Applications
n
COPS
TM
or microprocessor-driven displays
n
Instrumentation readouts
n
Industrial control indicator
n
Digital clock, thermostat, counter, voltmeter
n
Word processor text displays
n
Automotive dashboards
Features
n
Direct interface to high voltage display
n
Serial data input
n
No external resistors required
n
Wide display power supply operation
n
LSTTL compatible inputs
n
Software compatible with NS display driver family
n
Compatible with alphanumeric or dot matrix displays
n
Display blanking control input
n
Simple to cascade
Block Diagram
00792501
FIGURE 1.
February 1995
MM58342
High
V
oltage
Display
Driver
2001 National Semiconductor Corporation
DS007925
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Input Pin
V
DD
+ 0.3V to
V
SS
-0.3V
Voltage at Any Display Pin
V
DD
to V
DD
-36.5V
V
DD
+ |V
DIS
|
36.5V
Storage Temperature
-65C to +150C
Power Dissipation at 25C
Molded DIP Package, Board Mount
2.03W (Note 2)
Molded DIP Package, Socket Mount
1.83W (Note 3)
Junction Temperature
130C
Lead Temperature (Soldering, 10 sec.)
260C
Operating Conditions
Min
Max
Units
Supply Voltage (V
DD
)
V
SS
= 0V
4.5
5.5
V
Display Voltage (V
DIS
)
-30
-10
V
Temperature Range
-40
+85
C
Electrical Characteristics
T
A
= -40C to +85C, V
DD
= 5V
0.5V, V
SS
= 0V unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Power Supply Currents
I
DD
V
IN
= V
SS
or V
DD
, V
SS
= 0V,
V
DIS
Disconnected
150
A
I
DIS
V
DD
= 5.5V, V
SS
= 0V, V
DIS
= -30V
All Outputs Low
10
mA
Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
V
IL
Logic "0"
0.8
V
V
IH
Logic "1"
(Note 4)
2.4
V
Data Output Logic Levels
V
OL
Logic "0"
I
OUT
= 400 A
0.4
V
V
OH
Logic "1"
I
OUT
= -10 A
V
DD
-0.5
V
V
OH
Logic "1"
I
OUT
= -500 A
2.8
V
I
IN
Input Currents DATA IN,
CLOCK ENABLE, BLANK
V
IN
= 0V or V
DD
-10
10
A
C
IN
Input Capacitance DATA IN,
CLOCK ENABLE, BLANK
15
pF
Display Output Impedances
V
DD
= 5.5V, V
SS
= 0V
R
OFF
Output Off (
Figure 3)
V
DIS
= -10V
55
250
k
V
DIS
= -20V
60
300
k
V
DIS
= -30V
65
400
k
R
ON
Output On (
Figure 4)
V
DIS
= -10V
700
800
V
DIS
= -20V
600
750
V
DIS
= -30V
500
680
V
DOL
Display Output Low Voltage
V
DD
= 5.5V, I
OUT
= Open Circuit,
-30V
V
DIS
-10V
V
DIS
V
DIS
+ 2
V
AC Electrical Characteristics
T
A
= -40C to +85C, V
DD
= 5V
0.5V
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Clock Input
(Notes 6, 7)
f
C
Frequency
800
kHz
t
H
High Time
300
ns
t
L
Low Time
300
ns
Data Input
t
DS
Set-Up Time
100
ns
t
DH
Hold Time
100
ns
MM58342
www.national.com
2
AC Electrical Characteristics
T
A
= -40C to +85C, V
DD
= 5V
0.5V (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Enable Input
(Note 5)
t
ES
Set-Up Time
100
ns
t
EH
Hold Time
100
ns
t
CDO
Data Output
C
L
= 50 pF
500
ns
Clock Low to Data Out
Time
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Molded DIP Package, Board Mount,
JA
= 52C/W, derate 19.2 mW/C above 25C.
Note 3: Molded DIP Package, Socket Mount,
JA
= 58C/W, derate 17.2 mW/C above 25C.
Note 4: 74LSTTL V
OH
= 2.7V
@
I
OUT
= -400 A, TTL V
OH
= 2.4V
@
I
OUT
= -400 A.
Note 5: For timing purposes, the signals ENABLE and BLANK can be considered to be totally independent of each other.
Note 6: AC input waveform specification for test purposes: t
r
, t
f
20 ns, f = 800 kHz, 50%
10% duty cycle.
Note 7: Clock input rise and fall times must not exceed 5 s.
Connection Diagrams
Plastic Chip Carrier
00792508
Top View
Order Number MM58342V
See NS Package Number V28B
Functional Description
This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data path
to the display driver. The MM58342 uses three signals,
DATA IN, CLOCK and ENABLE, where ENABLE acts as an
external load signal. Display blanking can be achieved by
means of the BLANKING CONTROL input, and a logic "1"
will turn off all sections of the display. A block diagram of the
MM58342 is shown in
Figure 1.
Figure 2 shows the pinout of the MM58342 device, where
output 1 (pin 12) is equivalent to bit 1 (i.e., the first bit of data
to be loaded into the shift register following ENABLE high). A
logic "1" at the input will turn on the corresponding display
digit/segment/dot output.
A significant reduction in discrete board components can be
achieved by use of the MM58342, because external
Dual-In-Line Package
00792502
Top View
Order Number MM58342N
See NS Package Number N28B
FIGURE 2.
MM58342
www.national.com
3
Functional Description
(Continued)
pull-down resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied. However,
Figures 3, 4
show that this output impedance will remain constant for a
fixed value of display voltage.
Figure 5 demonstrates the critical timing requirements be-
tween CLOCK and DATA IN for the MM58342.
To clear (reset) the display driver at power on or any time,
the following flushing routine may be used. With the enable
signal high, clock in 20 zeroes. Drive the enable signal low
and the display will be blank. It is recommended to clear the
driver at power on.
In
Figure 6, the ENABLE signal acts as an envelope, and
only while this signal is at a logic "1" does the circuit accept
CLOCK input signals. Data is transferred and shifted in the
internal shift register on the rising clock edge, i.e., "0""1"
transition. When the ENABLE signal goes low, the contents
of the shift registers are latched, and the display will show
new data. During data transfer, the display will show old
data. DATA OUT is also provided on the MM58342 being
output on the falling edge. At any time, the display may be
blanked under processor control, using the BLANKING
CONTROL input.
Figure
7
shows
a
schematic
diagram
of
a
microprocessor-based system where the MM58342 is used
to provide the grid drive for a 40-digit 2 line 5 x 7 multiplexed
vacuum fluorescent (VF) display. The anode drive in this
example is provided by another member of the high voltage
display driver family, namely the MM58348, which does not
require an extremely generated load signal.
Timing Diagrams
00792503
FIGURE 3. Output Impedance Off
00792504
FIGURE 4. Output Impedance On
00792505
FIGURE 5. Clock and Data Timings
MM58342
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4
Timing Diagrams
(Continued)
Typical Application
00792506
FIGURE 6. Timings (Data Format)
00792507
FIGURE 7. Microprocessor-Controlled Word Processor
MM58342
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5
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