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Электронный компонент: MM54C200

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TL F 5903
MM54C200MM74C200
256-Bit
TRI-STATE
Random
Access
ReadWrite
Memory
February 1988
MM54C200 MM74C200 256-Bit TRI-STATE
Random Access Read Write Memory
General Description
The MM54C200 MM74C200 is a 256-bit random access
read write memory Inputs consist of eight address lines
and three chip enables The eight binary address inputs are
decoded internally to select each of the 256 locations The
internal address register latches and address information
are on the positive to negative edge of CE
3
The TRI-
STATE data output line working in conjunction with CE
1
or
CE
2
inputs provides for easy memory expansion
Address Operation
Address inputs must be stable t
SA
pri-
or to the positive to negative transition of CE
3
It is therefore
unnecessary to hold address information stable for more
than t
HA
after the memory is enabled (positive to negative
transition)
Note
The timing is different from the DM74200 in that a positive to negative
transition of the CE
3
must occur for the memory to be selected
Read Operation
The data is read out by selecting the
proper address and bringing CE
3
low and WE high
Holding either CE
1
CE
2
or CE
3
at a high level forces the
output into TRI-STATE When used in bus-organized sys-
tems CE
1
or CE
2
a TRI-STATE control provides for fast
access times by not totally disabling the chip
Write Operation
Data is written into the memory with CE
3
low and WE low The state of CE
1
or CE
2
has no effect on
the write cycle The output assumes TRI-STATE with WE
low
Features
Y
Wide supply voltage range
3V to 15V
Y
Guaranteed noise margin
1V
Y
High noise immunity
0 45 V
CC
(typ )
Y
TTL compatibility
Fan out of 1
driving standard TTL
Y
Low power
500 nW (typ )
Y
Internal address register
Logic and Connection Diagrams
TL F 5903 1
Dual-In-Line Package
TL F 5903 2
Top View
Order Number MM54C200 or
MM74C200
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Pin
b
0 3V to V
CC
a
0 3V
Operating Temperature Range (T
A
)
MM54C200
b
55 C to
a
125 C
MM74C200
b
40 C to
a
85 C
Storage Temperature Range (T
S
)
b
65 C to
a
150 C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Operating V
CC
Range
3V to 15V
Absolute Maximum V
CC
18V
Lead Temperature (T
L
)
(Soldering 10 seconds)
260 C
DC Electrical Characteristics
Min Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
IN(1)
Logical ``1'' Input Voltage
V
CC
e
5V
3 5
V
V
CC
e
10V
8
V
V
IN(0)
Logical ``0'' Input Voltage
V
CC
e
5V
1 5
V
V
CC
e
10V
2
V
V
OUT(1)
Logical ``1'' Output Voltage
V
CC
e
5V I
O
e b
10 mA
4 5
V
V
CC
e
10V I
O
e b
10 mA
9
V
V
OUT(0)
Logical ``0'' Output Voltage
V
CC
e
5V I
O
e a
10 mA
0 5
V
V
CC
e
10V I
O
e a
10 mA
1
V
I
IN(1)
Logical ``1'' Input Current
V
CC
e
15V V
IN
e
15V
0 005
1
m
A
I
IN(0)
Logical ``0'' Input Current
V
CC
e
15V V
IN
e
0V
b
1
b
0 005
m
A
I
CC
Supply Current
V
CC
e
15V
0 1
600
m
A
CMOS TTL INTERFACE
V
IN(1)
Logical ``1'' Input Voltage
54C
V
CC
e
4 5V
V
CC
b
1 5
V
74C
V
CC
e
4 75V
V
CC
b
1 5
V
V
IN(0)
Logical ``0'' Input Voltage
54C
V
CC
e
4 5V
0 8
V
74C
V
CC
e
4 75V
0 8
V
V
OUT(1)
Logical ``1'' Output Voltage
54C
V
CC
e
4 5V I
O
e b
1 6 mA
2 4
V
74C
V
CC
e
4 75V I
O
e b
1 6 mA
2 4
V
V
OUT(0)
Logical ``0'' Output Voltage
54C
V
CC
e
4 5V I
O
e
1 6 mA
0 4
V
74C
V
CC
e
4 75V I
O
e
1 6 mA
OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
Output Source Current
V
CC
e
5V V
OUT
e
0V
b
4
b
6
mA
(P-Channel)
T
A
e
25 C
b
1 8
mA
I
SOURCE
Output Source Current
V
CC
e
10V V
OUT
e
0V
b
16
b
25
mA
(P-Channel)
T
A
e
25 C
b
1 5
mA
I
SINK
Output Sink Current
V
CC
e
5V V
OUT
e
V
CC
5
8
mA
(N-Channel)
T
A
e
25 C
I
SINK
Output Sink Current
V
CC
e
10V V
OUT
e
V
CC
20
30
mA
(N-Channel)
T
A
e
25 C
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range''
they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device
operation
2
AC Electrical Characteristics
T
A
e
25 C C
L
e
50 pF unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
ACC
Access Time from Address
V
CC
e
5V
450
900
ns
V
CC
e
10V
200
400
ns
t
pd
Propagation Delay from CE
3
V
CC
e
5V
360
700
ns
V
CC
e
10V
120
300
ns
t
pCE1
Propagation Delay from CE
1
or CE
2
V
CC
e
5V
250
700
ns
V
CC
e
10V
85
200
ns
t
SA
Address Setup Time
V
CC
e
5V
200
80
ns
V
CC
e
10V
100
30
ns
t
HA
Address Hold Time
V
CC
e
5V
50
15
ns
V
CC
e
10V
25
5 0
ns
t
WE
Write Enable Pulse Width
V
CC
e
5V
300
160
ns
V
CC
e
10V
150
70
ns
t
CE
CE
3
Pulse Widths
V
CC
e
5V
400
200
ns
V
CC
e
10V
160
80
ns
C
IN
Input Capacity
Any Input (Note 2)
5 0
pF
C
OUT
Output Capacity in TRI-STATE
(Note 2)
9 0
pF
C
PD
Power Dissipation Capacity
(Note 3)
400
pF
AC Electrical Characteristics
C
L
e
50 pF
MM54C200
MM74C200
Symbol
Parameter
Conditions
T
A
e b
55 C to
a
125 C
T
A
e b
40 C to
a
85 C
Units
Min
Max
Min
Max
t
ACC
Access Time from Address
V
CC
e
5V
1200
1100
ns
V
CC
e
10V
520
480
ns
t
pd
Propagation Delay from CE
3
V
CC
e
5V
950
850
ns
V
CC
e
10V
400
360
ns
t
pdCE1
Propagation Delay from
V
CC
e
5V
650
600
ns
CE
1
or CE
2
V
CC
e
10V
300
275
ns
t
SA
Address Setup Time
V
CC
e
5V
250
250
ns
V
CC
e
10V
120
120
ns
t
HA
Address Hold Time
V
CC
e
5V
100
100
ns
V
CC
e
10V
50
50
ns
t
WE
Write Enable Pulse Width
V
CC
e
5V
450
400
ns
V
CC
e
10V
225
200
ns
t
CE
Disable Pulse Width
V
CC
e
5V
500
460
ns
V
CC
e
10V
250
230
ns
t
HD
Data Hold Time
V
CC
e
5V
50
50
ns
V
CC
e
10V
25
25
ns
AC Parameters are guaranteed by DC correlated testing
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range''
they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device
operation
Note 2
Capacitance is guaranteed by periodic testing
Note 3
C
PD
determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note
AN-90
3
Switching Time Waveforms
Read and Write Cycles Using CE
3
(CE
1
e
CE
2
e
logic 0)
TL F 5903 3
Read and Write Cycles Using CE
3
and CE
1
(or CE
2
)
TL F 5903 4
Note
Used for fast access time in bused systems
4
Physical Dimensions
inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C200J or MM74C200J
NS Package Number J16A
5