DS90LV049
3V LVDS Dual Line Driver with Dual Line Receiver
General Description
The DS90LV049 is a dual CMOS flow-through differential
line driver-receiver pair designed for applications requiring
ultra low power dissipation, exceptional noise immunity, and
high data throughput. The device is designed to support data
rates in excess of 400 Mbps utilizing Low Voltage Differential
Signaling (LVDS) technology.
The DS90LV049 drivers accept LVTTL/LVCMOS signals and
translate them to LVDS signals. On the other hand, the
receivers accept LVDS signals and translate them to 3 V
CMOS signals. The LVDS input buffers have internal failsafe
biasing that places the outputs to a known H (high) state for
floating receiver inputs. In addition, the DS90LV049 supports
a TRI-STATE function for a low idle power state when the
device is not in use.
The EN and EN inputs are ANDed together and control the
TRI-STATE outputs. The enables are common to all four
gates.
Features
n
Up to 400 Mbps switching rates
n
Flow-through pinout simplifies PCB layout
n
50 ps typical driver channel-to-channel skew
n
50 ps typical receiver channel-to-channel skew
n
3.3 V single power supply design
n
TRI-STATE output control
n
Internal fail-safe biasing of receiver inputs
n
Low power dissipation (70 mW at 3.3 V static)
n
High impedance on LVDS outputs on power down
n
Conforms to TIA/EIA-644-A LVDS Standard
n
Industrial operating temperature range (-40C to +85C)
n
Available in low profile 16 pin TSSOP package
Connection Diagram
Dual-In-Line
20042001
Order Number DS90LV049TMT
Order Number DS90LV049TMTX (Tape and Reel)
See NS Package Number MTC16
Functional Diagram
20042002
Truth Table
EN
EN
LVDS Out
LVCMOS Out
L or Open
L or Open
OFF
OFF
H
L or Open
ON
ON
L or Open
H
OFF
OFF
H
H
OFF
OFF
March 2003
DS90L
V049
3V
L
VDS
Dual
Line
Driver
with
Dual
Line
Receiver
2003 National Semiconductor Corporation
DS200420
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DD
)
-0.3 V to +4 V
LVCMOS Input Voltage (D
IN
)
-0.3 V to (V
DD
+ 0.3 V)
LVDS Input Voltage (R
IN+
, R
IN-
)
-0.3 V to +3.9 V
Enable Input Voltage (EN, EN)
-0.3 V to (V
DD
+ 0.3 V)
LVCMOS Output Voltage (D
IN
)
-0.3 V to (V
DD
+ 0.3 V)
LVDS Output Voltage
(D
OUT+
, D
OUT-
)
-0.3 V to +3.9 V
LVCMOS Output Short Circuit
Current (R
OUT
)
100 mA
LVDS Output Short Circuit
Current (D
OUT+
, D
OUT-
)
24 mA
LVDS Output Short Circuit
Current Duration(D
OUT+
, D
OUT-
)
Continuous
Storage Temperature Range
-65C to +150C
Lead Temperature Range
Soldering (4 sec.)
+260C
Maximum Junction Temperature
+150C
Maximum Package Power Dissipation
@
+25C
MTC Package
866 mW
Derate MTC Package
6.9 mW/C above +25C
ESD Rating
(HBM, 1.5 k
, 100 pF)
7 kV
(MM, 0
, 200 pF)
250 V
Recommended Operating
Conditions
Min
Typ
Max
Units
Supply Voltage (V
DD
)
+3.0
+3.3
+3.6
V
Operating Free Air
Temperature (T
A
)
-40
+25
+85
C
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 4, 6)
Symbol
Parameter
Conditions
Pin
Min
Typ
Max
Units
LVCMOS Input DC Specifications (Driver Inputs, ENABLE Pins)
V
IH
Input High Voltage
D
IN
EN
EN
2.0
V
DD
V
V
IL
Input Low Voltage
GND
0.8
V
I
IH
Input High Current
V
IN
= V
DD
-10
1
+10
A
I
IL
Input Low Current
V
IN
= GND
-10
-0.1
+10
A
V
CL
Input Clamp Voltage
I
CL
= -18 mA
-1.5
-0.6
V
LVDS Output DC Specifications (Driver Outputs)
| V
OD
|
Differential Output Voltage
R
L
= 100
(Figure 1)
250
350
450
mV
V
OD
Change in Magnitude of V
OD
for
Complementary Output States
1
35
|mV|
V
OS
Offset Voltage
1.125
1.23
1.375
V
V
OS
Change in Magnitude of V
OS
for
Complementary Output States
1
25
|mV|
I
OS
Output Short Circuit Current
(Note 14)
ENABLED,
D
IN
= V
DD
, D
OUT+
= 0 V or
D
IN
= GND, D
OUT-
= 0 V
D
OUT-
D
OUT+
-5.8
-9.0
mA
I
OSD
Differential Output Short Circuit
Current (Note 14)
ENABLED, V
OD
= 0 V
-5.8
-9.0
mA
I
OFF
Power-off Leakage
V
OUT
= 0 V or 3.6 V
V
DD
= 0 V or Open
-20
1
+20
A
I
OZ
Output TRI-STATE Current
EN = 0 V and EN = V
DD
V
OUT
= 0 V or V
DD
-10
1
+10
A
LVDS Input DC Specifications (Receiver Inputs)
V
TH
Differential Input High Threshold
V
CM
= 1.2 V, 0.05 V, 2.35 V
-15
35
mV
V
TL
Differential Input Low Threshold
R
IN+
R
IN-
-100
-15
mV
V
CMR
Common-Mode Voltage Range
V
ID
= 100 mV, V
DD
=3.3 V
0.05
3
V
I
IN
Input Current
V
DD
=3.6 V
V
IN
=0 V or 2.8 V
-12
4
+12
A
V
DD
=0 V
V
IN
=0 V or 2.8 V or 3.6 V
-10
1
+10
A
DS90L
V049
www.national.com
2
Electrical Characteristics
(Continued)
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 4, 6)
Symbol
Parameter
Conditions
Pin
Min
Typ
Max
Units
LVCMOS Output DC Specifications (Receiver Outputs)
V
OH
Output High Voltage
I
OH
= -0.4 mA, V
ID
= 200 mV
R
OUT
2.7
3.3
V
V
OL
Output Low Voltage
I
OL
= 2 mA, V
ID
= 200 mV
0.05
0.25
V
I
OZ
Output TRI-STATE Current
Disabled, V
OUT
=0 V or V
DD
-10
1
+10
A
General DC Specifications
I
DD
Power Supply Current (Note 3)
EN = 3.3 V
V
DD
21
35
mA
I
DDZ
TRI-State Supply Current
EN = 0 V
15
25
mA
Switching Characteristics
V
DD
= +3.3V
10%, T
A
= -40C to +85C (Notes 4, 13)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVDS Outputs (Driver Outputs)
t
PHLD
Differential Propagation Delay High to Low
R
L
= 100
(Figure 2 and Figure 3)
0.7
2
ns
t
PLHD
Differential Propagation Delay Low to High
0.7
2
ns
t
SKD1
Differential Pulse Skew |t
PHLD
- t
PLHD
|
(Notes 5, 7)
0
0.05
0.4
ns
t
SKD2
Differential Channel-to-Channel Skew
(Notes 5, 8)
0
0.05
0.5
ns
t
SKD3
Differential Part-to-Part Skew (Notes 5, 9)
0
1.0
ns
t
TLH
Rise Time (Note 5)
0.2
0.4
1
ns
t
THL
Fall Time (Note 5)
0.2
0.4
1
ns
t
PHZ
Disable Time High to Z
R
L
= 100
(Figure 4 and Figure 5)
1.5
3
ns
t
PLZ
Disable Time Low to Z
1.5
3
ns
t
PZH
Enable Time Z to High
1
3
6
ns
t
PZL
Enable Time Z to Low
1
3
6
ns
f
MAX
Maximum Operating Frequency (Note 16)
200
250
MHz
LVCMOS Outputs (Receiver Outputs)
t
PHL
Propagation Delay High to Low
(Figure 6 and Figure 7)
0.5
2
3.5
ns
t
PLH
Propagation Delay Low to High
0.5
2
3.5
ns
t
SK1
Pulse Skew |t
PHL
- t
PLH
| (Note 10)
0
0.05
0.4
ns
t
SK2
Channel-to-Channel Skew (Note 11)
0
0.05
0.5
ns
t
SK3
Part-to-Part Skew (Note 12)
0
1.0
ns
t
TLH
Rise Time(Note 5)
0.3
0.9
1.4
ns
t
THL
Fall Time(Note 5)
0.3
0.75
1.4
ns
t
PHZ
Disable Time High to Z
(Figure 8 and Figure 9)
3
5.6
8
ns
t
PLZ
Disable Time Low to Z
3
5.4
8
ns
t
PZH
Enable Time Z to High
2.5
4.6
7
ns
t
PZL
Enable Time Z to Low
2.5
4.6
7
ns
f
MAX
Maximum Operating Frequency (Note 17)
200
250
MHz
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: V
TH
, V
TL
,
V
OD
and
V
OD
.
Note 3: Both, driver and receiver inputs are static. All LVDS outputs have 100
load. All LVCMOS outputs are floating. None of the outputs have any lumped
capacitive load.
Note 4: All typical values are given for: V
DD
= +3.3 V, T
A
= +25C.
Note 5: These parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage,
temperature) ranges.
Note 6: The DS90LV049's drivers are current mode devices and only function within datasheet specifications when a resistive load is applied to their outputs. The
typical range of the resistor values is 90
to 110 .
Note 7: t
SKD1
or differential pulse skew is defined as |t
PHLD
- t
PLHD
|. It is the magnitude difference in the differential propagation delays between the positive going
edge and the negative going edge of the same driver channel.
DS90L
V049
www.national.com
3
Switching Characteristics
(Continued)
Note 8: t
SKD2
or differential channel-to-channel skew is defined as the magnitude difference in the differential propagation delays between two driver channels on
the same device.
Note 9: t
SKD3
or differential part-to-part skew is defined as |t
PLHD Max
- t
PLHD Min
| or |t
PHLD Max
- t
PHLD Min
|. It is the difference between the minimum and maximum
specified differential propagation delays. This specification applies to devices at the same V
DD
and within 5C of each other within the operating temperature range.
Note 10: t
SK1
or pulse skew is defined as |t
PHL
- t
PLH
|. It is the magnitude difference in the propagation delays between the positive going edge and the negative
going edge of the same receiver channel.
Note 11: t
SK2
or channel-to-channel skew is defined as the magnitude difference in the propagation delays between two receiver channels on the same device.
Note 12: t
SK3
or part-to-part skew is defined as |t
PLH Max
- t
PLH Min
| or |t
PHL Max
- t
PHL Min
|. It is the difference between the minimum and maximum specified
propagation delays. This specification applies to devices at the same V
DD
and within 5C of each other within the operating temperature range.
Note 13: Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50
, t
r
1 ns, and t
f
1 ns.
Note 14: Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only.
Note 15: All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
Note 16: f
MAX
generator input conditions: t
r
= t
f
<
1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output Criteria: duty cycle = 45%/55%, V
OD
>
250 mV, all channels
switching.
Note 17: f
MAX
generator input conditions: t
r
= t
f
<
1 ns (0% to 100%), 50% duty cycle, V
ID
= 200 mV, V
CM
= 1.2 V . Output Criteria: duty cycle = 45%/55%, V
OH
>
2.7 V, V
OL
<
0.25 V, all channels switching.
Parameter Measurement Information
20042003
FIGURE 1. Driver V
OD
and V
OS
Test Circuit
20042004
FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit
DS90L
V049
www.national.com
4
Parameter Measurement Information
(Continued)
20042005
FIGURE 3. Driver Propagation Delay and Transition Time Waveforms
20042006
FIGURE 4. Driver TRI-STATE Delay Test Circuit
DS90L
V049
www.national.com
5
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