DS90LV032A
3V LVDS Quad CMOS Differential Line Receiver
General Description
The DS90LV032A is a quad CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion and high data rates. The device is designed to support
data rates in excess of 400 Mbps (200 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
The DS90LV032A accepts low voltage (350 mV typical) dif-
ferential input signals and translates them to 3V CMOS out-
put levels. The receiver supports a TRI-STATE
function that
may be used to multiplex outputs. The receiver also supports
open, shorted and terminated (100
) input Fail-safe. The re-
ceiver output will be HIGH for all fail-safe conditions.
The DS90LV032A and companion LVDS line driver (eg.
DS90LV031A) provide a new alternative to high power
PECL/ECL devices for high speed point-to-point interface
applications.
Features
n
>
400 Mbps (200 MHz) switching rates
n
0.1 ns channel-to-channel skew (typical)
n
0.1 ns differential skew (typical)
n
3.3 ns maximum propagation delay
n
3.3V power supply design
n
Power down high impedance on LVDS inputs
n
Low Power design (40mW 3.3V static)
n
Interoperable with existing 5V LVDS networks
n
Accepts small swing (350 mV typical) VID
n
Supports open, short and terminated input fail-safe
n
Compatible with ANSI/TIA/EIA-644
n
Industrial temp. operating range (-40C to +85C)
n
Available in SOIC and TSSOP Packaging
Connection Diagram
Functional Diagram
ENABLES
INPUTS
OUTPUT
EN
EN*
R
IN+
- R
IN-
R
OUT
L
H
X
Z
All other combinations
V
ID
0.1V
H
of ENABLE inputs
V
ID
-0.1V
L
Full Fail-safe
OPEN/SHORT
H
or Terminated
Dual-in-Line
DS100067-1
Order Number DS90LV032ATM
or DS90LV032ATMTC
See NS Package Number M16A or MTC16
DS100067-2
July 1999
DS90L
V032A
3V
L
VDS
Quad
CMOS
Differential
Line
Receiver
1999 National Semiconductor Corporation
DS100067
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.3V to +4V
Input Voltage (R
IN+
, R
IN-
)
-0.3V to +3.9V
Enable Input Voltage (EN, EN*)
-0.3V to (V
CC
+ 0.3V)
Output Voltage (R
OUT
)
-0.3V to (V
CC
+ 0.3V)
Maximum Package Power Dissipation +25C
M Package
1025 mW
MTC Package
866 mW
Derate M Package
8.2 mW/C above +25C
Derate MTC Package
6.9 mW/C above +25C
Storage Temperature Range
-65C to +150C
Lead Temperature Range
(Soldering 4 sec.)
+260C
Maximum Junction Temperature
+150C
ESD Rating (Note 10)
(HBM 1.5 k
, 100 pF)
4.5 kV
(EIAJ 0
, 200 pF)
250 V
Recommended Operating
Conditions
Min
Typ
Max
Units
Supply Voltage (V
CC
)
+3.0
+3.3
+3.6
V
Receiver Input Voltage
GND
+3.0
V
Operating Free Air
Temperature (T
A
)
-40
25
+85
C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 2)
Symbol
Parameter
Conditions
Pin
Min
Typ
Max
Units
V
TH
Differential Input High Threshold
V
CM
= +1.2V
(Note 13)
R
IN+
,
R
IN-
+20
+100
mV
V
TL
Differential Input Low Threshold
-100
-20
mV
VCMR
Common-Mode Voltage Range
VID = 200 mV peak to peak (Note 5)
0.1
2.3
V
I
IN
Input Current
V
IN
= +2.8V
V
CC
= 3.6V or 0V
-10
1
+10
A
V
IN
= 0V
-10
1
+10
A
V
IN
= +3.6V
V
CC
= 0V
-20
+20
A
V
OH
Output High Voltage
I
OH
= -0.4 mA, V
ID
= +200 mV
R
OUT
2.7
3.0
V
I
OH
= -0.4 mA, Input terminated
2.7
3.0
V
I
OH
= -0.4 mA, Input shorted
2.7
3.0
V
V
OL
Output Low Voltage
I
OL
= 2 mA, V
ID
= -200 mV
0.1
0.25
V
I
OS
Output Short Circuit Current
Enabled, V
OUT
= 0V (Note 11)
-15
-48
-120
mA
I
OZ
Output TRI-STATE Current
Disabled, V
OUT
= 0V or V
CC
-10
1
+10
A
V
IH
Input High Voltage
EN,
EN*
2.0
V
CC
V
V
IL
Input Low Voltage
GND
0.8
V
I
I
Input Current
V
IN
= 0V or V
CC
, Other Input = V
CC
or
GND
-10
1
+10
A
V
CL
Input Clamp Voltage
I
CL
= -18 mA
-1.5
-0.8
V
I
CC
No Load Supply Current
EN, EN* = V
CC
or GND, Inputs Open
V
CC
10
15
mA
Receivers Enabled
EN, EN* = 2.4V or 0.5V, Inputs Open
10
15
mA
I
CCZ
No Load Supply Current
Receivers Disabled
EN = GND, EN* = V
CC
, Inputs Open
3
5
mA
Switching Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 3, 4, 7, 8)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHLD
Differential Propagation Delay High to Low
C
L
= 10 pF
1.8
3.3
ns
t
PLHD
Differential Propagation Delay Low to High
V
ID
= 200 mV
1.8
3.3
ns
t
SKD1
Differential Pulse Skew |t
PHLD
- t
PLHD
| (Note 6)
(
Figure 1 and Figure 2)
0
0.1
0.35
ns
t
SKD2
Differential Channel-to-Channel Skew-same device
(Note 7)
0
0.1
0.5
ns
t
SKD3
Differential Part to Part Skew (Note 8)
1.0
ns
t
SKD4
Differential Part to Part Skew (Note 9)
1.5
ns
t
TLH
Rise Time
0.35
1.2
ns
t
THL
Fall Time
0.35
1.2
ns
www.national.com
2
Switching Characteristics
(Continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 3, 4, 7, 8)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHZ
Disable Time High to Z
R
L
= 2 k
8
12
ns
t
PLZ
Disable Time Low to Z
C
L
= 10 pF
6
12
ns
t
PZH
Enable Time Z to High
(
Figure 3 and Figure 4)
11
17
ns
t
PZL
Enable Time Z to Low
11
17
ns
f
MAX
Maximum Operating Frequency (Note 14)
All Channels Switching
200
250
MHz
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise speci-
fied.
Note 3: All typicals are given for: V
CC
= +3.3V, T
A
= +25C.
Note 4: Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50
, t
r
and t
f
(0% to 100%)
3 ns for R
IN
.
Note 5: The VCMR range is reduced for larger VID. Example: if VID = 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs shorted is valid over
a common-mode range of 0V to 2.3V. A VID up to V
CC
- 0V may be applied to the R
IN+
/ R
IN-
inputs with the Common-Mode voltage set to V
CC
/2. Propagation delay
and Differential Pulse skew decrease when VID is increased from 200mV to 400mV. Skew specifications apply for 200mV
VID
800mV over the common-mode
range .
Note 6: t
SKD1
is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel
Note 7: t
SKD2
, Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with
any event on the inputs.
Note 8: t
SKD3
, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V
CC
,
and within 5C of each other within the operating temperature range.
Note 9: t
SKD4
, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
operating temperature and voltage ranges, and across process distribution. t
SKD4
is defined as |Max - Min| differential propagation delay.
Note 10: ESD Rating:
HBM (1.5 k
, 100 pF)
4.5kV
EIAJ (0
, 200 pF)
250V
Note 11: Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not
exceed maximum junction temperature specification.
Note 12: C
L
includes probe and jig capacitance.
Note 13: V
CC
is always higher than R
IN+
and R
IN-
voltage. R
IN-
and R
IN+
are allowed to have a voltage range -0.2V to V
CC
- VID/2. However, to be compliant with
AC specifications, the common voltage range is 0.1V to 2.3V
Note 14: f
MAX
generator input conditions: t
r
= t
f
<
1ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35V peak to peak). Output Criteria: 60%/40% duty cycle,
V
OL
(max 0.4V), V
OH
(min 2.7V), Load = 10 pF (stray plus probes)
Parameter Measurement Information
DS100067-3
FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
DS100067-4
FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms
www.national.com
3
Parameter Measurement Information
(Continued)
Typical Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner's Manual (lit #550062-001), AN808,
AN1035, AN977, AN971, AN916, AN805, AN903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in
Figure 5. This configuration provides a clean signaling en-
vironment for the fast edge rates of the drivers . The receiver
is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically the characteristic impedance of
the media is in the range of 100
. A termination resistor of
100
should be selected to match the media, and is located
as close to the receiver input pins as possible. The termina-
tion resistor converts the driver output (current mode) into a
voltage that is detected by the receiver. Other configurations
are possible such as a multi-receiver configuration, but the
effects of a mid-stream connector(s), cable stub(s), and
other impedance discontinuities as well as ground shifting,
noise margin limits, and total termination loading must be
taken into account.
DS100067-5
C
L
includes load and test jig capacitance.
S
1
= V
CC
for t
PZL
, and t
PLZ
measurements.
S
1
= GND for t
PZH
and t
PHZ
measurements.
FIGURE 3. Receiver TRI-STATE Delay Test Circuit
DS100067-6
FIGURE 4. Receiver TRI-STATE Delay Waveforms
Balanced System
DS100067-7
FIGURE 5. Point-to-Point Application
www.national.com
4
Applications Information
(Continued)
The DS90LV032A differential line receiver is capable of de-
tecting signals as low as 100 mV, over a
1V common-mode
range centered around +1.2V. This is related to the driver off-
set voltage which is typically +1.2V. The driven signal is cen-
tered around this voltage and may shift
1V around this cen-
ter point. The
1V shifting may be the result of a ground
potential difference between the driver's ground reference
and the receiver's ground reference, the common-mode ef-
fects of coupled noise, or a combination of the two. Both re-
ceiver input pins have a recommended operating input volt-
age range of 0V to +2.4V (measured from each pin to
ground), exceeding these limits may turn on the ESD protec-
tion circuitry which will clamp the bus voltages.
Power Decoupling Recommendations:
Bypass capacitors must be used on power pins. High fre-
quency ceramic (surface mount is recommended) 0.1F in
parallel with 0.01F, in parallel with 0.001F at the power
supply pin as well as scattered capacitors over the printed
circuit board. Multiple vias should be used to connect the de-
coupling capacitors to the power planes A 10F (35V) or
greater solid tantalum capacitor should be connected at the
power entry point on the printed circuit board.
PC Board considerations:
Use at least 4 PCB layers (top to bottom); LVDS signals,
ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
may couple onto the LVDS lines. It is best to put TTL and
LVDS signals on different layers which are isolated by a
power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
Differential Traces:
Use controlled impedance traces which match the differen-
tial impedance of your transmission medium (ie. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
(stubs should be
<
10mm long). This will help eliminate re-
flections and ensure noise is coupled as common-mode. In
fact, we have seen that differential signals which are 1mm
apart radiate far less noise than traces 3mm apart since
magnetic field cancellation is much better with the closer
traces. Plus, noise induced on the differential lines is much
more likely to appear as common-mode which is rejected by
the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase differ-
ence between signals which destroys the magnetic field can-
cellation benefits of differential signals and EMI will result.
(Note the velocity of propagation, v = c/Er where c (the
speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely
solely on the autoroute function for differential traces. Care-
fully review dimensions to match differential impedance and
provide isolation for the differential lines. Minimize the num-
ber or vias and other discontinuities on the line.
Avoid 90 turns (these cause impedance discontinuities).
Use arcs or 45 bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow-
able.
Termination:
Use a resistor which best matches the differential impedance
or your transmission line. The resistor should be between
90
and 130
. Remember that the current mode outputs
need the termination resistor to generate the differential volt-
age. LVDS will not work without resistor termination. Typi-
cally, connect a single resistor across the pair at the receiver
end.
Surface mount 1% to 2% resistors are best. PCB stubs,
component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be
<
10mm
(12mm MAX)
Probing LVDS Transmission Lines:
Always use high impedance (
>
100k
), low capacitance
(
<
2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
Cables and Connectors, General Comments:
When choosing cable and connectors for LVDS it is impor-
tant to remember:
Use controlled impedance media. The cables and connec-
tors you use should have a matched differential impedance
of about 100
. They should not introduce major impedance
discontinuities.
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax.) for noise re-
duction and signal quality. Balanced cables tend to generate
less EMI due to field canceling effects and also tend to pick
up electromagnetic radiation a common-mode (not differen-
tial mode) noise which is rejected by the receiver. For cable
distances
<
0.5M, most cables can be made to work effec-
tively. For distances 0.5M
d
10M, CAT 3 (category 3)
twisted pair cable works well, is readily available and rela-
tively inexpensive.
Fail-Safe Feature:
The LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to CMOS logic
levels. Due to the high gain and tight threshold of the re-
ceiver, care should be taken to prevent noise from appearing
as a valid signal.
The receiver's internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating, terminated or shorted receiver inputs.
1.
Open Input Pins. The DS90LV032A is a quad receiver
device, and if an application requires only 1, 2 or 3 re-
ceivers, the unused channel(s) inputs should be left
OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high
value pull up and pull down resistors to set the output to
a HIGH state. This internal circuitry will guarantee a
HIGH, stable output state for open inputs.
2.
Terminated Input. If the driver is disconnected (cable
unplugged), or if the driver is in a TRI-STATE or power-
off condition, the receiver output will again be in a HIGH
state, even with the end of cable 100
termination resis-
tor across the input pins. The unplugged cable can be-
come a floating antenna which can pick up noise. If the
cable picks up more than 10mV of differential noise, the
receiver may see the noise as a valid signal and switch.
To insure that any noise is seen as common-mode and
not differential, a balanced interconnect should be used.
Twisted pair cable will offer better balance than flat rib-
bon cable.
www.national.com
5
Applications Information
(Continued)
3.
Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V differ-
ential input voltage, the receiver output will remain in a
HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to
2.4V). It is only supported with inputs shorted and no ex-
ternal common-mode voltage applied.
External lower value pull up and pull down resistors (for a
stronger bias) may be used to boost fail-safe in the presence
of higher noise levels. The pull up and pull down resistors
should be in the 5k
to 15k
range to minimize loading and
waveform distortion to the driver. The common-mode bias
point should be set to approximately 1.2V (less than 1.75V)
to be compatible with the internal circuitry.
The footprint of the DS90LV032A is the same as the industry
standard 26LS32 Quad Differential (RS-422) Receiver.
Pin Descriptions
Pin
No.
Name
Description
2, 6,
R
IN+
Non-inverting receiver input pin
Pin
No.
Name
Description
10, 14
1, 7,
R
IN-
Inverting receiver input pin
9, 15
3, 5,
R
OUT
Receiver output pin
11, 13
4
EN
Active high enable pin, OR-ed with
EN*
12
EN*
Active low enable pin, OR-ed with EN
16
V
CC
Power supply pin, +3.3V
0.3V
8
GND
Ground pin
Ordering Information
Operating
Package Type/
Order Number
Temperature
Number
-40C to +85C
SOP/M16A
DS90LV032ATM
-40C to +85C
TSSOP/MTC16 DS90LV032ATMTC
DS100067-8
FIGURE 6. ICC vs Frequency, four channels switching
DS100067-9
FIGURE 7. Typical Common-Mode Range variation with respect to amplitude of differential input
www.national.com
6
Applications Information
(Continued)
DS100067-10
FIGURE 8. Typical Pulse Skew variation versus common-mode voltage
DS100067-11
FIGURE 9. Variation in High to Low Propagation Delay versus VCM
DS100067-12
FIGURE 10. Variation in Low to High Propagation Delay versus VCM
www.national.com
7
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC
Order Number DS90LV032ATM
NS Package Number M16A
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8
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
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COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
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www.national.com
16-Lead (0.100" Wide) Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90LV032ATMTC
NS Package Number MTC16
DS90L
V032A
3V
L
VDS
Quad
CMOS
Differential
Line
Receiver
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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