TL F 11109
DP8420V21V22V-33
DP84T22-25
microCMOS
Programmable
256k1M4M
Dynamic
RAM
ControllerDrivers
May 1992
DP8420V 21V 22V-33 DP84T22-25 microCMOS
Programmable 256k 1M 4M Dynamic RAM
Controller Drivers
General Description
The DP8420V 21V 22V-33
DP84T22-25 dynamic RAM
controllers provide a low cost single chip interface between
dynamic RAM and all 8- 16- and 32-bit systems The
DP8420V 21V 22V-33 DP84T22-25 generate all the re-
quired access control signal timing for DRAMs An on-chip
refresh request clock is used to automatically refresh the
DRAM array Refreshes and accesses are arbitrated on
chip If necessary a WAIT or DTACK output inserts wait
states into system access cycles including burst mode ac-
cesses RAS low time during refreshes and RAS precharge
time after refreshes and back to back accesses are guaran-
teed through the insertion of wait states Separate on-chip
precharge counters for each RAS output can be used for
memory interleaving to avoid delayed back to back access-
es because of precharge An additional feature of the
DP8422V DP84T22 is two access ports to simplify dual ac-
cessing Arbitration among these ports and refresh is done
on chip To make board level circuit testing easier the
DP84T22 incorporates TRI-STATE
output buffers
Features
Y
On chip high precision delay line to guarantee critical
DRAM access timing parameters
Y
microCMOS process for low power
Y
High capacitance drivers for RAS CAS WE and DRAM
address on chip
Y
On chip support for nibble page and static column
DRAMs
Y
TRI-STATE outputs (DP84T22 only)
Y
Byte enable signals on chip allow byte writing in a word
size up to 32 bits with no external logic
Y
Selection of controller speeds 25 MHz and 33 MHz
Y
On board Port A Port B (DP8422V DP84T22 only) re-
fresh arbitration logic
Y
Direct interface to all major microprocessors (applica-
tion notes available)
Y
4 RAS and 4 CAS drivers (the RAS and CAS configura-
tion is programmable)
of Pins
of Address
Largest
Direct Drive
Access
Control
(PLCC)
Outputs
DRAM
Memory
Ports
Possible
Capacity
Available
DP8420V
68
9
256 kbit
4 Mbytes
Single Access Port
DP8421V
68
10
1 Mbit
16 Mbytes
Single Access Port
DP8422V
84
11
4 Mbit
64 Mbytes
Dual Access Ports (A and B)
DP84T22
84
11
4 Mbit
64 Mbytes
Dual Access and TRI-STATE
Block Diagram
DP8420V 21V 22V DP74T22 DRAM Controller
TL F 11109 1
FIGURE 1
TRI-STATE
is a registered trademark of National Semiconductor Corporation
Staggered Refresh
TM
is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Table of Contents
1 0 INTRODUCTION
2 0 SIGNAL DESCRIPTIONS
2 1 Address R W and Programming Signals
2 2 DRAM Control Signals
2 3 Refresh Signals
2 4 Port A Access Signals
2 5 Port B Access Signals (DP8422V DP84T22)
2 6 Common Dual Port Signals (DP8422V DP84T22)
2 7 Power Signals and Capacitor Input
2 8 Clock Inputs
3 0 PROGRAMMING AND RESETTING
3 1 External Reset
3 2 Programming Methods
3 2 1 Mode Load Only Programming
3 2 2 Chip Selected Access Programming
3 3 Internal Programming Modes
4 0 PORT A ACCESS MODES
4 1 Access Mode 0
4 2 Access Mode 1
4 3 Extending CAS with Either Access Mode
4 4 Read-Modify-Write Cycles with Either Access Mode
4 5 Additional Access Support Features
4 5 1 Address Latches and Column Increment
4 5 2 Address Pipelining
4 5 3 Delay CAS during Write Accesses
5 0 REFRESH OPTIONS
5 1 Refresh Control Modes
5 1 1 Automatic Internal Refresh
5 1 2 Externally Controlled Burst Refresh
5 1 3 Refresh Request Acknowledge
5 2 Refresh Cycle Types
5 2 1 Conventional Refresh
5 2 2 Staggered Refresh
TM
5 2 3 Error Scrubbing Refresh
5 3 Extending Refresh
5 4 Clearing the Refresh Address Counter
5 5 Clearing the Refresh Request Clock
6 0 PORT A WAIT STATE SUPPORT
6 1 WAIT Type Output
6 2 DTACK Type Output
6 3 Dynamically Increasing the Number of Wait States
6 4 Guaranteeing RAS Low Time and RAS Precharge
Time
7 0 RAS AND CAS CONFIGURATION MODES
7 1 Byte Writing
7 2 Memory Interleaving
7 3 Address Pipelining
7 4 Error Scrubbing
7 5 Page Burst Mode
8 0 TEST MODE
9 0 DRAM CRITICAL TIMING PARAMETERS
9 1 Programmable Values of t
RAH
and t
ASC
9 2 Calculation of t
RAH
and t
ASC
10 0 DUAL ACCESSING (DP8422V and DP84T22V)
10 1 Port B Access Mode
10 2 Port B Wait State Support
10 3 Common Port A and Port B Dual Port Functions
10 3 1 GRANTB Output
10 3 2 LOCK Input
10 4 TRI-STATE Outputs (DP84T22 Only)
11 0 ABSOLUTE MAXIMUM RATINGS
12 0 DC ELECTRICAL CHARACTERISTICS
13 0 AC TIMING PARAMETERS
14 0 FUNCTIONAL DIFFERENCES BETWEEN THE
DP8420V 21V 22V DP84T22 AND THE
DP8420 21 22
15 0 DP8420V 21V 22V DP84T22 USER HINTS
2
1 0 Introduction
The DP8420V 21V 22V DP84T22 are CMOS Dynamic
RAM controllers that incorporate many advanced features
which include address latches refresh counter refresh
clock row column and refresh address multiplexer delay
line refresh access arbitration logic and high capacitive
drivers The programmable system interface allows any
manufacturer's microprocessor or bus to directly interface
via the DP8420V 21V 22V DP84T22 to DRAM arrays up to
64 Mbytes in size
After power up the user must first reset and program the
DP8420V 21V 22V DP84T22 before accessing the DRAM
The chip is programmed through the address bus
Reset
Due to the differences in power supplies an External (hard-
ware) Reset must be performed before programming the
chip
Programming
After resetting the chip the user can program the controller
by either one of two methods Mode Load Only Program-
ming or Chip Select Access Programming
Initialization Period
Once the DP8420V 21V 22V DP84T22 has been pro-
grammed for the first time a 60 ms initialization period is
entered During this time the DRC performs refreshes to the
DRAM array so further warm up cycles are unnecessary
The initialization period is entered only after the first pro-
gramming after a reset
Accessing Modes
After
resetting
and
programming
the
chip
the
DP8420V 21V 22V
DP84T22 is ready to access the
DRAM There are two modes of accessing with these con-
trollers Mode 0 which indicates RAS synchronously and
Mode 1 which indicates RAS asynchronously
Refresh Modes
The DP8420V 21V 22V DP84T22 have expanded refresh
capabilities compared to previous DRAM controllers There
are three modes of refreshing available Internal Automatic
Refreshing Externally Controlled Burst Refreshing and Re-
fresh Request Acknowledge Refreshing
Any of these
modes can be used together or separately to achieve the
desired results
Refresh Types
These controllers have three types of refreshing available
Conventional Staggered and Error Scrubbing Any refresh
control mode can be used with any type of refresh
Wait Support
The DP8420V 21V 22V DP84T22 have wait support avail-
able as DTACK or WAIT Both are programmable DTACK
Data Transfer ACKnowledge
is useful for processors
whose wait signal is active high WAIT is useful for those
processors whose wait signal is active low The user can
choose either at programming These signals are used by
the on chip arbiter to insert wait states to guarantee the
arbitration between accesses refreshes and precharge
Both signals are independent of the access mode chosen
and both signals can be dynamically delayed further through
the WAITIN signal to the DP8420V 21V 22V DP84T22
Sequential Accesses (Static Column Page Mode)
The DP8420V 21V 22V DP84T22 have address latches
used to latch the bank row and column address inputs
Once the address is latched a COLumn INCrement (COL-
INC) feature can be used to increment the column address
The address latches can also be programmed to be fall
through COLINC can be used for Sequential Accesses of
Static Column DRAMs Also COLINC in conjunction with
ECAS inputs can be used for Sequential Accesses to Page
Mode DRAMs
RAS and CAS Configuration (Byte Writing)
The RAS and CAS drivers can be configured to drive a one
two or four bank memory array up to 32 bits in width The
ECAS signals can then be used to select one of four CAS
drivers for Byte Writing with no extra logic
Memory Interleaving
When configuring the DP8420V 21V 22V DP84T22 for
more than one bank Memory Interleaving can be used By
tying the low order address bits to the bank select lines B0
and B1 sequential back to back accesses will not be de-
layed since these controllers have separate precharge
counters per bank
Address Pipelining
The DP8420V 21V 22V DP84T22 are capable of perform-
ing Address Pipelining In address pipelining the DRC will
guarantee the column address hold time and switch the in-
ternal multiplexor to place the row address on the address
bus At this time another memory access to another bank
can be initiated
Dual Accessing
The DP8422V DP84T22 have all the features previously
mentioned and unlike the DP8420V 21V the DP8422V
DP84T22 have a second port to allow a second CPU to
access the same memory array The DP8422V DP84T22
have four signals to support Dual Accessing these signals
are AREQB ATACKB LOCK and GRANTB All arbitration
for the two ports and refresh is done on chip by the control-
ler through the insertion of wait states Since the DP8422V
DP84T22 have only one input address bus the address
lines must be multiplexed externally The signal GRANTB
can be used for this purpose
TRI-STATE Outputs
The DP84T22 implements TRI-STATE outputs When the
input OE is asserted the output buffers are enabled when
OE is negated logic 1 the output buffers at TRI-STATE
(high Z)
Terminology
The following explains the terminology used in this data
sheet The terms negated and asserted are used Asserted
refers to a ``true'' signal Thus ``ECAS0 asserted'' means
the ECAS0 input is at a logic 0 The term ``COLINC assert-
ed'' means the COLINC input is at a logic 1 The term negat-
ed refers to a ``false'' signal Thus ``ECAS0 negated''
means the ECAS0 input is at a logic 1 The term ``COLINC
negated'' means the input COLINC is at a logic 0 The table
shown below clarifies this terminology
Signal
Action
Logic Level
Active High
Asserted
High
Active High
Negated
Low
Active Low
Asserted
Low
Active Low
Negated
High
3
Connection Diagrams
TL F 11109 2
Top View
FIGURE 2
Order Number DP8420V-33
See NS Package Number V68A
TL F 11109 3
Top View
FIGURE 3
Order Number DP8421V-33
See NS Package Number V68A
TL F 11109 4
Top View
FIGURE 4
Order Number DP8422V-33 or DP84T22-25
See NS Package Number V84A
4
2 0 Signal Descriptions
Pin
Device (If Not
Input
Description
Name
Applicable to All)
Output
2 1 ADDRESS R W AND PROGRAMMING SIGNALS
R0 10
DP8422V T22
I
ROW ADDRESS
These inputs are used to specify the row address during an access
to the DRAM They are also used to program the chip when ML is asserted (except
R0 9
DP8420V 21V
I
R10)
C0 10
DP8422V T22
I
COLUMN ADDRESS
These inputs are used to specify the column address during an
access to the DRAM They are also used to program the chip when ML is asserted
C0 9
DP8420V 21V
I
(except C10)
B0 B1
I
BANK SELECT
Depending on programming these inputs are used to select a group
of RAS and CAS outputs to assert during an access They are also used to program
the chip when ML is asserted
ECAS0 3
I
ENABLE CAS
These inputs are used to enable a single or group of CAS outputs
when asserted In combination with the B0 B1 and the programming bits these
inputs select which CAS output or CAS outputs will assert during an access The
ECAS signals can also be used to toggle a group of CAS outputs for page nibble
mode accesses They also can be used for byte write operations If ECAS0 is
negated during programming continuing to assert the ECAS0 while negating AREQ
or AREQB during an access will cause the CAS outputs to be extended while the
RAS outputs are negated (the ECASn inputs have no effect during scrubbing
refreshes)
WIN
I
WRITE ENABLE IN
This input is used to signify a write operation to the DRAM If
ECAS0 is asserted during programming the WE output will follow this input This
input asserted will also cause CAS to delay to the next positive clock edge if address
bit C9 is asserted during programming
COLINC
I
COLUMN INCREMENT
When the address latches are used and RFIP is negated
this input functions as COLINC Asserting this signal causes the column address to
(EXTNDRF)
I
be incremented by one When RFIP is asserted this signal is used to extend the
refresh cycle by any number of periods of CLK until it is negated
ML
I
MODE LOAD
This input signal when low enables the internal programming register
that stores the programming information
2 2 DRAM CONTROL SIGNALS
Q0 10
DP8422V T22
O
DRAM ADDRESS
These outputs are the multiplexed output of the R0 9 10 and
C0 9 10 and form the DRAM address bus These outputs contain the refresh
Q0 9
DP8421V
O
address whenever RFIP is asserted They contain high capacitive drivers with 20X
Q0 8
DP8421V
O
series damping resistors
RAS0 3
O
ROW ADDRESS STROBES
These outputs are asserted to latch the row address
contained on the outputs Q0 8 9 10 into the DRAM When RFIP is asserted the
RAS outputs are used to latch the refresh row address contained on the Q0 8 9 10
outputs in the DRAM These outputs contain high capacitive drivers with 20X series
damping resistors
CAS0 3
O
COLUMN ADDRESS STROBES
These outputs are asserted to latch the column
address contained on the outputs Q0 8 9 10 into the DRAM These outputs have
high capacitive drivers with 20X series damping resistors
WE
O
WRITE ENABLE
or REFRESH REQUEST This output asserted specifies a write
operation to the DRAM When negated this output specifies a read operation to the
(RFRQ)
O
DRAM When the controller is programmed in address pipelining mode or when
ECAS0 is negated during programming this output will function as RFRQ When
asserted this pin specifies that 13 ms or 15 ms have passed If DISRFSH is negated
the DP8420V 21V 22V DP84T22 will perform an internal refresh as soon as
possible If DISRFRSH is asserted RFRQ can be used to externally request a refresh
through the input RFSH This output has a high capacitive driver and a 20X series
damping resistor
OE
DP84T22
I
OUTPUT ENABLE
This input asserted enables the output buffers for the row
column RASs CASs and WE If this input is disabled logic 1 the output buffers are at
(Only)
TRI-STATE facilitating the board level circuit testing
5
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