Document Outline
- COVER
- FEATURES
- ORDERING INFORMATION
- BLOCK DIAGRAMS
- PIN CONFIGURATION
- PIN NAME
- 1. PIN FUNCTIONS
- 1.1 PCI/Cardbus Interface Signals: (52 pins)
- 1.2 Cable Interface Signals: (15 pins)
- 1.3 PHY Signals: (9 pins)
- 1.4 PHY Control Signals: (5 pins)
- 1.5 PCI/Cardbus Select Signals: (2 pins)
- 1.6 Serial ROM Interface Signals: (3 pins)
- 1.7 Miscellaneous Signals: (1 pin)
- 1.8 IC: ( 21 pins)
- 1.9 VDD
- 1.10 GND
- 2. PHY REGISTERS
- 2.1 Complete Structure for PHY Registers
- 2.2 Port Status Page (Page 000)
- 2.3 Vendor ID Page (Page 001)
- 3. CONFIGURATION REGISTERS
- 3.1 PCI Bus Mode Configuration Register ( CARD_ON=Low )
- 3.1.1 Offset_00 Vendor ID Register
- 3.1.2 Offset_02 DeviceID Register
- 3.1.3 Offset_04 Command Register
- 3.1.4 Offset_06 Status Register
- 3.1.5 Offset_08 Revision ID Register
- 3.1.6 Offset_09 Class Code Register
- 3.1.7 Offset_0C Cache Line Size Register
- 3.1.8 Offset_0D Latency Timer Register
- 3.1.9 Offset_0E Header Type Register
- 3.1.10 Offset_0F BIST Register
- 3.2 CardBus Mode Configuration Register ( CARD_ON=High )
- 3.2.1 Offset_14/18 Base_Address_1/2 Register (CardBus Status Registers)
- 3.2.2 Offset_28 Cardbus CIS Pointer
- 3.2.3 Offset_80 CIS Area
- 4. PHY FUNCTION
- 4.1 Cable Interface
- 4.1.1 Connections
- 4.1.2 Cable Interface Circuit
- 4.1.3 CPS
- 4.1.4 Unused Ports
- 4.2 PLL and Crystal Oscillation Circuit
- 4.2.1 Crystal Oscillation Circuit
- 4.2.2 PLL
- 4.3 PC0-PC2, CMC
- 4.4 P_RESETB#
- 4.5 RI0, RI1
- 5. SERIAL ROM INTERFACE
- 5.1 Serial EEPROM Register
- 5.2 Serial EEPROM Register Description
- 5.3 Load Control
- 6. ELECTRICAL SPECIFICATIONS
- 7. APPLICATION CIRCUIT EXAMPLE
- 8. PACKAGE DRAWINGS
1999
IEEE1394 1-CHIP OHCI HOST CONTROLLER
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD72870,72871
Document No. S13925EJ2V0DS00 (2nd edition)
Date Published September 1999 NS CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The
PD72870, 72871 are the LSIs which integrated OHCI-Link and PHY function into a single chip.
The
PD72870, 72871 comply with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0 and work
up to 400 Mbps.
These make design so compact for PC and PC card application.
FEATURES
Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0
Compliant with Physical Layer Services as defined in P1394a draft 2.0 (Data Rate 100/200/400 Mbps)
3-port :
PD72870
1-port :
PD72871
Compliant with protocol enhancement as defined in P1394a draft 2.0
Modular 32-bit host interface compliant to PCI Specification release 2.1
Support PCI-Bus Power Management Interface Specification release 1.0
Modular 32-bit host interface compliant to Card Bus Specification
Cycle Master and Isochronous Resource Manager capable
Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048
bytes)
32-bit CRC generation and checking for receive/transmit packets
4 isochronous transmit DMAs and 4 isochronous receive DMAs supported
32-bit DMA channels for physical memory read/write
Clock generation by 24.576 MHz X'tal
Internal control and operational registers direct-mapped to PCI configuration space
2-wire Serial EEPROM
TM
interface supported
Separate power supply Link and PHY
ORDERING INFORMATION
Part number
Package
PD72870GM-8ED
PD72870F1-FA2
PD72871GM-8ED
PD72871 F1-FA2
160-pin plastic LQFP (Fine pitch) (24 x 24 mm)
192-pin Plastic FBGA (14 x 14 mm)
160-pin plastic LQFP (Fine pitch) (24 x 24 mm)
192-pin Plastic FBGA (14 x 14 mm)
The mark
5
5
5
5
shows major revised points.
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
2
PD72870,72871
BLOCK DIAGRAMS
Top Block Diagram
Serial ROM Interface
Cable
Interface
PCI Bus/
Cardbus
PHY Signal
Link
PHY
Preliminary Data Sheet S13925EJ2V0DS00
3
PD72870,72871
PHY Block Diagram
Link
Interface
I/O
Voltage
and
Current
Generator
Cable
Power
Status
Crystal
Oscillator
PLL
System
and
Transmit
Clock
Generator
Receive Data
Decoder and
Retimer
Transmit Data
Encoder
Arbitration
and Control
State Machine
Logic
PHY/Link
Interface
Cable
Interface
Cable
Port1
Cable
Port2
Cable
Port3
PHY
Signal
Remark Cable Port:
PHY Control
Signal
(CMC,PC0-PC2)
Preliminary Data Sheet S13925EJ2V0DS00
4
PD72870,72871
Link Block Diagram
Serial ROM Interface
OPCI Internal Bus
PCIS Bus (PCI Slave Bus)
PCI Controller Interface
(Master, Parity Check & Generator)
PCI-DMA
CSR
(CIS)
PFCOMM
IOREG
Byte
Swap
Buf
PCIS_CNT
PCICFG
OPCIBUS_ARB
ATDMA
PAU
GRSU
GRQU
IRDMA0-
IRDMA3
ITDMA
SFIDU
Byte
Swap
Byte
Swap
Byte
Swap
ATF
ITF
ITCF
RF
RCF
IOREG
Link Layer
Core
PH
Y/L
i
n
k
In
te
r
f
a
c
e
PC
I Bu
s
/
C
a
r
d
b
u
s In
te
r
f
a
c
e
ATDMA
: Asynchronous Transmit DMA
ATF
: Asynchronous Transmit FIFO
CIS
: CIS Register
CSR
: Control and Status Registers
IOREG
: IO Registers
IRDMA
: Isochronous Receive DMA
ITCF
: Isochronous Transmit Control FIFO
ITDMA
: Isochronous Transmit DMA
ITF
: Isochronous Transmit FIFO
OPCIBUS_ARB
: OPCI Internal Bus Arbitration
PAU
: Physical Response and Request Unit
PCICFG
: PCI Configuration Registers
PCIS_CNT
: PHY Control Isochronous Control
PFCOMM
: Pre Fetch Command FIFO
RCF
: Receive Control FIFO
RF
: Receive FIFO
SFIDU
: Self-ID DMA
Preliminary Data Sheet S13925EJ2V0DS00
5
PD72870,72871
PIN CONFIGURATION
160-pin plastic LQFP (Fine pitch) (24 x 24 mm)
PD72870GM-8ED
GROM_SDA
P _ A V
D D
A G N D
X O
XI
P _ A V
D D
FIL0
FIL1
A G N D
A G N D
P _ A V
D D
P _ A V
D D
L_V
D D
C L K R U N
P M E
INTA
P R S T
P C L K
G N T
R E Q
D G N D
A D 3 1
A D 3 0
PCI_V
D D
A D 2 9
D G N D
A D 2 7
A D 2 6
A D 2 5
A D 2 8
A D 2 4
L_V
D D
D G N D
C B E 3
IDSEL
A D 2 3
A D 2 2
A D 2 1
A D 2 0
D G N D
A D 1 9
A D 1 8
PCI_V
D D
A D 1 7
A D 1 6
D G N D
C B E 2
F R A M E
IRDY
D E V S E L
T R D Y
L_V
D D
DGND
L_V
DD
DGND
DGND
DGND
STOP
AD15
AD14
PCI_V
DD
AD13
AD12
AD11
AD10
AD9
AD8
DGND
L_V
DD
CBE0
AD7
AD6
AD5
AD4
DGND
AD3
AD2
PCI_V
DD
AD1
AD0
IC(N)
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
14
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
39
38
40
41
42
43
44
45
46
47
48
49
50
51
52
53
55
56
57
58
54
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
79
78
80
120
160
159
158
157
156
155
154
153
152
151
150
149
148
146
145
144
143
147
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
122
123
121
PERR
SERR
PAR
L_V
DD
CBE1
P _ R E S E T B
P_DV
DD
IC(L)
IC(L)
CARD_ON
CIS_ON
GROM_EN
GROM_SCL
DGND
L_V
DD
DGND
P_AV
DD
P_AV
DD
RI1
AGND
AGND
TpA0p
TpA0n
TpB0p
TpB0n
TpA1p
TpA1n
TpB1p
TpB1n
TpA2p
TpA2n
TpB2p
TpB2n
TpBias0
TpBias1
TpBias2
P_AV
DD
AGND
CPS
RI0
AGND
AGND
IC(N)
PIN_EN
IC(N)
IC(N)
IC(N)
L_V
D D
S U S _ R E S M
P _ D V
D D
IC(L)
C M C
D G N D
D G N D
IC(H)
IC(H)
D G N D
P _ D V
D D
P C 2
P C 1
P C 0
IC(N)
D G N D
IC(N)
IC(N)
IC(N)
IC(N)
IC(N)
P O R T D I S
IC(L)
D G N D
P _ D V
D D
119
118
117
116
115
114
113
112
111
110
109
108
106
105
104
103
107
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
82
83
81
IC(L)
IC(L)
IC(N)
P_AV
DD
AGND
Top View
IC(H)
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
6
PD72870,72871
160-pin plastic LQFP (Fine pitch) (24 x 24 mm)
PD72871GM-8ED
GROM_SDA
P _ A V
D D
A G N D
X O
XI
P _ A V
D D
FIL0
FIL1
A G N D
A G N D
P _ A V
D D
P _ A V
D D
L_V
D D
C L K R U N
P M E
INTA
P R S T
P C L K
G N T
R E Q
D G N D
A D 3 1
A D 3 0
PCI_V
D D
A D 2 9
D G N D
A D 2 7
A D 2 6
A D 2 5
A D 2 8
A D 2 4
L_V
D D
D G N D
C B E 3
IDSEL
A D 2 3
A D 2 2
A D 2 1
A D 2 0
D G N D
A D 1 9
A D 1 8
PCI_V
D D
A D 1 7
A D 1 6
D G N D
C B E 2
F R A M E
IRDY
D E V S E L
T R D Y
L_V
D D
DGND
L_V
DD
DGND
DGND
DGND
STOP
AD15
AD14
PCI_V
DD
AD13
AD12
AD11
AD10
AD9
AD8
DGND
L_V
DD
CBE0
AD7
AD6
AD5
AD4
DGND
AD3
AD2
PCI_V
DD
AD1
AD0
IC(N)
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
14
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
39
38
40
41
42
43
44
45
46
47
48
49
50
51
52
53
55
56
57
58
54
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
79
78
80
120
160
159
158
157
156
155
154
153
152
151
150
149
148
146
145
144
143
147
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
122
123
121
PERR
SERR
PAR
L_V
DD
CBE1
P _ R E S E T B
P_DV
DD
IC(L)
IC(L)
CARD_ON
CIS_ON
GROM_EN
GROM_SCL
DGND
L_V
DD
DGND
P_AV
DD
P_AV
DD
RI1
AGND
AGND
TpA0p
TpA0n
TpB0p
TpB0n
NC
NC
NC
NC
NC
NC
NC
NC
TpBias0
NC
NC
P_AV
DD
AGND
CPS
RI0
AGND
AGND
IC(N)
PIN_EN
IC(N)
IC(N)
IC(N)
L_V
D D
S U S _ R E S M
P _ D V
D D
IC(L)
C M C
D G N D
D G N D
IC(H)
IC(H)
D G N D
P _ D V
D D
P C 2
P C 1
P C 0
IC(N)
D G N D
IC(N)
IC(N)
IC(N)
IC(N)
IC(N)
P O R T D I S
IC(L)
D G N D
P _ D V
D D
119
118
117
116
115
114
113
112
111
110
109
108
106
105
104
103
107
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
82
83
81
IC(L)
IC(L)
IC(N)
P_AV
DD
AGND
Top View
IC(H)
Preliminary Data Sheet S13925EJ2V0DS00
7
PD72870,72871
192-pin Plastic FBGA (14 x 14 mm)
PD72870 F1-FA2
PD72871 F1-FA2
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
T R P N M L K J H G F E D C B A
A B C D E F G H J K L M N P R T
Index mark
Bottom View
Top View
Remark : Pin connected on the FPBGA board.
P
r
el
i
m
i
nary D
a
ta S
heet S
13925E
J2V
0
D
S
00
8
P
D
72870,72871
T
DGND
IC(N)
IC(N)
IC(H)
AD0
AD2
AD4
AD6
AD8
AD10
AD12
AD14
CBE1
SERR
STOP
DEVSEL
R
L_V
DD
IC(N)
IC(N)
IC(N)
AD1
AD3
AD5
AD7
AD9
AD11
AD13
AD15
PAR
PERR
IRDY
TRDY
P
IC(N)
IC(N)
IC(N)
PIN_EN
DGND
DGND
DGND
CBE0
DGND
DGND
PCI_V
DD
DGND
DGND
L_V
DD
CBE2
FRAME
N
IC(N)
IC(N)
DGND
L_V
DD
PCI_V
DD
PCI_V
DD
L_V
DD
L_V
DD
DGND
DGND
PCI_V
DD
L_V
DD
DGND
PCI_V
DD
AD17
AD16
M
IC(L)
DGND
IC(L)
IC(N)
DGND
DGND
AD19
AD18
L
PC1
PC0
IC(N)
P_DV
DD
L_V
DD
DGND
AD21
AD20
K
CMC
PC2
P_DV
DD
P_DV
DD
L_V
DD
DGND
AD23
AD22
J
IC(L)
IC(H)
IC(H)
DGND
L_V
DD
DGND
CBE3
IDSEL
Top View
H
PORTDIS
DGND
P_DV
DD
IC(L)
DGND
DGND
AD25
AD24
G
P_AV
DD
SUS_RESM
P_DV
DD
P_DV
DD
DGND
DGND
AD27
AD26
F
P_RESETB
P_AV
DD
DGND
DGND
DGND
PCI_V
DD
AD29
AD28
E
FIL0
FIL1
AGND
AGND
DGND
PCI_V
DD
AD31
AD30
D
XO
XI
P_AV
DD
P_AV
DD
P_AV
DD
P_AV
DD
AGND
AGND
AGND
AGND
P_AV
DD
DGND
IC(L)
DGND
GNT
REQ
C
AGND
P_AV
DD
TpBias0
AGND
AGND
AGND
AGND
AGND
AGND
AGND
P_AV
DD
L_V
DD
GROM_EN
IC(L)
PRST
PCLK
B
RI1
AGND
TpBias1
TpB2p
TpA2p
TpB1p
TpA1p
TpB0p
TpA0p
AGND
P_AV
DD
DGND
GROM_SCL
CARD_ON
PME
INTA
A
RI0
CPS
TpBias2
TpB2n
TpA2n
TpB1n
TpA1n
TpB0n
TpA0n
AGND
AGND
P_DV
DD
GROM_SDA
CIS_ON
L_V
DD
CLKRUN
PD72870 F1-FA2
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
P
r
el
i
m
i
nary D
a
ta S
heet S
13925E
J2V
0
D
S
00
9
P
D
72870,72871
T
DGND
IC(N)
IC(N)
IC(H)
AD0
AD2
AD4
AD6
AD8
AD10
AD12
AD14
CBE1
SERR
STOP
DEVSEL
R
L_V
DD
IC(N)
IC(N)
IC(N)
AD1
AD3
AD5
AD7
AD9
AD11
AD13
AD15
PAR
PERR
IRDY
TRDY
P
IC(N)
IC(N)
IC(N)
PIN_EN
DGND
DGND
DGND
CBE0
DGND
DGND
PCI_V
DD
DGND
DGND
L_V
DD
CBE2
FRAME
N
IC(N)
IC(N)
DGND
L_V
DD
PCI_V
DD
PCI_V
DD
L_V
DD
L_V
DD
DGND
DGND
PCI_V
DD
L_V
DD
DGND
PCI_V
DD
AD17
AD16
M
IC(L)
DGND
IC(L)
IC(N)
DGND
DGND
AD19
AD18
L
PC1
PC0
IC(N)
P_DV
DD
L_V
DD
DGND
AD21
AD20
K
CMC
PC2
P_DV
DD
P_DV
DD
L_V
DD
DGND
AD23
AD22
J
IC(L)
IC(H)
IC(H)
DGND
L_V
DD
DGND
CBE3
IDSEL
Top View
H
PORTDIS
DGND
P_DV
DD
IC(L)
DGND
DGND
AD25
AD24
G
P_AV
DD
SUS_RESM
P_DV
DD
P_DV
DD
DGND
DGND
AD27
AD26
F
P_RESETB
P_AV
DD
DGND
DGND
DGND
PCI_V
DD
AD29
AD28
E
FIL0
FIL1
AGND
AGND
DGND
PCI_V
DD
AD31
AD30
D
XO
XI
P_AV
DD
P_AV
DD
P_AV
DD
P_AV
DD
AGND
AGND
AGND
AGND
P_AV
DD
DGND
IC(L)
DGND
GNT
REQ
C
AGND
P_AV
DD
TPBias0
AGND
AGND
AGND
AGND
AGND
AGND
AGND
P_AV
DD
L_V
DD
GROM_EN
IC(L)
PRST
PCLK
B
RI1
AGND
NC
NC
NC
NC
NC
TpB0p
TpA0p
AGND
P_AV
DD
DGND
GROM_SCL
CARD_ON
PME
INTA
A
RI0
CPS
NC
NC
NC
NC
NC
TpB0n
TpA0n
AGND
AGND
P_DV
DD
GROM_SDA
CIS_ON
L_V
DD
CLKRUN
PD72871
F1-FA2
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Preliminary Data Sheet S13925EJ2V0DS00
10
PD72870,72871
PIN NAME
AD0-AD31
: PCI Multiplexed Address and Data
AGND
: Analog GND
CARD_ON
: PCI/Card Select
CBE0-CBE3 : Command/Byte Enables
CIS_ON
: CIS Register ON
CLKRUN
: PCICLK Running
CMC
: Configuration Manager Capable
CPS
: Cable Power Status Input
DEVSEL
: Device Select
DGND
: Digital GND
FIL0
: APLL Filter GND
FIL1
: APLL Filter Terminal
FRAME
: Cycle Frame
GNT
: Bus_master Grant
GROM_EN : Serial EEPROM Enable
GROM_SCL : Serial EEPROM Clock Output
GROM_SDA : Serial EEPROM Data Input / Output
IC(H)
: Internally Connected (High Clamped)
IC(L)
: Internally Connected (Low Clamped)
IC(N)
: Internally Connected (Open)
IDSEL
: ID Select
INTA
: Interrupt
IRDY
: Initiator Ready
L_V
DD
: V
DD
for Link Digital Core and Link I/Os
PAR
: Parity
PC0-PC2
: Power Class Input
PCI_V
DD
: V
DD
for PCI I/Os
PCLK
: PCI Clock
PERR
: Parity Error
PIN_EN
: Pin Enable Input
PME
: PME Output
PORTDIS
: Port Disable
PRST
: Reset
P_AV
DD
: PHY Analog V
DD
P_DV
DD
: PHY Digital V
DD
P_RESETB : PHY Power on Reset Input
REQ
: Bus_master Request
RI0
: Resistor0 for Reference Current Setting
RI1
: Resistor1 for Reference Current Setting
SERR
: System Error
STOP
: PCI Stop
SUS_RESM : Suspend/Resume Function Select
Tp0n
: Port-1 Twisted Pair A Negative Input/Output
TpA0p
: Port-1 Twisted Pair A Positive Input/Output
TpA1n
: Port-2 Twisted Pair A Negative Input/Output
TpA1p
: Port-2 Twisted Pair A Positive Input/Output
TpA2n
: Port-3 Twisted Pair A Negative Input/Output
TpA2p
: Port-3 Twisted Pair A Positive Input/Output
TpB0n
: Port-1 Twisted Pair B Negative Input/Output
TpB0p
: Port-1 Twisted Pair B Positive Input/Output
TpB1n
: Port-2 Twisted Pair B Negative Input/Output
TpB1p
: Port-2 Twisted Pair B Positive Input/Output
TpB2n
: Port-3 Twisted Pair B Negative Input/Output
TpB2p
: Port-3 Twisted Pair B Positive Input/Output
TpBias0
: Port-1 Twisted Pair Bias Voltage Output
TpBias1
: Port-2 Twisted Pair Bias Voltage Output
TpBias2
: Port-3 Twisted Pair Bias Voltage Output
TRDY
: Target Ready
XI
: X'tal XI
XO
: X'tal XO
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
11
PD72870,72871
CONTENTS
1. PIN FUNCTIONS ................................................................................................................................... 13
1.1 PCI/Cardbus Interface Signals: (52 pins)..................................................................................... 13
1.2 Cable Interface Signals: (15 pins) ................................................................................................ 14
1.3 PHY Signals: (9 pins)..................................................................................................................... 15
1.4 PHY Control Signals: (5 pins) ....................................................................................................... 15
1.5 PCI/Cardbus Select Signals: (2 pins) ........................................................................................... 16
1.6 Serial ROM Interface Signals: (3 pins) ......................................................................................... 16
1.7 Miscellaneous Signals: (1 pin)...................................................................................................... 16
1.8 IC: ( 21 pins) ................................................................................................................................... 17
1.9 V
DD
................................................................................................................................................... 17
1.10 GND ............................................................................................................................................... 17
2. PHY REGISTERS .................................................................................................................................. 18
2.1 Complete Structure for PHY Registers ........................................................................................ 18
2.2 Port Status Page (Page 000) ......................................................................................................... 21
2.3 Vendor ID Page (Page 001) ........................................................................................................... 22
3. CONFIGURATION REGISTERS........................................................................................................... 23
3.1 PCI Bus Mode Configuration Register ( CARD_ON=Low ) ........................................................ 23
3.1.1 Offset_00 Vendor ID Register............................................................................................................ 24
3.1.2 Offset_02 DeviceID Register ............................................................................................................. 24
3.1.3 Offset_04 Command Register ........................................................................................................... 24
3.1.4 Offset_06 Status Register.................................................................................................................. 25
3.1.5 Offset_08 Revision ID Register.......................................................................................................... 26
3.1.6 Offset_09 Class Code Register ......................................................................................................... 26
3.1.7 Offset_0C Cache Line Size Register ................................................................................................. 26
3.1.8 Offset_0D Latency Timer Register..................................................................................................... 26
3.1.9 Offset_0E Header Type Register....................................................................................................... 26
3.1.10 Offset_0F BIST Register................................................................................................................... 26
3.1.11 Offset_10 Base Address 0 Register................................................................................................. 27
3.1.12 Offset_20 Subsystem Vendor ID Register ....................................................................................... 27
3.1.13 Offset_22 Subsystem ID Register.................................................................................................... 27
3.1.14 Offset_30 Expansion Rom Base Address Register ......................................................................... 27
3.1.15 Offset_34 Cap_Ptr Register............................................................................................................. 27
3.1.16 Offset_3C Interrupt Line Register .................................................................................................... 28
3.1.17 Offset_3D Interrupt Pin Register...................................................................................................... 28
3.1.18 Offset_3E Min_Grant Register......................................................................................................... 28
3.1.19 Offset_3F Max Lat Register ............................................................................................................. 28
3.1.20 Offset_40 PCI_OHCI_Control Register ........................................................................................... 28
3.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register .................................................................................. 29
3.1.22 Offset_62 Power Management Capabilities Register ...................................................................... 29
3.1.23 Offset_64 Power Management Control/Status Register .................................................................. 30
3.2 CardBus Mode Configuration Register ( CARD_ON=High ) ...................................................... 31
3.2.1 Offset_14/18 Base_Address_1/2 Register (CardBus Status Registers)............................................ 32
3.2.2 Offset_28 Cardbus CIS Pointer ......................................................................................................... 33
3.2.3 Offset_80 CIS Area............................................................................................................................ 33
Preliminary Data Sheet S13925EJ2V0DS00
12
PD72870,72871
4. PHY FUNCTION .................................................................................................................................... 34
4.1 Cable Interface ............................................................................................................................... 34
4.1.1 Connections .......................................................................................................................................... 34
4.1.2 Cable Interface Circuit .......................................................................................................................... 35
4.1.3 CPS....................................................................................................................................................... 35
4.1.4 Unused Ports ........................................................................................................................................ 35
4.2 PLL and Crystal Oscillation Circuit.............................................................................................. 35
4.2.1 Crystal Oscillation Circuit ...................................................................................................................... 35
4.2.2 PLL ....................................................................................................................................................... 35
4.3 PC0-PC2, CMC................................................................................................................................ 35
4.4 P_RESETB ...................................................................................................................................... 35
4.5 RI0, RI1 ............................................................................................................................................ 35
5. SERIAL ROM INTERFACE .................................................................................................................. 36
5.1 Serial EEPROM Register ............................................................................................................... 36
5.2 Serial EEPROM Register Description .......................................................................................... 36
5.3 Load Control................................................................................................................................... 40
6. ELECTRICAL SPECIFICATIONS ......................................................................................................... 41
7. APPLICATION CIRCUIT EXAMPLE.................................................................................................... 44
8. PACKAGE DRAWINGS ........................................................................................................................ 45
Preliminary Data Sheet S13925EJ2V0DS00
13
PD72870,72871
1. PIN FUNCTIONS
1.1 PCI/Cardbus Interface Signals: (52 pins)
(1/2)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
PAR
I/O
45
R4
PCI/Cardbus
5/3.3
Parity is even parity across AD0-AD31 and CBE0-CBE3. It is
an input when AD0-AD31 is an input; it is an output when AD0-
AD31 is an output.
AD0-AD31
I/O
11-14,
16-19,
24-27,
29,30,32,
33,49,50,
52,53,
55-58,
61-64,
66-69
E1,E2,
F1,F2,
G1,G2,
H1,H2,
K1,K2,
L1,L2,
M1,M2,
N1,N2,
R5-R12,
T5-T12
PCI/Cardbus
5/3.3
PCI Multiplexed Address and Data
CBE0-CBE3
I
22,35,47,
60
J2,P2,P9,
T4
-
5/3.3
Command/Byte Enables are multiplexed Bus Commands &
Byte enables.
FRAME
I/O
36
P1
PCI/Cardbus
5/3.3
Cycle Frame is asserted by the initiator to indicate the cycle
beginning and is kept asserted during the burst cycle.
If Cardbus mode (CARD_ON = 1), this pin is should be pulled
up to V
DD
.
TRDY
I/O
38
R1
PCI/Cardbus
5/3.3
Target Ready indicates that the current data phase of the
transaction is ready to be completed.
IRDY
I/O
37
R2
PCI/Cardbus
5/3.3
Initiator Ready indicates that the current bus master is ready
to complete the current data phase. During a write, its assertion
indicates that the initiator is driving valid data onto the data bus.
During a read, its assertion indicates that the initiator is ready
to accept data from the currently-addressed target.
REQ
O
8
D1
PCI/Cardbus
5/3.3
Bus_master Request indicates to the bus arbiter that this
device wants to become a bus master.
GNT
I
7
D2
-
5/3.3
Bus_master Grant indicates to this device that access to the
bus has been granted.
IDSEL
I
23
J1
-
5/3.3
ID Select when actively driven, indicates that the IUHC is chip-
selected for configuration read/write transaction during the
phase of device initialization.
If Cardbus mode (CARD_ON = 1), this pin is should be pulled
up to V
DD
.
DEVSEL
I/O
39
T1
PCI/Cardbus
5/3.3
Device Select when actively driven, indicates that the driving
device has decoded its address as the target of the current
access.
STOP
I/O
42
T2
PCI/Cardbus
5/3.3
PCI Stop when actively driven, indicates that the target is
requesting the current bus master to stop the transaction.
5
5
5
5
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
14
PD72870,72871
(2/2)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
PME
O
3
B2
PCI/Cardbus
5/3.3
PME Output for power management enable.
Caution The PME pin is not an N-channel open drain
structure pin.
Therefore, when using S3, S4, S5 state in ACPI, a
circuit that can separate between the power supply
and the PME pin externally is needed.
ACPI: Advanced Configuration and Power Interface.
Please refer to ACPI Specification.
CLKRUN
I/O
2
A1
PCI/Cardbus
5/3.3
PCICLK Running as input, to determine the status of PCLK;
as output, to request starting or speeding up clock.
INTA
O
4
B1
PCI/Cardbus
5/3.3
Interrupt the PCI interrupt request A.
PERR
I/O
43
R3
PCI/Cardbus
5/3.3
Parity Error is used for reporting data parity errors during all
PCI transactions, except a Special Cycle. It is an output when
AD0-AD31 and PAR are both inputs. It is an input when AD0-
AD31 and PAR are both outputs.
SERR
O
44
T3
PCI/Cardbus
5/3.3
System Error is used for reporting address parity errors, data
parity errors during the Special Cycle, or any other system error
where the effect can be catastrophic. When reporting address
parity errors, it is an output.
PRST
I
5
C2
-
5/3.3
Reset PCI reset
PCLK
I
6
C1
-
5/3.3
PCI Clock 33 MHz systembus clock.
1.2 Cable Interface Signals: (15 pins)
(1/2)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
TpA0p
I/O
140
B8
-
-
Port-1 Twisted Pair A Positive Input/Output
Note 2
TpA0n
I/O
139
A8
-
-
Port-1 Twisted Pair A Negative Input/Output
Note 2
TpB0p
I/O
138
B9
-
-
Port-1 Twisted Pair B Positive Input/Output
Note 2
TpB0n
I/O
137
A9
-
-
Port-1 Twisted Pair B Negative Input/Output
Note 2
TpA1p
Note 1
I/O
136
B10
-
-
Port-2 Twisted Pair A Positive Input/Output
Note 2
TpA1n
Note 1
I/O
135
A10
-
-
Port-2 Twisted Pair A Negative Input/Output
Note 2
TpB1p
Note 1
I/O
134
B11
-
-
Port-2 Twisted Pair B Positive Input/Output
Note 2
TpB1n
Note 1
I/O
133
A11
-
-
Port-2 Twisted Pair B Negative Input/Output
Note 2
TpA2p
Note 1
I/O
132
B12
-
-
Port-3 Twisted Pair A Positive Input/Output
Note 2
TpA2n
Note 1
I/O
131
A12
-
-
Port-3 Twisted Pair A Negative Input/Output
Note 2
TpB2p
Note 1
I/O
130
B13
-
-
Port-3 Twisted Pair B Positive Input/Output
Note 2
TpB2n
Note 1
I/O
129
A13
-
-
Port-3 Twisted Pair B Negative Input/Output
Note 2
Note 1.
PD72870 only. In
PD72871, it is open.
2. If unused port, please refer to 4.1.4 Unused Port.
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
15
PD72870,72871
(2/2)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
PORTDIS
I
105
H16
Port Disable
SUS_RESM = "1"
This selected state will be loaded to Disabled bit which
allocated PHY register Port Status Page.
1:Disable
At this time, all ports will be disabled (
PD72870: 3ports,
PD72871: 1port).
SUS_RESM="0"
PORTDIS has no effect.
SUS_RESM
I
106
G15
Suspend/Resume Function Select
1 : Suspend/Resume On (P1394a draft 2.0 compliant)
0 : Suspend/Resume Off (P1394a draft 1.3 compliant)
CPS
I
123
A15
-
-
Cable Power Status Input
Note
Note Please refer to 4.1.3 CPS.
1.3 PHY Signals: (9 pins)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
TpBias0
O
128
C14
-
-
Port-1 Twisted Pair Bias Voltage Output
Note 2
TpBias1
Note1
O
127
B14
-
-
Port-2 Twisted Pair Bias Voltage Output
Note 2
TpBias2
Note1
O
126
A14
-
-
Port-3 Twisted Pair Bias Voltage Output
Note 2
RI0
-
121
A16
-
-
Resistor0 for Reference Current Setting
Note 3
RI1
-
122
B16
-
-
Resistor1 for Reference Current Setting
Note 3
FIL1
-
114
E15
-
-
APLL Filter Terminal (No need to assemble)
FIL0
-
115
E16
-
-
APLL Filter GND (No need to assemble)
XI
I
117
D15
-
-
X'tal XI
XO
O
118
D16
-
-
X'tal XO
Note 1.
PD72870 only. In
PD72871, it is open.
2. If unused port, please refer to 4.1.4 Unused Port.
3. Please refer to 4.5 RI0, RI1.
1.4 PHY Control Signals: (5 pins)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
PC0-PC2
I
93-95
K15,L15,
L16
-
3.3
Power Class Input
Note 1
CMC
I
96
K16
-
3.3
Configuration Manager Capable
Note 1
P_RESETB
I
110
F16
PHY Power on Reset Input
Note 2
Note 1. Please refer to 4.3 PC0-PC2, CMC.
2. Please refer to 4.4 P_RESETB.
5
5
5
5
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
16
PD72870,72871
1.5 PCI/Cardbus Select Signals: (2 pins)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
CARD_ON
I
157
B3
-
3.3
PCI/Card Select (1:Cardbus, 0:PCI bus)
CIS Register ON
CARD_ON
CIS_ON
CIS
PME
CIS_ON
I
156
A3
-
3.3
0
0
1
1
0
X
off
on
on
PME
CSTSCHG
CSTSCHG
1.6 Serial ROM Interface Signals: (3 pins)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
GROM_SDA
I/O
153
A4
6mA
3.3
Serial EEPROM Data Input / Output
GROM_SCL
O
154
B4
6mA
3.3
Serial EEPROM Clock Output
GROM_EN
I
155
C4
-
3.3
Serial EEPROM Enable
(`high': GUID Load enabled, `low': GUID Load disabled)
1.7 Miscellaneous Signals: (1 pin)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
PIN_EN
I
73
P13
-
5/3.3
Pin Enable Input (High clamped)
Preliminary Data Sheet S13925EJ2V0DS00
17
PD72870,72871
1.8 IC: ( 21 pins)
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
IC(H)
I
75,99,100
J14,J15,T13
-
-
Internally Connected (High clamped)
IC(L)
I
89,91,101,102,158,
159
C3,D4,H13,J16,
M14,M16
-
-
Internally Connected (Low clamped)
IC(N)
-
74,76-79,82-84,
86-88,92
L14,M13,N15,N16,
P14-P16,R13-R15,
T14,T15
-
-
Internally Connected (Open)
1.9 V
DD
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
PCI_V
DD
-
10,31,51,70
E3,F3,N3,N6,
N11,N12,P6
-
5/3.3
V
DD
for PCI I/Os
L_V
DD
-
1,20,40,46,59,72,81,
151
A2,C5,J4,K4,L4,N5,
N9,N10,N13,P3,R16
-
3.3
V
DD
for Link digital Core and Link I/Os
P_DV
DD
-
97,103,108,149
A5,G13,G14,H14,K13,
K14,L13
-
3.3
PHY digital V
DD
-
111
F15
-
3.3
PHY PLL V
DD
-
107,116
D14,G16
-
3.3
PHY PLL,OSC V
DD
-
120,125
C15,D11-D13
-
3.3
PHY Bias V
DD
P_AV
DD
-
146-148
B6,C6,D6
-
3.3
PHY Port V
DD
1.10 GND
Pin No.
Name
I/O
LQFP
FPBGA
I
OL
Volts(V)
Function
DGND
-
9,15,21,28,34,41,48,
54,65,71,80,85,90,98,
104,109,150,152,160
B5,D3,D5,E4,F4,F13,
F14,G3,G4,H3,H4,
H15,J3,J13,K3,L3,
M3,M4,M15,N4,N7,
N8,N14,P4,P5,P7,P8,
P10-P12,T16
-
-
Digital GND
-
112
E13
-
-
PHY PLL GND
-
113
E14
-
-
PHY PLL,OSC GND
-
119,124
B15,C16
-
-
PHY Bias GND
-
141
A7
-
-
PHY Common GND
-
142
B7
-
-
PHY Speed Signal GND
AGND
-
143,144,145
A6,C7-C13,D7-D10
-
-
PHY Port GND
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
18
PD72870,72871
2. PHY REGISTERS
2.1 Complete Structure for PHY Registers
Figure 2-1. Complete Structure of PHY Registers
0
1
2
3
4
5
6
7
0000
Physical_ID
R
PS
0001
RHB
IBR
Gap_count
0010
Extended (7)
Reserved
Total_ports
0011
Max_speed
Reserved
Delay
0100
Link_active
Contender
Jitter
Pwr_class
0101
Resume_int
ISBR
Loop
Pwr_fail
Timeout
Port_event
Enab_accel
Enab_multi
0110
Reserved
0111
Page_select
Reserved
Port_select
1000
Register0 (page_select)
1001
Register1 (page_select)
1010
Register2 (page_select)
1011
Register3 (page_select)
1100
Register4 (page_select)
1101
Register5 (page_select)
1110
Register6 (page_select)
1111
Register7 (page_select)
Table 2-1. Bit Field Description (1/3)
Field
Size
R/W
Reset value
Description
Physical_ID
6
R
000000
Physical_ID value selected from Self_ID period.
R
1
R
0
If this bit is 1, the node is root.
1: Root
0: Not root
PS
1
R
Cable power status.
1: Cable power on
0: Cable power off
RHB
1
R/W
0
Root Hold -off bit. If 1, becomes root at the bus reset.
IBR
1
R/W
0
Initiate bus reset.
Setting to 1 begins a long bus reset.
Long bus reset signal duration: 166
sec.
Returns to 0 at the beginning of bus reset.
Gap_count
6
R/W
111111
Gap count value.
It is updated by the changes of transmitting and receiving the PHY
configuration packet Tx/Rx.
The value is maintained after first bus reset.
After the second bus reset it returns to reset value.
Preliminary Data Sheet S13925EJ2V0DS00
19
PD72870,72871
Table 2-1. Bit Field Description (2/3)
Field
Size
R/W
Reset value
Description
Extended
3
R
111
Shows the extended register map.
Total_ports
4
R
0011
or
0001
Supported port number.
0011: 3port (
PD72870)
0001: 1port (
PD72871)
Max_speed
3
R
010
Indicate the maximum speed that this node supports.
010: 98.304, 196.608 and 393.216 Mbps
Delay
4
R
0010
Indicate worst case repeating delay time. 144+(2 x 20)=184 nsec
Link_active
1
R/W
1
Link active.
1: Enable
0: Disable
The logical AND status of this bit and LPS.
State will be referred to "L bit" of Self-ID Packet#0.
The LPS is a PHY/Link interface signal and is defined in P1394a draft 2.0. It
is an internal signal in the
PD72870,72871.
Contender
1
R/W
See
Description
Contender.
"1" indicate this node support bus manager function. This bit will be referred
to "C bit" of Self-ID Packet#0.
The reset data is depending on CMC pin setting.
CMC pin condition
1: Pull up (Contender)
0: Pull down (Non Contender)
Jitter
3
R
010
The difference of repeating time (Max.-Min.). (2+1) x 20=60 nsec
Pwr_class
3
R/W
See
Description
Power class.
Please refer to IEEE1394 -1995 [4.3.4.1].
This bit will be referred to Pwr field of Self-ID Packet#0.
The reset data will be determined by PC0-PC2 Pin status.
Resume_int
1
R/W
0
Resume interrupt enable. When set to 1, if any one port does resume, the
Port_event bit becomes 1.
ISBR
1
R/W
0
Initiate short (arbitrated) bus reset.
Setting to 1 acquires the bus and begins short bus reset.
Short bus reset signal output : 1.3
sec
Returns to 0 at the beginning of the bus reset.
Loop
1
R/W
0
Loop detection output.
1: Detection
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Pwr_fail
1
R/W
0
Power cable disconnect detect.
It becomes 1 when there is a change from 1 to 0 in the CPS bit.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Timeout
1
R/W
0
Arbitration state machine time-out.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
20
PD72870,72871
Table 2-1. Bit Field Description (3/3)
Field
Size
R/W
Reset value
Description
Port_event
1
R/W
0
Set to 1 when the Int_Enable bit in the register map of each port is 1 and
there is a change in the ports connected, Bias, Disabled and Fault bits.
Set to 1 when the Resume_int bit is 1 and any one port does resume.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Enab_accel
1
R/W
0
Enables arbitration acceleration.
Ack-acceleration and Fly-by arbitration are enabled.
1: Enabled
0: Disabled
If this bit changes while the bus request is pending, the operation is not
guaranteed.
Enab_multi
1
R/W
0
Enable multi-speed packet concatenation.
Setting this bit to 1 follows multi-speed transmission.
When this bit is set to 0,the packet will be transmitted with the same speed
as the first packet.
Page_select
3
R/W
000
Select page address between 1000 to 1111.
000: Port Status Page
001: Vendor Definition Page
Others: Unused
Port Selection.
Selecting 000 (Port Status Page) with the page selection selects the port.
PD72870
PD72871
Port_select
4
R/W
0000
0000: Port 0
0001: Port 1
0010: Port 2
Others: Unused
0000: Port 0
Others: Unused
Reserved
-
R
000...
Reserved. Read as 0.
Preliminary Data Sheet S13925EJ2V0DS00
21
PD72870,72871
2.2 Port Status Page (Page 000)
Figure 2-2. Port Status Page
0
1
2
3
4
5
6
7
1000
AStat
BStat
Child
Connected
Bias
Disabled
1001
Negotiated_speed
Int_enable
Fault
Reserved
1010
Reserved
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
Table 2-2. Bit Field Description
Field
Size
R/W
Reset value
Description
AStat
2
R
XX
A port status value.
00:---, 10: "0"
01: "1", 11: "Z"
BStat
2
R
XX
B port status value.
00:---, 10: "0"
01: "1", 11: "Z"
Child
1
R
Child node status value.
1: Connected to child node
0 : Connected to parent node
Connected
1
R
0
Connection status value.
1: Connected
0: Disconnected
Bias
1
R
Bias voltage status value.
1: Bias voltage
0: No bias voltage
Disabled
1
R/W
See
Description
The reset value is set by the PORTDIS pin.
1: Disable
Negotiated_
Speed
3
R
Shows the maximum data transfer rate of the node connected to this port.
000: 100 Mbps
001: 200 Mbps
010: 400 Mbps
Int_enable
1
R/W
0
The Port_event is set to 1 by a change to 1 of the Connected, Bias, Disable,
and Fault bits.
Fault
1
R/W
0
Set to 1 if an error occurs during Suspend/Resume.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Reserved
-
R
000...
Reserved. Read as 0.
Preliminary Data Sheet S13925EJ2V0DS00
22
PD72870,72871
2.3 Vendor ID Page (Page 001)
Figure 2-3. Vendor ID Page
0
1
2
3
4
5
6
7
1000
Compliance_level
1001
Reserved
1010
1011
1100
Vendor_ID
1101
1110
1111
Product_ID
Table 2-3. Bit Field Description
Field
Size
R/W
Reset value
Description
Compliance_level
8
R
00000001
According to IEEE P1394a.
Vendor_ID
24
R
00004CH
Company ID Code value, NEC IEEE OUI.
Product_ID
24
R
Product code.
Reserved
-
R
000...
Reserved. Read as 0.
Preliminary Data Sheet S13925EJ2V0DS00
23
PD72870,72871
3. CONFIGURATION REGISTERS
3.1 PCI Bus Mode Configuration Register ( CARD_ON=Low )
31
24
23
16
15
08
07
00
Device ID
Vendor ID
00H
Status
Command
04H
Class Code
Revision ID
08H
BIST
Header Type
Latency Timer
Cache Line Size
0CH
Base Address 0
10H
Base Address 1
14H
Base Address 2
18H
Base Address 3
1CH
Base Address 4
20H
Base Address 5
24H
CardBus CIS Pointer
28H
Subsystem ID
Subsystem Vendor ID
2CH
Expansion Rom Base Address Register
30H
000000H
Cap_Ptr
34H
00000000H
38H
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
3CH
PCI_OHCI_Control
40H
00000000H
44H
00000000H
48H
00000000H
4CH
Diagnostic register0
50H
Diagnostic register1
54H
Diagnostic register2
58H
Diagnostic register3
5CH
Power Management Capabilities
Next_Item_Ptr
Cap_ID
60H
Data
PMCSR_BSE
Power Management Control/Status
64H
00000000H
68H
00000000H
6CH
User Area (GENERAL_RegisterA)
70H
User Area (GENERAL_RegisterB)
74H
User Area (GENERAL_RegisterC)
78H
User Area (GENERAL_RegisterD)
7CH
00000000H
80H
FCH
Preliminary Data Sheet S13925EJ2V0DS00
24
PD72870,72871
3.1.1 Offset_00 Vendor ID Register
This register identifies the manufacturer of the
PD72870, 72871. The ID is assigned by the PCI_SIG committee.
Bits
R/W
Description
15-0
R
Constant value of 1033H.
3.1.2 Offset_02 DeviceID Register
This register identifies the type of the device for the
PD72870, 72871. The ID is assigned by NEC Corporation.
Bits
R/W
Description
15-0
R
Constant value of 00CDH (
PD72870 ).
Constant value of 00CEH (
PD72871).
3.1.3 Offset_04 Command Register
The register provides control over the device's ability to generate and respond to PCI cycles.
Bits
R/W
Description
0
R
I/O enable Constant value of 0. The
PD72870, 72871 does not respond to PCI I/O
accesses.
1
R/W
Memory enable Default value of 1. It defines if the
PD72870, 72871 responds to PCI
memory accesses. This bit should be set to one upon power-up reset.
0: The
PD72870, 72871 does not respond to PCI memory cycles
1: The
PD72870, 72871 responds to PCI memory cycles
2
R/W
Master enable Default value of 1. It enables the
PD72870, 72871 as bus-master on the
PCI-bus.
0: The
PD72870, 72871 cannot generate PCI accesses by being a bus-master
1: The
PD72870, 72871 is capable of acting as a bus-master
3
R
Special cycle monitor enable Constant value of 0. The special cycle monitor is always
disabled.
4
R/W
Memory write and invalidate enable Default value of 0. It enables Memory Write and Invalid
Command generation.
0: Memory write must be used
1: The
PD72870, 72871, when acts as PCI master, can generate the command
5
R
VGA color palette invalidate enable Constant value of 0. VGA color palette invalidate is
always disabled.
6
R/W
Parity error response Default value of 0. It defines if the
PD72870, 72871 responds to PERR.
0: Ignore parity error
1: Respond to parity error
7
R
Stepping enable Constant value of 0. Stepping is always disabled.
8
R/W
System error enable Default value of 0. It defines if the
PD72870, 72871 responds to SERR.
0: Disable system error checking
1: Enable system error checking
9
R
Fast back-to-back enable Constant value of 0. Fast back-to-back transactions are only
allowed to the same agent.
15-10
R
Reserved Constant value of 000000.
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
25
PD72870,72871
3.1.4 Offset_06 Status Register
This register tracks the status information of PCI-bus related events which are relevant to the
PD72870, 72871.
"Read" and "Write" are handled somewhat differently.
Bits
R/W
Description
3-0
R
Reserved Constant value of 0000.
4
R
New capabilities Constant value of 1. It indicates the existence of the Capabilities List.
6,5
R
Reserved Constant value of 00.
7
R
Fast back-to-back capable Constant value of 1. It indicates that the
PD72870, 72871, as a
target, cannot accept fast back-to-back transactions when the transactions are not to the same
agent.
8
R/W
Signaled parity error Default value of 0. It indicates the occurrence of any "Data Parity".
0: No parity detected (default)
1: Parity detected
10,9
R
DEVSEL timing Constant value of 01. These bits define the decode timing for DEVSEL.
0: Fast (1 cycles)
1: Medium (2 cycles)
2: Slow (3 cycles)
3: undefined
11
R/W
Signaled target abort Default value of 0. This bit is set by a target device whenever it
terminates a transaction with "Target Abort".
0: The
PD72870, 72871 did not terminate a transaction with Target Abort
1: The
PD72870, 72871 has terminated a transaction with Target Abort
12
R/W
Received target abort Default value of 0. This bit is set by a master device whenever its
transaction is terminated with a "Target Abort".
0: The
PD72870, 72871 has not received a Target Abort
1: The
PD72870, 72871 has received a Target Abort from a bus-master
13
R/W
Received master abort Default value of 0. This bit is set by a master device whenever its
transaction is terminated with "Master Abort". The
PD72870, 72871 asserts "Master Abort"
when a transaction response exceeds the time allocated in the latency timer field.
0: Transaction was not terminated with a Master Abort
1: Transaction has been terminated with a Master Abort
14
R/W
Signaled system error Default value of 0. It indicates that the assertion of SERR by the
PD72870, 72871.
0: System error was not signaled
1: System error was signaled
15
R/W
Received parity error Default value of 0. It indicates the occurrence of any PERR.
0: No parity error was detected
1: Parity error was detected
Preliminary Data Sheet S13925EJ2V0DS00
26
PD72870,72871
3.1.5 Offset_08 Revision ID Register
This register specifies a revision number assigned by NEC Corporation for the
PD72870, 72871.
Bits
R/W
Description
7-0
R
Default value of 01H. It specifies the silicon revision. It will be incremented for subsequent
silicon revisions.
3.1.6 Offset_09 Class Code Register
This register identifies the class code, sub-class code, and programming interface of the
PD72870, 72871.
Bits
R/W
Description
7-0
R
Constant value of 10H. It specifies an IEEE1394 OpenHCI-compliant Host Controller.
15-8
R
Constant value of 00H. It specifies an "IEEE1394" type.
23-16
R
Constant value of 0CH. It specifies a "Serial Bus Controller".
3.1.7 Offset_0C Cache Line Size Register
This register specifies the system cache line size, which is PC-host system dependent, in units of 32-bit words.
The following cache line sizes are supported: 2, 4, 8, 16, 32, 64, and 128. All other values will be recognized as 0,
i.e. cache disabled.
Bits
R/W
Description
7-0
R/W
Default value of 00H.
3.1.8 Offset_0D Latency Timer Register
This register defines the maximum amount of time that the
PD72870, 72871 is permitted to retain ownership of
the bus after it has acquired bus ownership and initiated a subsequent transaction.
Bits
R/W
Description
7-0
R/W
Default value of 00H. It specifies the number of PCI-bus clocks that the
PD72870, 72871 may
hold the PCI bus as a bus-master.
3.1.9 Offset_0E Header Type Register
Bits
R/W
Description
7-0
R
Constant value of 00H. It specifies a single function device.
3.1.10 Offset_0F BIST Register
Bits
R/W
Description
7-0
R
Constant value of 00H. It specifies whether the device is capable of Built-in Self Test.
Preliminary Data Sheet S13925EJ2V0DS00
27
PD72870,72871
3.1.11 Offset_10 Base Address 0 Register
This register specifies the base memory address for accessing all the "Operation registers" (i.e. control,
configuration, and status registers) of the
PD72870, 72871, while the BIOS is expected to set this value during
power-up reset.
Bits
R/W
Description
11-0
R
Constant value of 000H. These bits are "read-only".
31-12
R/W
-
3.1.12 Offset_20 Subsystem Vendor ID Register
This register identifies the subsystem that contains the NEC's
PD72870, 72871 function. While the ID is
assigned by the PCI_SIG committee, the value should be loaded into the register from the external serial ROM after
power-up reset. Access to this register through PCI-bus is prohibited.
Bits
R/W
Description
15-0
R
Default value of 1033H.
3.1.13 Offset_22 Subsystem ID Register
This register identifies the type of the subsystem that contains the NEC's
PD72870, 72871 function. While the ID
is assigned by the manufacturer, the value should be loaded into the register from the external serial EEPROM after
power-up reset. Access to this register through PCI-bus is prohibited.
Bits
R/W
Description
15-0
R
Default value of 0063H.
3.1.14 Offset_30 Expansion Rom Base Address Register
This register is not supported by the current implementation of the
PD72870, 72871.
Bits
R/W
Description
31-0
R
Reserved Constant value of 0.
3.1.15 Offset_34 Cap_Ptr Register
This register points to a linked list of additional capabilities specific to the
PD72870, 72871, the NEC's
implementation of the 1394 OpenHCI specification.
Bits
R/W
Description
7-0
R
Constant value of 60H. The value represents an offset into the
PD72870, 72871's PCI
Configuration Space for the location of the first item in the New Capabilities Linked List.
Preliminary Data Sheet S13925EJ2V0DS00
28
PD72870,72871
3.1.16 Offset_3C Interrupt Line Register
This register provides the interrupt line routing information specific to the
PD72870, 72871, the NEC's
implementation of the 1394 OpenHCI specification.
Bits
R/W
Description
7-0
R/W
Default value of 00H. It specifies which input of the host system interrupt controller the
interrupt pin of the
PD72870, 72871 is connected to.
3.1.17 Offset_3D Interrupt Pin Register
This register provides the interrupt line routing information specific to the
PD72870, 72871, the NEC's
implementation of the 1394 OpenHCI specification.
Bits
R/W
Description
7-0
R
Constant value of 01H. It specifies PCI INTA is used for interrupting the host system.
3.1.18 Offset_3E Min_Grant Register
This register specifies how long of a burst period the
PD72870, 72871 needs, assuming a clock rate of 33MHz.
Resolution is in units of
s. The value should be loaded into the register from the external serial EEPROM upon
power-up reset, and access to this register through PCI-bus is prohibited.
Bits
R/W
Description
7-0
R
Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
3.1.19 Offset_3F Max Lat Register
This register specifies how often the
PD72870, 72871 needs to gain access to the PCI-bus, assuming a clock
rate of 33MHz. Resolution is in units of
s. The value should be loaded into the register from the external serial
EEPROM after hardware reset, and access to this register through PCI-bus is prohibited.
Bits
R/W
Description
7-0
R
Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
3.1.20 Offset_40 PCI_OHCI_Control Register
This register specifies the control bits that are IEEE1394 OpenHCI specific. Vendor options are not allowed in this
register. It is reserved for OpenHCI use only.
Bits
R/W
Description
0
R/W
PCI global SWAP Default value of 0. When this bit is 1, all quadrates read from and written to
the PCI Interface are byte swapped, thus a "PCI Global Swap". PCI addresses for expansion
ROM and PCI Configuration registers, are, however, unaffected by this bit. This bit is not
required for motherboard implementations.
31-1
R
Reserved Constant value of all 0.
Preliminary Data Sheet S13925EJ2V0DS00
29
PD72870,72871
3.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register
The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the
Next_Item_Ptr describes the location of the next item in the
PD72870, 72871's Capability List.
Bits
R/W
Description
7-0
R
Cap_ID Constant value of 01H. The default value identified the Link List item as being the PCI
Power Management registers, while the ID value is assigned by the PCI SIG.
15-8
R
Next_Item_Ptr Constant value of 00H. It indicated that there are no more items in the Link
List.
3.1.22 Offset_62 Power Management Capabilities Register
This is a 16-bit read-only register that provides information on the power management capabilities of the
PD72870, 72871.
Bits
R/W
Description
2-0
R
version Constant value of 001. The power management registers are implemented as defined
in revision 1.0 of PCI Bus Power Management Interface Specification.
3
R
PME clock Constant value of 0.
4
R
Auxiliary power source Constant value of 0. The alternative power source is not supported.
5
R
DIS Constant value of 0.
8,6
R
Reserved Constant value of 000.
9
R
D1_support Constant value of 0. The
PD72870, 72871 does not support the D1 Power
Management state.
10
R
D2_support Constant value of 1. The
PD72870, 72871 supports the D2 Power Management
state.
15-11
R
PME_support Constant value of 01100.
Preliminary Data Sheet S13925EJ2V0DS00
30
PD72870,72871
3.1.23 Offset_64 Power Management Control/Status Register
This is a 16-bit read-only register that provides control status information of the
PD72870, 72871.
Bits
R/W
Description
1,0
R/W
PowerState Default value is undefined. This field is used both to determine the current power
state of the
PD72870, 72871 and to set the
PD72870, 72871 into a new power state. As D1
is not supported in the current implementation of the
PD72870, 72871, writing of `01' will be
ignored.
00: D0 (DMA contexts: ON, Link Layer: ON)
01: Reserved (D1 state not supported)
10: D2 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon
LinkON being active)
11: D3 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon
LinkON being active, Power can be removed)
The LPS is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal
signal in the
PD72870,72871.
7-2
R
Reserved Constant value of 000000.
8
R/W
PME_En Default value of 0. This field is used to enable the specific power management
features of the
PD72870, 72871.
12-9
R
Data_Select Constant value of 0000.
14,13
R
Data_Scale Constant value of 00.
15
R/W
PME_Status Default value is undefined. A write of `1' clears this bit, while a write of `0' is
ignored.
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
31
PD72870,72871
3.2 CardBus Mode Configuration Register ( CARD_ON=High )
31
24
23
16
15
08
07
00
Device ID
Vendor ID
00H
Status
Command
04H
Class Code
Revision ID
08H
BIST
Header Type
Latency Timer
Cache Line Size
0CH
Base Address 0
10H
Base Address 1 (CardBus Status Reg)
Note
14H
Base Address 2 (CardBus Status Reg)
Note
18H
Base Address 3
1CH
Base Address 4
20H
Base Address 5
24H
CardBus CIS Pointer
Note
28H
Subsystem ID
Subsystem Vendor ID
2CH
Expansion Rom Base Address Register
30H
000000H
Cap_Ptr
34H
00000000H
38H
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
3CH
PCI_OHCI_Control
40H
00000000H
44H
00000000H
48H
00000000H
4CH
Diagnostic register0
50H
Diagnostic register1
54H
Diagnostic register2
58H
Diagnostic register3
5CH
Power Management Capabilities
Next_Item_Ptr
Cap_ID
60H
Data
PMCSR_BSE
Power Management Control/Status
64H
00000000H
68H
00000000H
6CH
User Area (GENERAL_RegisterA)
70H
User Area (GENERAL_RegisterB)
74H
User Area (GENERAL_RegisterC)
78H
User Area (GENERAL_RegisterD)
7CH
CIS Area
Note
80H
FCH
Note Different from PCI Bus Mode Configuration Register.
Preliminary Data Sheet S13925EJ2V0DS00
32
PD72870,72871
3.2.1 Offset_14/18 Base_Address_1/2 Register (CardBus Status Registers)
Bits
R/W
Description
7-0
R
Constant value of 00.
31-8
R/W
-
(1) Function Event Register (FER) ( Base Address 1 ( 2 )+ 0H )
Bits
R/W
Description
0
R
Write Protect (No Use).
Read only as `0'
1
R
Ready Status (No Use).
Read only as `0'
2
R
Battery Voltage Detect 2 (No Use).
Read only as `0'
3
R
Battery Voltage Detect 1 (No Use).
Read only as `0'
4
R/W
General Wakeup
14-5
R
Reserved. Read only as `0'
15
R/W
Interrupt
31-16
R
Reserved. Read only as `0'
(2) Function Event Mask Register (FEMR) ( Base Address 1 ( 2 )+ 4H )
Bits
R/W
Description
0
R
Write Protect (No Use).
Read only as `0'
1
R
Ready Status (No Use).
Read only as `0'
2
R
Battery Voltage Detect 2 (No Use).
Read only as `0'
3
R
Battery Voltage Detect 1 (No Use).
Read only as `0'
4
R/W
General Wakeup Mask
5
R
BAM. Read only as `0'
6
R
PWM. Read only as `0'
13-7
R
Reserved. Read only as `0'
14
R/W
Wakeup Mask
15
R/W
Interrupt
31-16
R
Reserved. Read only as `0'
Preliminary Data Sheet S13925EJ2V0DS00
33
PD72870,72871
(3) Function Reset Status Register (FRSR) ( Base Address 1 ( 2 )+ 8H )
Bits
R/W
Description
0
R
Write Protect (No Use).
Read only as `0'
1
R
Ready Status (No Use).
Read only as `0'
2
R
Battery Voltage Detect 2 (No Use).
Read only as `0'
3
R
Battery Voltage Detect 1 (No Use).
Read only as `0'
4
R/W
General Wakeup Mask
14-5
R
Reserved. Read only as `0'
15
R/W
Interrupt
31-16
R
Reserved. Read only as `0'
(4) Function Force Event Register (FFER) ( Base Address 1 ( 2 )+ CH )
Bits
R/W
Description
0
R
Write Protect (No Use).
Read only as `0'
1
R
Ready Status (No Use).
Read only as `0'
2
R
Battery Voltage Detect 2 (No Use).
Read only as `0'
3
R
Battery Voltage Detect 1 (No Use).
Read only as `0'
4
R/W
General Wakeup Mask
14-5
-
No Use
15
R/W
Interrupt
31-16
R
Reserved. Read only as `0'
3.2.2 Offset_28 Cardbus CIS Pointer
This register specifies start memory address of the Cardbus CIS Area.
Bits
R/W
Description
31-0
R
Starting Pointer of CIS Area.
Constant value of 00000080H.
3.2.3 Offset_80 CIS Area
The
PD72870, 72871 supports external Serial ROM(AT24C02 compatible) interface.
CIS Area Register can be loaded from external Serial ROM in the CIS area when CARD_ON are HIGH.
CARD_ON
CIS_ON
Bus
CIS
FUNCTION
0
1
PCI
OFF
PME
0
0
PCI
ON
CSTSCHG
1
X
Cardbus
ON
CSTSCHG
Preliminary Data Sheet S13925EJ2V0DS00
34
PD72870,72871
4. PHY FUNCTION
4.1 Cable Interface
4.1.1 Connections
Figure 4-1. Cable Interface
+
-
+
-
+
-
+
-
+
-
+
-
56
56
7 k
7 k
Connection Detection Current
C o n n e c t i o n D e t e c t i o n C o m p a r a t o r
T p A p
T p B i a s
T p A n
Driver
R e c e i v e r
Arbitration Comparators
C o m m o n M o d e C o m p a r a t o r s
+
-
+
-
+
-
+
-
56
56
7 k
7 k
T p B p
T p B n
Driver
R e c e i v e r
Arbitration Comparators
C o m m o n M o d e C o m p a r a t o r
C o m m o n M o d e S p e e d C u r r e n t D r i v e r
1
F
2 7 0 p F
5.1 k
+
-
+
-
+
-
+
-
+
-
+
-
56
56
7 k
7 k
Connection Detection Current
C o n n e c t i o n D e t e c t i o n C o m p a r a t o r
T p A p
T p B i a s
T p A n
Driver
R e c e i v e r
Arbitration Comparators
C o m m o n M o d e C o m p a r a t o r s
1
F
+
-
+
-
+
-
+
-
56
56
7 k
7 k
T p B p
T p B n
Driver
R e c e i v e r
Arbitration Comparators
C o m m o n M o d e C o m p a r a t o r
C o m m o n M o d e S p e e d C u r r e n t d r i v e r
2 7 0 p F
5.1 k
0.01
F
0.01
F
Preliminary Data Sheet S13925EJ2V0DS00
35
PD72870,72871
4.1.2 Cable Interface Circuit
Each port is configured with two twisted-pairs of TpA and TpB.
TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables.
During transmission to the IEEE1394 bus, the Data/Strobe signal received from the Link layer controller is
encoded, converted from parallel to serial and transmitted.
While receiving from the IEEE1394 bus, the Data/Strobe signal from TpA, TpB is converted from serial to parallel
after synchronization by SCLK
Note
, then transmitted to the Link layer controller in 2/4/8 bits according to the data rate
of 100/200/400 Mbps.
The bus arbitration for TpA and TpB and the state of the line are monitored by the built-in comparator. The state of
the 1394 bus is transmitted to the state machine in the LSI.
Note The SCLK is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal signal in the
PD72870,72871.
4.1.3 CPS
An external resistance of 390 k
is connected in series to the power cable to monitor the power of the power
cable. If the cable power falls under 7.5 V there is an indication to the Link layer that the power has failed.
4.1.4 Unused Ports
TpAp, TpAn : Not connected
TpBp, TpBn : AGND
TpBias : Connected to AGND using a 1.0
F load capacitor
4.2 PLL and Crystal Oscillation Circuit
4.2.1 Crystal Oscillation Circuit
To supply the clock of 24.576 MHz 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm.
4.2.2 PLL
The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz).
4.3 PC0-PC2, CMC
CMC shows the bus manager function which corresponds to the c bit of the Self_ID packet and the Contender bit
in the PHY register when the input is High.
The value of CMC can be changed with software through the Link layer; this pin sets the initial value during Power-
on Reset. Use a pull-up or pull-down resistor of 10 k
, based on the device's specification.
The PC0-PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer to
Section 4.3.4.1 of the IEEE1394-1995 specification for information regarding the Pwr_class. The value of Pwr can be
changed with software through the Link layer; this pin sets the initial value during Power-on Reset. Use a pull-up or
pull-down resistor of 10 k
based on the application.
4.4 P_RESETB
Connect an external capacitor of 0.1
F between the pins P_RESETB and GND. If the voltage drops below 0 V, a
reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register.
4.5 RI0, RI1
Connect an external resistor of 9.1 k
to limit the LSI's current.
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
36
PD72870,72871
5. SERIAL ROM INTERFACE
The
PD72870, 72871 provides a serial ROM interface to initialize the 1394 Global Unique ID Register and the
PCI/Cardbus Mode Configuration registers from a serial EEPROM.
5.1 Serial EEPROM Register
Register Address
Register Name
R/W
Base address + 0x930
SUBID register
R/W
Base address + 0x934
LATVAL register
R/W
Base address + 0x938
W_GUIDHi register
R/W
Base address + 0x93C
W_GUIDLo register
R/W
Base address + 0x940
Parameters Write register
R/W
Base address + 0x95C
W_GENERAL register
R/W
Base address + 0x960
W_PHYS register
R/W
Base address + 0x984
W_CIS register
R/W
Remark Base address : Base Address 0 in Configuration register
5.2 Serial EEPROM Register Description
(1) SUBID register (Base address + 0x930)
31
16 15
0
W_SUBSYSID
W_SUBVNDID
Field
Bits
R/W
Default value
Description
W_SUBSYSID
31-16
R/W
0063H
Subsystem ID value. The value is loaded into Subsystem ID register in
Configuration register (offset+2CH bit 31-16).
W_SUBVNDID
15-0
R/W
1033H
Subsystem Vendor ID value. The value is loaded into Subsystem Vendor ID
register in Configuration register (Offset+2CH bit 15-0).
(2) LATVAL register (Base address + 0x934)
31
24 23
16 15
12 11 10
4
3
0
W_MAXLAT
W_MINGNT
- 0 -
1
- 0 -
W_MAX_REC
Field
Bits
R/W
Default value
Description
W_MAXLAT
31-24
R/W
00H
Max Latency value. The value is loaded into Max Latency register in
Configuration register (Offset+3CH bit 31-24).
W_MINGNT
23-16
R/W
00H
Min Grant value. The value is loaded into Min Grant register in Configuration
register (Offset+3CH bit 23-16).
15-12
-
-
Reserved. Write 0 to these bits.
11
-
-
Reserved. Write 1 to this bit.
-
10-4
-
-
Reserved. Write 0 to these bits.
W_MAX_REC
3-0
R/W
9H
MAX__REC value. The value is loaded into the max_rec field of OHCI
BusOption register in OHCI register (Offset+020H bit 15-12).
5
5
5
5
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
37
PD72870,72871
(3) W_GUIDHi register (Base address + 0x938)
31
0
W_GUIDHi
Field
Bits
R/W
Default value
Description
W_GUIDHi
31-0
R/W
Undefined
GlobalUniqueIDHi value. The value is loaded into OHCI GlobalUniqueIDHi
register in OHCI register (Offset+024H bit 31-0).
Please refer to the 1394 Open Host Controller Interface Specification/Release
1.0 [5.5.5].
(4) W_GUIDLo register (Base address + 0x93C)
31
0
W_GUIDLo
Field
Bits
R/W
Default value
Description
W_GUIDLo
31-0
R/W
Undefined
GlobalUniqueIDLo value. The value is loaded into GlobalUniqueIDLo register
in OHCI register (Offset+028H bit 31-0).
Please refer to the 1394 Open Host Controller Interface Specification/Release
1.0 [5.5.5].
(5) Parameters Write register (Base address + 0x940)
31
7
6
4
3
1
0
- 0 -
PAGE_S
- 0 -
PAR
_W
Field
Bits
R/W
Default value
Description
-
31-7
-
-
Reserved. Write 0 to these bits.
PAGE_S
6-4
R/W
000
Write register select page. The bit field returns zero when read.
000: Select SUBID register and LATVAL register.
001: Select W_GUIDHi register and W_GUIDLo register.
010: Select W_GENERAL register (W_GENERAL_0 and W_GENERAL_1).
011: Select W_GENERAL register (W_GENERAL_2 and W_GENERAL_3).
100: Select W_PHYS register (W_ programPhyEnable,
W_aPhyEnhanceEnable).
101: Select W_CIS register (W_CIS_EVEN - W_CIS_ODD).
-
3-1
-
-
Reserved. Write 0 to these bits.
PAR_W
0
R/W
0
Write control signal. The bit field returns zeros when read.
1: Write the value of select page defined PAGE_S. One write transaction is
the units of 8 byte.
0: Ignored.
Preliminary Data Sheet S13925EJ2V0DS00
38
PD72870,72871
(6) W_GENERAL register (Base address + 0x950 - 0x95C)
31
0
W_GENERAL_0 (Base address + 0x950) - W_GENERAL_3 (Base address + 0x95C)
Field
Bits
R/W
Default value
Description
W_GENERAL_0 -
W_GENERAL_3
31-0
R/W
Undefined
User define value. The value is loaded into GENERAL_registerA - D in
Configuration register (Offset+70H - 7BH).
(7) W_PHYS register (Base address + 0x960)
31
10
9
8
7
3
2
0
- 0 -
- 0 -
- 1 -
W_aPhyEnhanceEnable
W_programPhyEnable
Field
Bits
R/W
Default value
Description
-
31-10
-
-
Reserved. Write 0 to these bits.
W_programPhyEnable
9
R/W
1
programPhyEnable bit. The bit is loaded into HCControl registers in OHCI
register ((Offset+50H bit 23) and (54H bit 23)).
Please refer to the 1394 Open Host Controller Interface Specification/Release
1.0 [5.7].
1: P1394a enhancement is supported.
0. P1394a enhancement is not supported.
W_aPhyEnhanceEnable
8
R/W
0
aPhyEnhanceEnable bit. The bit is loaded into HCControl registers in OHCI
register ((Offset+50H bit 23) and (54H bit 23)).
7-3
-
-
Reserved. Write 0 to these bits.
-
2-0
-
-
Reserved. Write 1 to these bits.
(8) W_CIS register (Base address + 0x980 - 0x984)
31
0
W_CIS_EVEN (Base address + 0x980) - W_CIS_ODD (Base address + 0x984)
Field
Bits
R/W
Default value
Description
W_CIS_EVEN -
W_CIS_ODD
31-0
R/W
Undefined
CIS Area value. The value is loaded into CIS Area in Configuration register
(Offset+80H - FCH).
Preliminary Data Sheet S13925EJ2V0DS00
39
PD72870,72871
Table 5-1. Serial EEPROM Memory Map
Bit
Byte
address
7
6
5
4
3
2
1
0
0
W_SUBSYSID(31 : 24)
1
W_SUBSYSID(23 : 16)
2
W_SUBVNDID(15 : 8)
3
W_SUBVNDID( 7 : 0)
4
W_MAXLAT(31 : 24)
5
W_MINGNT(23 : 16)
6
0
0
0
0
1
0
0
0
7
0
0
0
0
W_MAX_REC( 3 : 0)
8
W_GUIDHi(31 : 24)
9
W_GUIDHi(23 : 16)
A
W_GUIDHi(15 : 8)
B
W_GUIDHi( 7 : 0)
C
W_GUIDLo(31 : 24)
D
W_GUIDLo(23 : 16)
E
W_GUIDLo(15 : 8)
F
W_GUIDLo( 7 : 0)
10
W_GENERAL_0(31 : 24)
11
W_GENERAL_0(23 : 16)
12
W_GENERAL_0(15 : 8)
13
W_GENERAL_0( 7 : 0)
:
:
:
:
1C
W_GENERAL_3(31 : 24)
1D
W_GENERAL_3(23 : 16)
1E
W_GENERAL_3(15 : 8)
1F
W_GENERAL_3( 7 : 0)
20
0
0
0
0
0
0
0
0
21
0
0
0
0
0
0
0
0
22
0
0
0
0
0
0
WPE
WPEE
23
0
0
0
0
0
1
1
1
:
:
:
:
28
W_CIS_0(31 : 24)
29
W_CIS_0(23 : 16)
2A
W_CIS_0(15 : 8)
2B
W_CIS_0( 7 : 0)
:
:
:
:
A4
W_CIS_31(31 : 24)
A5
W_CIS_31(23 : 16)
A6
W_CIS_31(15 : 8)
A7
W_CIS_31( 7 : 0)
WPE: W_programPhyEnable, WPEE: W_aPhyEnhanceEnable
Preliminary Data Sheet S13925EJ2V0DS00
40
PD72870,72871
5.3 Load Control
GROM_EN CARD_ON
CIS_ON
Description
0
X
X
No loading.
1
0
1
W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo,
W_GENERAL_0 - W_GENERAL_3, W_programPhyEnable, W_aPhyEnhanceEnable are
loaded.
1
0
0
1
1
X
All parameters (W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC,
W_GUIDHi/Lo, W_GENERAL_0 - W_GENERAL_3, W_programPhyEnable,
W_aPhyEnhanceEnable, W_CIS_EVEN - W_CIS_ODD) are loaded.
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
41
PD72870,72871
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage
V
DD
0.5 to +4.6
V
LVTTL @ (V
I
< 0.5 V + V
DD
)
0.5 to +4.6
V
Input voltage
V
I
PCI @ (V
I
< 3.0 V + V
DD
)
0.5 to +6.6
V
LVTTL @ (V
O
< 0.5 V + V
DD
)
0.5 to +4.6
V
Output voltage
V
O
PCI @ (V
O
< 3.0 V + V
DD
)
0.5 to +6.6
V
Operating temperature
T
A
0 to +70
C
Storage temperature
T
stg
65 to +150
C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Ranges
Parameter
Symbol
Condition
Rating
Unit
Used to clamp reflection on PCI bus.
4.5 to 5.5
V
Power supply voltage
V
DD
3.0 to +3.6
V
Operating temperature
T
A
0 to +70
C
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
42
PD72870,72871
DC Characteristics (V
DD
= 3.3 V
10%, V
SS
= 0 V, T
A
= 0
C to +70
C)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
High-level input voltage
V
IH
2.0
V
DD
+0.5
V
Low-level input voltage
V
IL
0.5
0.8
V
Pin No.
LQFP:153,154
FPBGA:A4,B4
6
mA
High-level output current
I
OH
V
OH
=2.4 V
Pin No.
LQFP:74,76-79,83,84,92
FPBGA:L14,P15,P16,
R13-R15,T14,T15
9
mA
Pin No.
LQFP:153,154
FPBGA:A4,B4
6
mA
Low-level output current
I
OL
V
OL
=0.4 V
Pin No.
LQFP:74,76-79,83,84,92
FPBGA:L14,P15,P16,
R13-R15,T14,T15
9
mA
Input leakage current
I
L
V
IN
= V
DD
or GND
10.0
A
PCI interface
High-level input voltage
V
IH
2.0
5.5
V
Low-level input voltage
V
IL
0.5
0.8
V
High-level output current
I
OH
V
OH
= 2.4 V
2
mA
Low-level output current
I
OL
V
OL
= 0.4 V
9
mA
Input leakage current
I
L
V
IN
= V
DD
or GND
10.0
A
Cable interface
Cable input, 100 Mbps operation
142
260
mV
Cable input, 200 Mbps operation
132
260
mV
Differential input voltage
V
ID
Cable input, 400 Mbps operation
118
260
mV
100 Mbps speed signaling off
1.165
2.515
V
200 Mbps speed signaling
0.935
2.515
V
TpB common mode input voltage
V
ICM
400 Mbps speed signaling
0.523
2.515
V
Differential output voltage
V
0D
Cable output (Test load 55
)
172.0
265.0
mV
100 Mbps speed signaling off
1.665
2.015
V
200 Mbps speed signaling
1.438
2.015
V
TpA common mode output voltage
V
0CM
400 Mbps speed signaling
1.030
2.015
V
100 Mbps speed signaling off
0.81
0.44
mA
200 Mbps speed signaling
4.84
2.53
mA
TpA common mode output current
I
CM
400 Mbps speed signaling
12.40
8.10
mA
Power status threshold voltage
V
TH
CPS
7.5
V
TpBias output voltage
V
TPBIAS
1.665
2.015
V
Preliminary Data Sheet S13925EJ2V0DS00
43
PD72870,72871
Remarks 1. Digital core runs at 3.3 V.
2. PCI Interface can run at 5 or 3.3 V, depending on the choice of 5 V-PCI or 3.3 V-PCI.
3. All other I/Os are 3.3 V driving, and 5 V tolerant.
4. 5 V are used only for 5 V-PCI clamping diode.
3.3 V
Protection Circuit
5.0 V
I/O Buffer
AC Characteristics
PCI Interface
See PCI local bus specification Revision 2.1.
Serial ROM Interface
See AT24C01A/02/04/08/16 Spec. Sheet.
Preliminary Data Sheet S13925EJ2V0DS00
44
PD72870,72871
7. APPLICATION CIRCUIT EXAMPLE
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 5
1 6
1 7
1 8
1 4
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 9
3 8
4 0
160
159
158
157
156
155
154
153
152
151
150
149
148
146
145
144
143
147
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
122
123
121
1 2 0
1 1 9
1 1 8
1 1 7
1 1 6
1 1 5
1 1 4
1 1 3
1 1 2
1 1 1
1 1 0
1 0 9
1 0 8
1 0 6
1 0 5
1 0 4
1 0 3
1 0 7
1 0 2
1 0 1
1 0 0
9 9
9 8
9 7
9 6
9 5
9 4
9 3
9 2
9 1
9 0
8 9
8 8
8 7
8 6
8 5
8 4
8 2
8 3
8 1
L _ V
D D
C L K R U N
P M E
I N T A
P R S T
P C L K
G N T
R E Q
D G N D
A D 3 1
A D 3 0
P C I _ V
D D
A D 2 9
D G N D
A D 2 7
A D 2 6
A D 2 5
A D 2 8
A D 2 4
L _ V
D D
D G N D
C B E 3
I D S E L
A D 2 3
A D 2 2
A D 2 1
A D 2 0
D G N D
A D 1 9
A D 1 8
P C I _ V
D D
A D 1 7
A D 1 6
D G N D
C B E 2
F R A M E
I R D Y
D E V S E L
T R D Y
L _ V
D D
L_V
DD
DGND
DGND
DGND
STOP
AD15
AD14
PCI_V
DD
AD13
AD12
AD11
AD10
AD9
AD8
DGND
L_V
DD
CBE0
AD7
AD6
AD5
AD4
DGND
AD3
AD2
PCI_V
DD
AD1
AD0
IC(N)
DGND
PERR
SERR
PAR
L_V
DD
CBE1
IC(N)
PIN_EN
IC(H)
IC(N)
IC(N)
IC(N)
GROM_SDA
DGND
P_DV
DD
IC(L)
IC(L)
CARD_ON
CIS_ON
GROM_EN
GROM_SCL
DGND
L_V
DD
DGND
P_AV
DD
P_AV
DD
RI1
AGND
AGND
TpA0p
TpA0n
TpB0p
TpB0n
TpA1p
TpA1n
TpB1p
TpB1n
TpA2p
TpA2n
TpB2p
TpB2n
TpBias0
TpBias1
TpBias2
P_AV
DD
AGND
CPS
RI0
AGND
AGND
P_AV
DD
AGND
P _ A V
D D
A G N D
X O
XI
P _ A V
D D
F I L 0
F I L 1
A G N D
A G N D
P _ A V
D D
P _ A V
D D
P _ R E S E T B
L _ V
D D
S U S _ R E S M
P _ D V
D D
IC(L)
C M C
D G N D
D G N D
IC(H)
IC(H)
D G N D
P _ D V
D D
P C 2
P C 1
P C 0
IC(N)
D G N D
IC(N)
IC(N)
IC(N)
IC(N)
IC(N)
P O R T D I S
IC(L)
D G N D
P _ D V
D D
IC(L)
IC(L)
IC(N)
56
0.01
F
5.1
k
0.01
F
0.01
F
5.1
k
5.1
k
270pF
1.0
F
1.0
F
1.0
F
41
42
43
44
45
46
47
48
49
50
51
52
53
55
56
57
58
54
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
79
78
80
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
1 0 pF
1 0 pF
0.1
F
9.1 k
( 0 . 5 % )
3 9 0 k
Vp (Cable Supply Voltage)
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F 33
F
33
F
33
F
3 3
F
33
F
33
F
A n a l o g G N D
A n a l o g G N D
Digital GND
D i g i t a l G N D
D i g i t a l G N D
D i g i t a l G N D
P o w e r
(3.3 V)
56
56
56
56
56
56
56
56
56
56
56
270pF
270pF
Note
Note
Note
Note Common mode choke.
Recommendation : TOKO Part No.857CM-0009 (TYPE B5W)
5
5
5
5
Preliminary Data Sheet S13925EJ2V0DS00
45
PD72870,72871
8. PACKAGE DRAWINGS
S
S
N
J
detail of lead end
R
K
M
L
P
I
S
Q
G
F
M
H
160-PIN PLASTIC LQFP (FINE PITCH) (24x24)
NOTE
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
B
D
G
26.0
0.2
24.0
0.2
0.5 (T.P.)
2.25
J
26.0
0.2
K
C
24.0
0.2
I
0.10
1.0
0.2
L
0.5
0.2
F
2.25
N
P
Q
0.10
1.4
0.1
0.125
0.075
S160GM-50-8ED-3
S
1.7 MAX.
H
0.22
+
0.05
-
0.04
M
0.145
+
0.055
-
0.045
R
3
+
7
-
3
120
121
160
1
4
0
41
80
81
A
B
C
D
Preliminary Data Sheet S13925EJ2V0DS00
46
PD72870,72871
192-PIN PLASTIC FBGA (14 x 14mm)
T
M
N
P
R
F
G
H
J
K
L
B
C
D
E
A
B
1
1 1
1 0
9
8
7
6
5
4
3
2
1 6
1 5
1 4
1 3
1 2
A
14 + 0.1
13.4 + 0.1
9.5
0.3
4.75
14 + 0.1
13.4 + 0.1
4 - C1.0
1.2
I N D E X M A R K
4 - R0.3 MAX.
1.0
0.8
0 . 3 6
0 . 9 6
2 5
0.5
-0.10
+ 0 . 0 5
0 . 1 0 S
0 . 2 0 S
//
S
0 . 0 8
M
A B
S
3 -
1.0
0.35 + 0.1
O
1.31 + 0.15
Preliminary Data Sheet S13925EJ2V0DS00
47
PD72870,72871
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD72870,72871
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M7 98. 8
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