1
Motorola Power Products Division Technical Data
Power Products Division
HIGH AND LOW SIDE DRIVER
The MPIC2112 is a high voltage, high speed, power MOSFET and IGBT driver
with independent high and low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable ruggedized monolithic construction.
Logic inputs are compatible with standard CMOS or LSTTL outputs. The output
drivers feature a high pulse current buffer stage designed for minimum driver
crossconduction. Propagation delays are matched to simplify use in high frequen-
cy applications. The floating channel can be used to drive an Nchannel power
MOSFET or IGBT in the high side configuration which operates from 10 to 600
volts.
Floating Channel Designed for Bootstrap Operation
Fully Operational to +600 V
Tolerant to Negative Transient Voltage
dV/dt Immune
Gate Drive Supply Range from 10 to 20 V
Undervoltage Lockout for Both Channels
Separate Logic Supply
Operating Supply Range from 5 to 20 V
Logic and Power Ground Operating Offset Range from 5 to +5 V
CMOS Schmitttriggered Inputs with Pulldown
Cycle by Cycle Edgetriggered Shutdown Logic
Matched Propagation Delay for Both Channels
Outputs in Phase with Inputs
PRODUCT SUMMARY
VOFFSET
600 V MAX
IO+/
200 mA/400 mA
VOUT
10 20 V
ton/off (typical)
125 & 105 ns
Delay Matching
30 ns
PIN CONNECTIONS
(TOP VIEW)
8
HO
9
VDD
10
HIN
11
SD
12
LIN
13
VSS
14
7
6
5
4
3
2
1
VB
VS
VCC
COM
LO
9
HO
VDD
11
HIN
12
SD
13
LIN
14
VSS
15
8
7
6
5
4
3
2
VB
VS
VCC
COM
LO
14 LEADS PDIP MPIC2112P
16
1
10
16 LEADS SOIC (WIDE BODY)
MPIC2112DW
Order this document
by MPIC2112/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MPIC2112
Device
Package
HIGH AND LOW
SIDE DRIVER
ORDERING INFORMATION
MPIC2112P
PDIP
MPIC2112DW
SOIC WIDE
DW SUFFIX
PLASTIC PACKAGE
CASE 751G02
SOIC WIDE
16
1
P SUFFIX
PLASTIC PACKAGE
CASE 64606
14
1
Motorola, Inc. 1996
MPIC2112
2
Motorola Power Products Division Technical Data
SIMPLIFIED BLOCK DIAGRAM
PULSE
GEN
UV
DETECT
PULSE
FILTER
HV
LEVEL
SHIFT
COM
LO
VCC
VS
VB
HO
R
R
S
Q
VDD
HIN
SD
LIN
VSS
UV
DETECT
DELAY
VDD/VCC
LEVEL
SHIFT
VDD/VCC
LEVEL
SHIFT
R Q
S
R Q
S
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air
conditions.
Rating
Symbol
Min
Max
Unit
High Side Floating Absolute Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
VB
VS
VHO
VCC
VLO
VDD
VSS
VIN
0.3
VB25
VS0.3
0.3
0.3
0.3
VCC25
VSS0.3
625
VB+0.3
VB+0.3
25
VCC+0.3
VSS+25
VCC+0.3
VDD+0.3
VDC
High Side Floating Absolute Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
VB
VS
VHO
VCC
VLO
VDD
VSS
VIN
0.3
VB25
VS0.3
0.3
0.3
0.3
VCC25
VSS0.3
625
VB+0.3
VB+0.3
25
VCC+0.3
VSS+25
VCC+0.3
VDD+0.3
VDC
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
VS
VHO
VCC
VLO
VDD
VSS
VIN
VB25
VS0.3
0.3
0.3
0.3
VCC25
VSS0.3
VB+0.3
VB+0.3
25
VCC+0.3
VSS+25
VCC+0.3
VDD+0.3
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
VHO
VCC
VLO
VDD
VSS
VIN
VS0.3
0.3
0.3
0.3
VCC25
VSS0.3
VB+0.3
25
VCC+0.3
VSS+25
VCC+0.3
VDD+0.3
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
VCC
VLO
VDD
VSS
VIN
0.3
0.3
0.3
VCC25
VSS0.3
25
VCC+0.3
VSS+25
VCC+0.3
VDD+0.3
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
LO
VDD
VSS
VIN
0.3
VCC25
VSS0.3
CC+0.3
VSS+25
VCC+0.3
VDD+0.3
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
DD
VSS
VIN
VCC25
VSS0.3
SS+25
VCC+0.3
VDD+0.3
Logic Input Voltage (HIN, LIN & SD)
SS
VIN
CC25
VSS0.3
CC+0.3
VDD+0.3
Allowable Offset Supply Voltage Transient
dVS/dt
50
V/ns
*Package Power Dissipation @ TA
+25
C
(14 Lead DIP)
(16 SOICWIDE)
PD
1.6
1.25
Watt
Thermal Resistance, Junction to Ambient
(14 Lead DIP)
(16 SOICWIDE)
R
JA
75
100
C/W
Operating and Storage Temperature
Tj, Tstg
55
150
C
Lead Temperature for Soldering Purposes, 10 seconds
TL
260
C
RECOMMENDED OPERATING CONDITIONS
The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended condi-
tions. The VS and VSS offset ratings are tested with all supplies biased at 15 V differential.
High Side Floating Supply Absolute Voltage
VB
VS+10
VS+20
V
High Side Floating Supply Offset Voltage
VS
Note 1
600
High Side Floating Output Voltage
VHO
VS
VB
Low Side Fixed Supply Voltage
VCC
10
20
Low Side Output Voltage
VLO
0
VCC
Logic Supply Voltage
VDD
VSS+5
VSS+20
Logic Supply Offset Voltage
VSS
5
5
Logic Input Voltage (HIN, LIN & SD)
VIN
VSS
VDD
Ambient Temperature
TA
40
125
C
Note 1: Logic operational for VS of 5 to +600 V. Logic state held for VS of 5 V to VBS.
MPIC2112
3
Motorola Power Products Division Technical Data
ELECTRICAL CHARACTERISTICS
(TC = 25
C unless otherwise specified)
Characteristic
Symbol
Min
Typ
Max
Unit
STATIC ELECTRICAL CHARACTERISTICS SUPPLY CHARACTERISTICS
VBIAS (VCC, VBS, VDD) = 15 V and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are referenced to COM or VSS and are applicable to
the respective output leads: HO or LO.
Logic "1" Input Voltage
VIH
9.5
V
Logic "0" Input Voltage
VIL
6.0
High Level Output Voltage, VBIASVO @ VIN = VIH, IO = 0 A
VOH
100
mV
Low Level Output Voltage, VO @ VIN = VIL, IO = 0 A
VOL
100
Offset Supply Leakage Current @ VB = VS = 600 V
ILK
50
A
Quiescent VBS Supply Current @ VIN = 0 V or VDD
IQBS
25
60
Quiescent VCC Supply Current @ VIN = 0 V or VDD
IQCC
80
180
Quiescent VDD Supply Current @ VIN = 0 V or VDD
IQDD
2.0
5.0
Logic "1" Input Bias Current @ VIN = 15 V
IIN+
20
40
Logic "0" Input Bias Current @ VIN = 0 V
IIN
1.0
VBS Supply Undervoltage Positive Going Threshold
VBSUV+
7.4
9.6
V
VBS Supply Undervoltage Negative Going Threshold
VBSUV
7.0
9.2
VCC Supply Undervoltage Positive Going Threshold
VCCUV+
7.6
9.6
VCC Supply Undervoltage Negative Going Threshold
VCCUV
7.2
9.2
Output High Short Circuit Pulsed Current
@ VOUT = 0 V, VIN = 15 V, PW
10
s
IO+
200
250
mA
Output Low Short Circuit Pulsed Current
@ VOUT = 15 V, VIN = 0 V, PW
10
s
IO
420
500
DYNAMIC ELECTRICAL CHARACTERISTICS
VBIAS (VCC, VBS, VDD) = 15 V and VSS = COM unless otherwise specified. TA = 25
C.
TurnOn Propagation Delay @ VS = 0 V
ton
125
180
ns
TurnOff Propagation Delay @ VS = 600 V
toff
105
160
Shutdown Propagation Delay @ VS = 600 V
tsd
105
160
TurnOn Rise Time @ CL = 1000 pF
tr
80
130
TurnOff Fall Time @ CL = 1000 pF
tf
40
65
Delay Matching, HS & LS TurnOn/Off
MT
30
TYPICAL CONNECTION
TO
LOAD
10 TO 600 V
VDD
HIN
SD
VSS
VS
HO
VB
LIN
VDD
HIN
SD
VSS
LIN
VCC
LO
VCC
COM
MPIC2112
4
Motorola Power Products Division Technical Data
LEAD DEFINITIONS
Symbol
Lead Description
VDD
Logic Supply
HIN
Logic Input for High Side Gate Driver Output (HO), In Phase
SD
Logic Input for Shutdown
LIN
Logic Input for Low Side Gate Driver Output (LO), In Phase
VSS
Logic Ground
VB
High Side Floating Supply
HO
High Side Gate Drive Output
VS
High Side Floating Supply Return
VCC
Low Side Supply
LO
Low Side Gate Drive Output
COM
Low Side Return
Figure 1. Input / Output Timing Diagram
Figure 2. Switching Time Waveform
Definitions
Figure 3. Deadtime Waveform Definitions
HIN
LIN
SD
HO
LO
HIN
LIN
HO
LO
10%
10%
90%
90%
ton
tr
50%
50%
toff
tf
Figure 4. Delay Matching Waveform
Definitions
50%
90%
HO
LO
SD
tsd
10%
50%
50%
90%
HIN
LIN
LO
HO
LO
HO
MT
MT
MPIC2112
5
Motorola Power Products Division Technical Data
PACKAGE DIMENSIONS
CASE 64606
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
1
7
14
8
B
A
F
H
G
D
K
C
N
L
J
M
SEATING
PLANE
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.715
0.770
18.16
19.56
B
0.240
0.260
6.10
6.60
C
0.145
0.185
3.69
4.69
D
0.015
0.021
0.38
0.53
F
0.040
0.070
1.02
1.78
G
0.100 BSC
2.54 BSC
H
0.052
0.095
1.32
2.41
J
0.008
0.015
0.20
0.38
K
0.115
0.135
2.92
3.43
L
0.300 BSC
7.62 BSC
M
0
10
0
10
N
0.015
0.039
0.39
1.01
_
_
_
_
CASE 751G02
ISSUE A
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
10.15
10.45
0.400
0.411
B
7.40
7.60
0.292
0.299
C
2.35
2.65
0.093
0.104
D
0.35
0.49
0.014
0.019
F
0.50
0.90
0.020
0.035
G
1.27 BSC
0.050 BSC
J
0.25
0.32
0.010
0.012
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
10.05
10.55
0.395
0.415
R
0.25
0.75
0.010
0.029
M
B
M
0.010 (0.25)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
B
P
8X
G
14X
D
16X
SEATING
PLANE
T
S
A
M
0.010 (0.25)
B
S
T
16
9
8
1
F
J
R
X 45
_
_
_
_
_
M
C
K
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