MOTOROLA CMOS LOGIC DATA
1
MC14076B
4-Bit D-Type Register
with Three-State Outputs
The MC14076B 4Bit Register consists of four Dtype flipflops operating
synchronously from a common clock. OR gated outputdisable inputs force
the outputs into a highimpedance state for use in bus organized systems.
OR gated datadisable inputs cause the Q outputs to be fed back to the D
inputs of the flipflops. Thus they are inhibited from changing state while the
clocking process remains undisturbed. An asynchronous master root is
provided to clear all four flipflops simultaneously independent of the clock
or disable inputs.
ThreeState Outputs with Gated Control Lines
Fully Independent Clock Allows Unrestricted Operation for the Two
Modes: Parallel Load and Do Nothing
Asynchronous Master Reset
Four Bus Buffer Registers
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two LowPower TTL Loads or One LowPower
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage
0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
10
mA
PD
Power Dissipation, per Package
500
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature (8Second Soldering)
260
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic "L" Packages: 12 mW/
_
C From 100
_
C To 125
_
C
FUNCTION TABLE
Inputs
Output
Q
Reset
Clock
Data Disable
Data
D
Output
Q
Reset
Clock
A
B
Data
D
Output
Q
1
X
X
X
X
0
0
0
X
X
X
Qn
0
1
X
X
Qn
0
X
1
X
Qn
0
0
0
0
0
0
0
0
1
1
When either output disable A or B (or both) is (are) high the
output is disabled to the highimpedance state; however
sequential operation of the flipflops is not affected.
X = Don't Care.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
MC14071B thru MC14073B,
MC14075B
See Page 6-5
MC14076B
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
Ceramic
MC14XXXBD
SOIC
TA = 55
to 125
C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
BLOCK DIAGRAM
15
14
13
12
11
10
9
7
2
1
3
4
5
6
RESET
D0
D1
D2
D3
B
A
CLOCK
B
A
DATA
DISABLE
OUTPUT
DISABLE
VDD = PIN 16
VSS = PIN 8
Q0
Q1
Q2
Q3
MOTOROLA CMOS LOGIC DATA
MC14076B
2
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
55
_
C
25
_
C
125
_
C
Unit
Characteristic
Symbol
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
"0" Level
Vin = VDD or 0
"1" Level
Vin = 0 or VDD
VOL
5.0
10
15
--
--
--
0.05
0.05
0.05
--
--
--
0
0
0
0.05
0.05
0.05
--
--
--
0.05
0.05
0.05
Vdc
"1" Level
Vin = 0 or VDD
VOH
5.0
10
15
4.95
9.95
14.95
--
--
--
4.95
9.95
14.95
5.0
10
15
--
--
--
4.95
9.95
14.95
--
--
--
Vdc
Input Voltage
"0" Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
"1" Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIL
5.0
10
15
--
--
--
1.5
3.0
4.0
--
--
--
2.25
4.50
6.75
1.5
3.0
4.0
--
--
--
1.5
3.0
4.0
Vdc
"1" Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
--
--
--
3.5
7.0
11
2.75
5.50
8.25
--
--
--
3.5
7.0
11
--
--
--
Vdc
Output Drive Current
(VOH = 2.5 Vdc)
Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
--
--
--
--
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
--
--
--
--
1.7
0.36
0.9
2.4
--
--
--
--
mAdc
(VOL = 0.4 Vdc)
Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL
5.0
10
15
0.64
1.6
4.2
--
--
--
0.51
1.3
3.4
0.88
2.25
8.8
--
--
--
0.36
0.9
2.4
--
--
--
mAdc
Input Current
Iin
15
--
0.1
--
0.00001
0.1
--
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
--
--
--
--
5.0
7.5
--
--
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
--
--
--
5.0
10
20
--
--
--
0.005
0.010
0.015
5.0
10
20
--
--
--
150
300
600
Adc
Total Supply Current**
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
IT = (0.75
A/kHz) f + IDD
IT = (1.50
A/kHz) f + IDD
IT = (2.25
A/kHz) f + IDD
Adc
ThreeState Leakage Current
ITL
15
--
0.1
--
0.0001
0.1
--
3.0
Adc
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
** The formulas given are for the typical characteristics only at 25
_
C.
To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk
where: IT is in
A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.002.
MOTOROLA CMOS LOGIC DATA
3
MC14076B
SWITCHING CHARACTERISTICS*
(CL = 50 pF, TA = 25
_
C)
Characteristic
Symbol
VDD
Vdc
Min
Typ #
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH, tTHL
5.0
10
15
--
--
--
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 92 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
tPLH, tPHL
5.0
10
15
--
--
--
300
125
90
600
250
180
ns
Reset to Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 92 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
5.0
10
15
--
--
--
300
125
90
600
250
180
3State Propagation Delay, Output "1" or "0"
to High Impedance
tPHZ, tPLZ
5.0
10
15
--
--
--
150
60
45
300
120
90
ns
3State Propagation Delay, High Impedance
to "1" or "0" Level
tPZH, tPZL
5.0
10
15
--
--
--
200
80
60
400
160
120
ns
Clock Pulse Width
tWH
5.0
10
15
260
110
80
130
55
40
--
--
--
ns
Reset Pulse Width
tWH
5.0
10
15
370
150
110
185
75
55
--
--
--
ns
Data Setup Time
tsu
5.0
10
15
30
10
4
15
5
2
--
--
--
ns
Data Hold Time
th
5.0
10
15
130
60
50
65
30
25
--
--
--
ns
Data Disable Setup Time
tsu
5.0
10
15
220
80
50
110
40
25
--
--
--
ns
Clock Pulse Rise and Fall Time
tTLH, tTHL
5.0
10
15
--
--
--
--
--
--
15
5
4
s
Clock Pulse Frequency
fcl
5.0
10
15
--
--
--
3.6
9.0
12
1.8
4.5
6.0
MHz
* The formulas given are for the typical characteristics only at 25
_
C.
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MOTOROLA CMOS LOGIC DATA
MC14076B
4
Figure 1. Timing Diagram
INPUT RISE AND FALL 20 ns
D
INPUT
INFORMATION
VDD
VSS
VSS
VOH
VOL
VDD
Q
OUTPUT
90%
50%
10%
tsu
th
tsu
th
20 ns
90%
10%
50%
90%
10%
tTLH
tPHL
tTHL
50%
tWH
tWL
fcl
RESET = 0
DATA DISABLE A AND B = 0
OUTPUT DISABLE A AND B = 0
Figure 2. ThreeState Propagation Delay
Waveshape and Circuit
MC14076B
OTHER
INPUTS
OUTPUT
DISABLE
A OR B
ANY Q
OUTPUT
RL = 1 k
CL
VDD FOR tPLZ AND tPZL
VSS FOR tPHZ AND tPZH
OUTPUT
DISABLE
A OR B
ANY Q
OUTPUT
ANY Q
OUTPUT
20 ns
20 ns
VDD
VSS
VOH
90%
50%
50%
10%
tPLZ
tPZL
90%
tPZH
tPHZ
90%
10%
10%
2.5 V @ VDD = 5 V,
10 V, AND 15 V
2 V @ VDD = 5 V
6 V @ VDD = 10 V
10 V @ VDD = 15 V
VOL
OUTPUTS
CONNECTED
OUTPUTS
DISCONNECTED
OUTPUTS
CONNECTED
tPLH
EQUIVALENT
FUNCTIONAL BLOCK DIAGRAM
OUTPUT DISABLE A
OUTPUT DISABLE B
D0
1
2
14
DATA DISABLE A
DATA DISABLE B
9
10
D1 13
CLOCK
7
D2 12
D3
11
RESET 15
6
Q3
5
Q2
4
Q1
3
Q0
D
Q
R
C
Q
D
Q
R
C
Q
D
Q
R
C
Q
D
Q
R
C
Q
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
D2
D1
D0
R
VDD
A
B
D3
Q1
B
A
VSS
C
Q3
Q2
Q0
OUTPUT
DISABLE
DATA
DISABLE
{
}
MOTOROLA CMOS LOGIC DATA
5
MC14076B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64808
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1
8
9
16
K
PLANE
T
M
A
M
0.25 (0.010)
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.740
0.770
18.80
19.55
B
0.250
0.270
6.35
6.85
C
0.145
0.175
3.69
4.44
D
0.015
0.021
0.39
0.53
F
0.040
0.70
1.02
1.77
G
0.100 BSC
2.54 BSC
H
0.050 BSC
1.27 BSC
J
0.008
0.015
0.21
0.38
K
0.110
0.130
2.80
3.30
L
0.295
0.305
7.50
7.74
M
0
10
0
10
S
0.020
0.040
0.51
1.01
_
_
_
_
L SUFFIX
CERAMIC DIP PACKAGE
CASE 62010
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
A
B
T
F
E
G
N
K
C
SEATING
PLANE
16 PL
D
S
A
M
0.25 (0.010)
T
16 PL
J
S
B
M
0.25 (0.010)
T
M
L
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.750
0.785
19.05
19.93
B
0.240
0.295
6.10
7.49
C
0.200
5.08
D
0.015
0.020
0.39
0.50
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
0.100 BSC
2.54 BSC
H
0.008
0.015
0.21
0.38
K
0.125
0.170
3.18
4.31
L
0.300 BSC
7.62 BSC
M
0
15
0
15
N
0.020
0.040
0.51
1.01
_
_
_
_
16
9
1
8
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