4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

4Mb
ZBT

SRAM

FEATURES

· High frequency and 100 percent bus utilization
· Fast cycle times: 6ns, 7.5ns and 10ns
· Single +3.3V ±5% power supply (V

)

· Separate +3.3V or +2.5V isolated output buffer

supply (V

· Advanced control logic for minimum control signal

interface

· Individual BYTE WRITE controls may be tied LOW
· Single R/W# (read/write) control pin
· CKE# pin to enable clock and suspend operations
· Three chip enables for simple depth expansion
· Clock-controlled and registered addresses, data

I/Os and control signals

· Internally self-timed, fully coherent WRITE
· Internally self-timed, registered outputs to

eliminate the need to control OE#

· SNOOZE MODE for reduced-power standby
· Common data inputs and data outputs
· Linear or interleaved burst modes
· Burst feature (optional)
· Pin/function compatibility with 2Mb, 8Mb, and

16Mb ZBT SRAM family

· Automatic power-down
· 165-pin FBGA package
· 100-pin TQFP package

OPTIONS

MARKING

· Timing (Access/Cycle/MHz)

3.5ns/6ns/166 MHz

-6

4.2ns/7.5ns/133 MHz

-7.5

5ns/10ns/100 MHz

-10

· Configurations

3.3V I/O

256K x 18

MT55L256L18P1

128K x 32

MT55L128L32P1

128K x 36

MT55L128L36P1

2.5V I/O

256K x 18

MT55L256V18P1

128K x 32

MT55L128V32P1

128K x 36

MT55L128V36P1

· Package

100-pin TQFP

165-pin FBGA

· Operating Temperature Range

Commercial (0°C to +70°C)

None

Industrial (-40°C to +85°C)**

Part Number Example:

MT55L256L18P1T-10

MT55L256L18P1, MT55L256V18P1,
MT55L128L32P1, MT55L128V32P1,
MT55L128L36P1, MT55L128V36P1

3.3V V

, 3.3V or 2.5V I/O

NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).

100-Pin TQFP

* A Part Marking Guide for the FBGA devices can be found on Micron's

Web site--

http://www.micron.com/support/index.html.

** Industrial temperature range offered in specific speed grades and

configurations. Contact factory for more information.

165-Pin FBGA

GENERAL DESCRIPTION

The Micron

Zero Bus Turnaround

(ZBT

) SRAM

family employs high-speed, low-power CMOS designs
using an advanced CMOS process.

Micron's 4Mb ZBT SRAMs integrate a 256K x 18,

128K x 32, or 128K x 36 SRAM core with advanced syn-
chronous peripheral circuitry and a 2-bit burst counter.
These SRAMs are optimized for 100 percent bus utiliza-
tion, eliminating any turnaround cycles when
transitioning from READ to WRITE, or vice versa. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams

for detailed information.

FUNCTIONAL BLOCK DIAGRAM

256K x 18

SA0, SA1, SA

MODE

BWa#

BWb#

R/W#

CE#
CE2

CE2#

OE#

READ LOGIC

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST
LOGIC

SA0'

SA1'

D1
D0

Q1
Q0

SA0

SA1

ADV/LD#

CLK

CKE#

DQPa
DQPb

INPUT

D
A

S
T
E
E
R

N
G

O
U

T
P

B
U
F
F
E
R
S

S
E

P
S

O
U

T
P

R
E
G

S
T
E
R
S

256K x 9 x 2

MEMORY

ARRAY

WRITE

DRIVERS

INPUT

MODE

BWa#

BWb#

BWc#

BWd#

R/W#

CE#
CE2

CE2#

OE#

READ LOGIC

DQs

DQPa
DQPb

DQPc

DQPd

D
A

S
T
E
E
R

N
G

O
U

T
P

B
U
F
F
E
R
S

128K x 8 x 4

(x32)

128K x 9 x 4

(x36)

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST
LOGIC

SA0'

SA1'

D1
D0

Q1
Q0

SA0

SA1

ADV/LD#

INPUT

S
E

P
S

O
U

T
P

R
E
G

S
T
E
R
S

CLK

CKE#

WRITE

DRIVERS

SA0, SA1, SA

FUNCTIONAL BLOCK DIAGRAM

128K x 32/36

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables
for easy depth expansion (CE2, CE2#), cycle start input
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc#, and BWd#) and
read/write (R/W#).

Asynchronous inputs include the output enable

(OE#, which may be tied LOW for control signal minimi-
zation), clock (CLK) and snooze enable (ZZ, which may
be tied LOW if unused). There is also a burst mode pin
(MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left
unconnected if burst is unused. The data-out (Q), en-
abled by OE#, is registered by the rising edge of CLK.
WRITE cycles can be from one to four bytes wide as
controlled by the write control inputs.

All READ, WRITE and DESELECT cycles are initi-

ated by the ADV/LD# input. Subsequent burst ad-
dresses can be internally generated as controlled by
the burst advance pin (ADV/LD#). Use of burst mode
is optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap
around after the fourth access from a base address.

To allow for continuous, 100 percent use of the data

bus, the pipelined ZBT SRAM uses a LATE LATE WRITE
cycle. For example, if a WRITE cycle begins in clock
cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The data associated with the address is
required two cycles later, or on the rising edge of clock
cycle three.

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa# con-
trols DQa pins; BWb# controls DQb pins; BWc# controls
DQc pins; and BWd# controls DQd pins. Cycle types
can only be defined when an address is loaded, i.e.,
when ADV/LD# is LOW. Parity/ECC bits are only avail-
able on the x18 and x36 versions.

Micron's 4Mb ZBT SRAMs operate from a +3.3V V

power supply, and all inputs and outputs are LVTTL-
compatible. Users can choose either a 2.5V or 3.3V I/O
version. The device is ideally suited for systems requir-
ing high bandwidth and zero bus turnaround delays.

Please refer to Micron's Web site (

www.micron.com/

sramds

) for the latest data sheet.

GENERAL DESCRIPTION (continued)

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

PIN# x18

x32

x36

PIN# x18

x32

x36

PIN# x18

x32

x36

TQFP PIN ASSIGNMENT TABLE

PIN# x18

x32

x36

DQc

S S

DQc

DQb

DQc

DQb

DQc

S S

DQb

DQc

DQb

DQc

S S

DQb

DQd

DQb

DQd

S S

DQb

DQd

DQb

DQd

DQb

DQd

* Pins 83 and 84 are reserved for address expansion, 8Mb and 16Mb respectively.

S S

DQd

MODE (LBO#)

SA1

SA0

DNU

S S

DNU

DQa

S S

DQa

S S

DQa

S S

DQa

DQb

DQa

DQb

S S

DQa

DQb

DQa

DQb

DQa

DQb

S S

DQb

NF*

ADV/LD#

OE# (G#)

CKE#

R/W#

CLK

S S

CE2#

BWa#

BWb#

BWc# BWc#

BWd# BWd#

CE2

CE#

100

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

Pin Assignment (Top View)

100-Pin TQFP

SA
SA

NF**
NF**

ADV/LD#

OE# (G#)

CKE#

R/W#

CLK

CE2#

BWa#

BWb#

NC
NC

CE2
CE#

SA
SA

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

DQa

SA
SA
SA
SA
SA
SA
SA

DNU
DNU
V

DNU
DNU

SA0
SA1
SA
SA
SA
SA

MODE
(LBO#)

DQb

x18

SA
SA

NF**
NF**

ADV/LD#

OE# (G#)

CKE#

R/W#

CLK

CE2#

BWa#

BWb#

BWc#

BWd#

CE2
CE#

SA
SA

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

NC/

DQb

DQa

NC/

DQa

SA
SA
SA
SA
SA
SA
SA

DNU
DNU
V

DNU
DNU

SA0
SA1
SA
SA
SA
SA

MODE
(LBO#)

NC/

DQc

DQd

NC/

DQd

x32/x36

*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 83 and 84 are reserved for address expansion, 8Mb and 16Mb respectively.

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

TQFP PIN DESCRIPTIONS

x18

x32/x36

SYMBOL

TYPE

DESCRIPTION

SA0

Input

Synchronous Address Inputs: These inputs are registered

SA1

and must meet the setup and hold times around the

3235, 4450,

rising edge of CLK. Pins 83 and 84 are reserved as address

8082, 99, 100 81, 82, 99, 100

bits for higher-density 8Mb and 16Mb ZBT SRAMs,
respectively. SA0 and SA1 are the two least significant
bits (LSB) of the address field and set the internal burst
counter if burst is desired.

BWa#

Input

Synchronous Byte Write Enables: These active LOW

BWb#

inputs allow individual bytes to be written when a

BWc#

WRITE cycle is active and must meet the setup and hold

BWd#

times around the rising edge of CLK. BYTE WRITEs need
to be asserted on the same cycle as the address. BWs are
associated with addresses and apply to subsequent data.
BWa# controls DQa pins; BWb# controls DQb pins; BWc#
controls DQc pins; BWd# controls DQd pins.

CLK

Input

Clock: This signal registers the address, data, chip
enables, byte write enables and burst control inputs on
its rising edge. All synchronous inputs must meet setup
and hold times around the clock's rising edge.

CE#

Input

Synchronous Chip Enable: This active LOW input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW).

CE2#

Input

Synchronous Chip Enable: This active LOW input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input
can be used for memory depth expansion.

CE2

Input

Synchronous Chip Enable: This active HIGH input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input
can be used for memory depth expansion.

OE#

Input

Output Enable: This

active LOW, asynchronous input

(G#)

enables the data I/O output drivers. G# is the JEDEC-
standard term for OE#.

ADV/LD#

Input

Synchronous Address Advance/Load: When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is
loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW
on ADV/LD# clocks a new address at the CLK rising edge.

CKE#

Input

Synchronous Clock Enable: This active LOW input
permits CLK to propagate throughout the device. When
CKE# is HIGH, the device ignores the CLK input and
effectively internally extends the previous CLK cycle. This
input must meet setup and hold times around the rising
edge of CLK.

Input

Snooze Enable: This active HIGH, asynchronous input
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When ZZ
is active, all other inputs are ignored.

(continued on next page)

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

TQFP PIN DESCRIPTIONS (continued)

x18

x32/x36

SYMBOL

TYPE

DESCRIPTION

R/W#

Input

Read/Write: This input determines the cycle type when
ADV/LD# is LOW and is the only means for determining
READs and WRITEs. READ cycles may not be converted
into WRITEs (and vice versa) other than by loading a
new address. A LOW on this pin permits BYTE WRITE
operations and must meet the setup and hold times
around the rising edge of CLK. Full bus-width WRITEs
occur if all byte write enables are LOW.

(a)

58, 59, 62,

(a)

52, 53,

DQa

Input/

SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb

63, 68, 69,

5659, 62, 63

Output

pins; Byte "c" is DQc pins; Byte "d" is DQd pins. Input

7274

data must meet setup and hold times around the rising

(b)

8, 9, 12, 13,

(b)

68, 69,

D Q b

edge of CLK.

18, 19, 2224

7275, 78, 79

(c)

2, 3, 69,

DQc

12, 13

(d)

18, 19,

D Q d

2225, 28, 29

N/A

NC/

DQa

NC/

No Connect/Data Bits: On the x32 version, these pins are

NC/

DQb

I/O

no connect (NC) and can be left floating or connected

NC/

DQc

to GND to minimize thermal impedance. On the x36

NC/

DQd

version, these bits are DQs.

MODE

Input

Mode: This input selects the burst sequence. A LOW on

(LBO#)

this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.

1-3, 6, 7, 25,

N/A

N C

No Connect: These pins can be left floating or connected

2830, 5153,

to GND to minimize thermal impedance.

56, 57, 75, 78,

79, 95, 96

83, 84

N F

No Function: These are internally connected to the die
and will have the capacitance of input pins. It is
allowable to leave these pins unconnected or driven by
signals. Reserved for address expansion, pin 83 becomes
an SA at 8Mb density and pin 84 becomes an SA at
16Mb density.

38, 39, 42, 43

DNU

Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.

14, 15, 16, 41,

Supply

Power Supply:

See DC Electrical Characteristics and

65, 66, 91

Operating Conditions for range.

4, 11, 20, 27,

Supply

Isolated Output Buffer Supply:

See DC Electrical

54, 61, 70, 77

Characteristics and Operating Conditions for range.

5, 10, 17, 21,

Supply

Ground:

GND.

26, 40, 55, 60,

67, 71, 76, 90

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

PIN LAYOUT (Top View)

165-Pin FBGA

CE#

CE2

DQb

DQPb

MODE

(LBO#)

BWb#

BWa#

DNU

CE2#

CLK

SA1

SA0

CKE#

R/W#

DNU

ADV/LD#

OE# (G#)

DQa

DQPa

DQa

TOP VIEW

CE#

CE2

DQc

DQd

NC/

DQPc*

DQc

DQd

NC/

DQPd*

MODE

(LBO#)

BWc#

BWd#

BWb#

BWa#

DNU

CE2#

CLK

SA1

SA0

CKE#

R/W#

DNU

ADV/LD#

OE# (G#)

DQb

DQa

NC/

DQPb*

DQb

DQa

NC/

DQPa*

TOP VIEW

x18

x32/x36

*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
NOTE: 1. Pins 9A, and 9B reserved for address pin expansion; 8Mb, and 16Mb respectively.

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

FBGA PIN DESCRIPTIONS

x18

x32/x36

SYMBOL

TYPE

DESCRIPTION

SA0

Input

Synchronous Address Inputs: These inputs are registered and must

SA1

meet the setup and hold times around the rising edge of CLK.

2A, 2B, 3P, 3R, 2A, 2B, 3P, 3R,

4P, 4R, 8P, 8R, 4P, 4R, 8P, 8R,

9P, 9R, 10A,

10B, 10P,

10R, 11A, 11R

10R, 11R

BWa#

Input

Synchronous Byte Write Enables: These active LOW inputs allow

BWb#

individual bytes to be written and must meet the setup and hold

BWc#

times around the rising edge of CLK. A byte write enable is LOW

BWd#

for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For
the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#
controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
controls DQds and DQPd. Parity is only available on the x18 and x36
versions.

CLK

Input

Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock's rising
edge.

CE#

Input

Synchronous Chip Enable: This active LOW input is used to enable
the device. CE# is sampled only when a new external address is
loaded.

CE2#

Input

Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.

CKE#

Input

Synchronous Clock Enable: This active LOW input permits CLK to
propagate throughout the device. When CKE# is HIGH, the device
ignores the CLK input and effectively internally extends the
previous CLK cycle. This input must meet setup and hold times
around the rising edge of CLK.

11H

Input

Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.

R/W#

Input

Read/Write: This input determines the cycle type when ADV/LD# is
LOW and is the only means for determining READs and WRITEs.
READ cycles may not be converted into WRITEs (and vice versa)
other than by loading a new address. A LOW on this pin permits
BYTE WRITE operations and must meet the setup and hold times
around the rising edge of CLK. Full bus-width WRITEs occur if all
byte write enables are LOW.

CE2

Input

Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.

OE#(G#)

Input

Output Enable: This

active LOW, asynchronous input enables the

data I/O output drivers.

(continued on next page)

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

FBGA PIN DESCRIPTIONS (continued)

x18

x32/x36

SYMBOL

TYPE

DESCRIPTION

8 A

ADV/LD#

Input Synchronous Address Advance/Load: When HIGH, this input is

used to advance the internal burst counter, controlling burst
access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new
address at the CLK rising edge.

MODE

Input

Mode: This input selects the burst sequence. A LOW on this input

(LB0#)

selects "linear burst." NC or HIGH on this input selects "interleaved
burst." Do not alter input state while device is operating.

(a)

10J, 10K,

(a)

10J, 10K,

DQa

Input/ SRAM Data I/Os: For the x18 version, Byte "a" is associated DQa's;

10L, 10M, 11D, 10L, 10M, 11J,

Output Byte "b" is associated with DQb's. For the x32 and x36 versions,

11E, 11F, 11G 11K, 11L, 11M

Byte "a" is associated with DQa's; Byte "b" is associated with DQb's;

(b)

1J, 1K,

(b)

10D, 10E,

DQb

Byte "c" is associated with DQc's; Byte "d" is associated with DQd's.

1L, 1M, 2D,

10F, 10G, 11D,

Input data must meet setup and hold times around the rising edge

2E, 2F, 2G

11E, 11F, 11G

of CLK.

(c)

1D, 1E,

DQc

1F, 1G, 2D,

2E, 2F, 2G

(d)

1J, 1K, 1L,

DQd

1M, 2J, 2K,

2L, 2M

11C

11N

NC/

DQPa

NC/

No Connect/Parity Data I/Os: On the x32 version, these are No

11C

NC/

DQPb

I/O

Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b"

NC/

DQPc

parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte

NC/

DQPd

"b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd.

1H, 2H, 4D,

Supply Power Supply:

See DC Electrical Characteristics and Operating

4E, 4F, 4G,

Conditions for range.

4H, 4J, 4K,

4L, 4M, 7N,

8D, 8E, 8F,

8G, 8H, 8J,

8K, 8L, 8M

3C, 3D, 3E,

Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and

3F, 3G, 3J,

Operating Conditions for range.

3K, 3L, 3M,

3N, 9C, 9D,

9E, 9F, 9G,

9J, 9K, 9L,

9M, 9N

(continued on next page)

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

FBGA PIN DESCRIPTIONS (continued)

x18

x32/x36

SYMBOL

TYPE

DESCRIPTION

4C, 4N, 5C,

Supply Ground:

GND.

5D, 5E 5F,

5G, 5H, 5J,

5K, 5L, 5M,

6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F,

6G, 6H, 6J,

6K, 6L, 6M,

7C, 7D, 7E,

7F, 7G, 7H,

7J, 7K, 7L,

7M, 8C, 8N

5P, 5R, 7P, 7R 5P, 5R, 7P, 7R

DNU

Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.

1A, 1B, 1C,

1A, 1B, 1P,

No Connect: These signals are not internally connected and

1D, 1E, 1F,

2C, 2N,

may be connected to ground to improve package heat

1G, 1P, 2C,

2P, 2R, 3H,

dissipation. Pins 9A, and 9B reserved for address pin

2J, 2K, 2L,

5N, 6N, 9A,

expansion; 8Mb, and 16Mb respectively.

2M, 2N, 2P,

9B, 9H, 10C,

2R, 3H, 4B,

10H, 10N,

5A, 5N, 6N,

11A, 11B,

9A, 9B, 9H,

11P

10C, 10D,

10E, 10F,

10G, 10H,

10N, 11B,

11J, 11K,

11L, 11M,

11N, 11P

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

FUNCTION

R/W#

BWa#

BWb#

BWc#

BWd#

READ

WRITE Byte "a"

WRITE Byte "b"

WRITE Byte "c"

WRITE Byte "d"

WRITE All Bytes

WRITE ABORT/NOP

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)

FIRST ADDRESS (EXTERNAL)

SECOND ADDRESS (INTERNAL)

THIRD ADDRESS (INTERNAL)

FOURTH ADDRESS (INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X00

X...X11

X...X10

X...X11

X...X00

X...X01

X...X11

X...X10

X...X01

X...X00

LINEAR BURST ADDRESS TABLE (MODE = LOW)

FIRST ADDRESS (EXTERNAL)

SECOND ADDRESS (INTERNAL)

THIRD ADDRESS (INTERNAL)

FOURTH ADDRESS (INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X10

X...X11

X...X00

X...X10

X...X11

X...X00

X...X01

X...X11

X...X00

X...X01

X...X10

PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36)

NOTE: Using R/W# and BYTE WRITE(s), any one or more bytes may be written.

FUNCTION

R/W#

BWa#

BWb#

READ

WRITE Byte "a"

WRITE Byte "b"

WRITE All Bytes

WRITE ABORT/NOP

PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18)

NOTE: Using R/W# and BYTE WRITE(s), any one or more bytes may

be written.

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

State Diagram for ZBT SRAM

DESELECT

BEGIN

READ

BURST

READ

BEGIN

WRITE

BURST

WRITE

READ

WRITE

BURST

READ

WRITE

READ

BURST

READ

BURST

WRITE

KEY:

COMMAND
DS
READ
WRITE
BURST

OPERATION
DESELECT
New READ
New WRITE
BURST READ,
BURST WRITE, or
CONTINUE DESELECT

BURST

READ

WRITE

NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the

clock (CLK) input and does not change the state of the device.

2. States change on the rising edge of the clock (CLK).

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

TRUTH TABLE

(Notes 510)

OPERATION

ADDRESS

ADV/

USED

CE# CE2# CE2 ZZ

LD#

R/W# BWx OE# CKE#

CLK

NOTES

DESELECT Cycle

None

H High-Z

DESELECT Cycle

None

H High-Z

DESELECT Cycle

None

H High-Z

CONTINUE DESELECT Cycle

None

H High-Z

READ Cycle

External

(Begin Burst)

READ Cycle

1, 11

(Continue Burst)

NOP/DUMMY READ

External

H High-Z

(Begin Burst)

DUMMY READ

H High-Z

1, 2,

(Continue Burst)

WRITE Cycle

External

(Begin Burst)

WRITE Cycle

1, 3,

(Continue Burst)

NOP/WRITE ABORT

None

H High-Z

2, 3

(Begin Burst)

WRITE ABORT

H High-Z

1, 2,

(Continue Burst)

3, 11

IGNORE CLOCK EDGE

Current

(Stall)

SNOOZE MODE

None

High-Z

NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or

WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle
is executed first.

2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A

WRITE ABORT means a WRITE command is given, but no operation is performed.

3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off

the output drivers during a WRITE cycle. Some users may use OE# when the bus turn-on and turn-off times do not meet
their requirements.

4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs

during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK
EDGE cycle.

5. X means "Don't Care." H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,

BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.

6. BWa# enables WRITEs to Byte "a" (DQas); BWb# enables WRITEs to Byte "b" (DQbs); BWc# enables WRITEs to

Byte "c" (DQcs); BWd# enables WRITEs to Byte "d" (DQds).

7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
8. Wait states are inserted by setting CKE# HIGH.
9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.

10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle.
11. The address counter is incremented for all CONTINUE BURST cycles.

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

Supply

Relative to V

.................................... -0.5V to +4.6V

Voltage on V

Q Supply

Relative to V

........................................ -0.5V to V

.................................................. -0.5V to V

Q + 0.5V

Storage Temperature (plastic) ........... -55°C to +150°C
Junction Temperature** ..................................... +150°C
Short Circuit Output Current .............................. 100mA

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Junction temperature depends upon package type,
cycle time, loading, ambient temperature and airflow.
See Micron Technical Note TN-05-14 for more
information.

3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(0°C

+70°C; V

, V

Q = 3.3V ±0.165 unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

2.0

+ 0.3

1, 2

Input High (Logic 1) Voltage

DQ pins

2.0

+ 0.3

1, 2

Input Low (Logic 0) Voltage

-0.3

0.8

1, 2

Input Leakage Current

-1.0

1.0

µA

Output Leakage Current

Output(s) disabled,

-1.0

1.0

µA

Output High Voltage

= -4.0mA

2.4

1, 4

Output Low Voltage

= 8.0mA

0.4

1, 4

Supply Voltage

3.135

3.465

Isolated Output Buffer Supply

3.135

1, 5

NOTE: 1. All voltages referenced to V

(GND).

2. Overshoot:

+4.6V for t

KHKH/2 for I

20mA

Undershoot:

-0.7V for t

KHKH/2 for I

20mA

Power-up:

+3.465V and V

3.135V for t 200ms

3. MODE pin has an internal pull-up, and input leakage = ±10µA.
4. The load used for V

, V

testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O

curves are available upon request.

5. V

Q should never exceed V

. V

and V

Q can be externally wired together to the same power supply for 3.3V I/O

operation.

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(0°C

+70°C; V

= +3.3V ±0.165V; V

Q = +2.5V +0.4V/-0.125V unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

Data bus (DQx)

1.7

Q + 0.3

1, 2

Inputs

1.7

+ 0.3

1, 2

Input Low (Logic 0) Voltage

-0.3

0.7

1, 2

Input Leakage Current

-1.0

1.0

µA

Output Leakage Current

Output(s) disabled,

-1.0

1.0

µA

Q (DQx)

Output High Voltage

= -2.0mA

1.7

= -1.0mA

2.0

Output Low Voltage

= 2.0mA

0.7

= 1.0mA

0.4

Supply Voltage

3.135

3.6

Isolated Output Buffer Supply

2.375

2.9

NOTE: 1. All voltages referenced to V

(GND).

2. Overshoot:

+4.6V for t

KHKH/2 for I

20mA

Undershoot:

-0.7V for t

KHKH/2 for I

20mA

Power-up:

+3.465V and V

3.135V for t 200ms

3. MODE pin has an internal pull-up, and input leakage = ±10µA.
4. This parameter is sampled.

TQFP CAPACITANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

NOTES

Control Input Capacitance

= 25°C; f = 1 MHz

p F

Input/Output Capacitance (DQ)

= 3.3V

Address Capacitance

3.5

Clock Capacitance

3.5

FBGA CAPACITANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

NOTES

Address/Control Input Capacitance

2.5

3.5

p F

Output Capacitance (Q)

= 25°C; f = 1 MHz

p F

Clock Capacitance

2.5

3.5

p F

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

OPERATING CONDITIONS AND MAXIMUM LIMITS

(Note 1) (0°C

+70°C; V

= +3.3V ±0.165V unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL

TYP

-6

-7.5

-10

UNITS NOTES

Power Supply

Device selected; All inputs

Current:

; Cycle time

KC (MIN);

200

500

400

300

2, 3, 4

Operating

= MAX; Outputs open

Power Supply

Device selected; V

= MAX;

Current: Idle

CKE#

;

2, 3, 4

All inputs

+ 0.2 or

- 0.2;

Cycle time

KC (MIN)

CMOS Standby

Device deselected; V

= MAX;

All inputs

+ 0.2 or

- 0.2;

0.5

3, 4

All inputs static; CLK frequency = 0

TTL Standby

Device deselected; V

= MAX;

All inputs

;

3, 4

All inputs static; CLK frequency = 0

Clock Running

Device deselected; V

= MAX;

ADV/LD#

; All inputs

+ 0.2

120

3, 4

- 0.2; Cycle time

KC (MIN)

SNOOZE MODE

0.5

MAX

NOTE: 1. V

Q = +3.3V ±0.165V for 3.3V I/O configuration; V

Q = +2.5V +0.4V/-0.125V for 2.5V I/O

configuration.

2. I

is specified with no output current and increases with faster cycle times. I

Q increases with faster cycle times and

greater output loading.

3. "Device deselected" means device is in a deselected cycle as defined in the truth table. "Device selected" means device

is active (not in deselected mode).

4. Typical values are measured at 3.3V, 25°C and 10ns cycle time.

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

NOTE: 1. This parameter is sampled.

2. Preliminary package data.

FBGA THERMAL RESISTANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS NOTES

Junction to Ambient

Test conditions follow standard test methods

°C/W

1, 2

(Airflow of 1m/s)

and procedures for measuring thermal

Junction to Case (Top)

impedance, per EIA/JESD51.

°C/W

1, 2

Junction to Pins

°C/W

1, 2

(Bottom)

TQFP THERMAL RESISTANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS NOTES

Thermal Resistance

Test conditions follow standard test methods

°C/W

(Junction to Ambient)

and procedures for measuring thermal

Thermal Resistance

impedance, per EIA/JESD51.

2.8

°C/W

(Junction to Top of Case)

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

NOTE: 1. This parameter is sampled.

2. Measured as HIGH above V

and LOW below V

3. Refer to Technical Note TN-55-01, "Designing with ZBT SRAMs," for a more thorough discussion on these parameters.
4. This parameter is sampled.
5. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
6. Transition is measured ±200mV from steady state voltage.
7. OE# can be considered a "Don't Care" during WRITEs; however, controlling OE# can help fine-tune a system for

turnaround timing.

8. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK

when they are being registered into the device. All other synchronous inputs must meet the setup and hold times with
stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising
edge of CLK when ADV/LD# is LOW to remain enabled.

9. Test conditions as specified with output loading shown in Figure 1 for 3.3V I/O (V

Q = +3.3V ±0.165V) and Figure 3 for

2.5V I/O (V

Q = +2.5V +0.4V/-0.125V).

10. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is

defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.

AC ELECTRICAL CHARACTERISTICS

(Notes 6, 8, 9) (0°C

+70°C; V

= +3.3V ±0.165V; ZBT mode)

-6

-7.5

-10

DESCRIPTION

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Clock
Clock cycle time

KHKH

6.0

7.5

Clock frequency

166

133

100

MHz

Clock HIGH time

KHKL

1.7

2.0

3.2

Clock LOW time

KLKH

1.7

2.0

3.2

Output Times
Clock to output valid

KHQV

3.5

4.2

5.0

Clock to output invalid

KHQX

1.5

Clock to output in Low-Z

KHQX1

1.5

2, 3, 4, 5

Clock to output in High-Z

KHQZ

1.5

3.5

1.5

3.5

1.5

3.5

2, 3, 4, 5

OE# to output valid

GLQV

3.5

4.2

5.0

OE# to output in Low-Z

GLQX

2, 3, 4, 5

OE# to output in High-Z

GHQZ

3.5

4.2

5.0

2, 3, 4, 5

Setup Times
Address

AVKH

1.5

1.7

2.0

Clock enable (CKE#)

EVKH

1.5

1.7

2.0

Control signals

CVKH

1.5

1.7

2.0

Data-in

DVKH

1.5

1.7

2.0

Hold Times

Address

KHAX

0.5

Clock enable (CKE#)

KHEX

0.5

Control signals

KHCX

0.5

Data-in

KHDX

0.5

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

V = 1.5V

Z = 50

Figure 1

351

317

5pF

+3.3V

Figure 2

3.3V I/O AC TEST CONDITIONS

Input pulse levels ................................... V

to 3.3V

Input rise and fall times ..................................... 1ns

Input timing reference levels .......................... 1.5V

Output reference levels ................................... 1.5V

Output load ............................. See Figures 1 and 2

LOAD DERATING CURVES

The Micron 256K x 18, 128K x 32, and 128K x 36 ZBT

SRAM timing is dependent upon the capacitive load-
ing on the outputs.

Consult the factory for copies of I/O current versus

voltage curves.

V = 1.25V

Z = 50

Figure 3

225

5pF

+2.5V

Figure 4

2.5V I/O AC TEST CONDITIONS

Input pulse levels ................................... V

to 2.5V

Input rise and fall times ..................................... 1ns

Input timing reference levels ........................ 1.25V

Output reference levels ................................. 1.25V

Output load ............................. See Figures 3 and 4

3.3V I/O Output Load Equivalents

2.5V I/O Output Load Equivalents

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

SNOOZE MODE

SNOOZE MODE is a low-current, "power-down"

mode in which the device is deselected and current is
reduced to I

. The duration of SNOOZE MODE is

dictated by the length of time the ZZ pin is in a HIGH
state. After the device enters SNOOZE MODE, all in-
puts except ZZ become disabled and all outputs go to
High-Z.

The ZZ pin is an asynchronous, active HIGH input

that causes the device to enter SNOOZE MODE. When

the ZZ pin becomes a logic HIGH, I

is guaranteed

after the time

ZZI is met. Any READ or WRITE opera-

tion pending when the device enters SNOOZE MODE
is not guaranteed to complete successfully. Therefore,
SNOOZE MODE must not be initiated until valid pend-
ing operations are completed. Similarly, when exiting
SNOOZE MODE during

RZZ, only a DESELECT or

READ cycle should be given.

SNOOZE MODE ELECTRICAL CHARACTERISTICS

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Current during SNOOZE MODE

2ZP

(P Version)

ZZ active to input ignored

KHKH)

ZZ inactive to input sampled

RZZ

KHKH)

ZZ active to snooze current

ZZI

KHKH)

ZZ inactive to exit snooze current

RZZI

SNOOZE MODE WAVEFORM

SUPPLY

CLK

RZZ

ALL INPUTS

(except ZZ)

DON'T CARE

ISB2Z

ZZI

RZZI

Outputs (Q)

High-Z

DESELECT or READ Only

NOTE: 1. This parameter is sampled.

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

READ/WRITE TIMING

WRITE

D(A1)

CLK

t KHKH

KLKH

KHKL

CE#

KHCX

CVKH

R/W#

CKE#

KHEX

EVKH

BWx#

ADV/LD#

KHAX

AVKH

ADDRESS

KHDX

DVKH

COMMAND

KHQX1

D(A1)

D(A2)

D(A5)

Q(A4)

Q(A3)

D(A2+1)

KHQX

KHQZ

KHQV

WRITE

D(A2)

BURST
WRITE

D(A2+1)

READ

Q(A3)

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

OE#

GLQV

GLQX

GHQZ

KHQX

DON'T CARE

UNDEFINED

Q(A6)

Q(A4+1)

NOTE:

1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most

recent data may be from the input data register.

-6

-7.5

-10

SYM

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

GHQZ

3.5

4.2

5.0

AVKH

1.5

1.7

2.0

EVKH

1.5

1.7

2.0

CVKH

1.5

1.7

2.0

DVKH

1.5

1.7

2.0

KHAX

0.5

KHEX

0.5

KHCX

0.5

KHDX

0.5

READ/WRITE TIMING PARAMETERS

-6

-7.5

-10

SYM

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

KHKH

6.0

7.5

166

133

100

MHz

KHKL

1.7

2.0

3.2

KLKH

1.7

2.0

3.2

KHQV

3.5

4.2

5.0

KHQX

1.5

KHQX1

1.5

KHQZ

1.5

3.5

1.5

3.5

1.5

3.5

GLQV

3.5

4.2

5.0

GLQX

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

NOP, STALL, AND DESELECT CYCLES

READ

Q(A3)

CLK

CE#

R/W#

CKE#

BWx#

ADV/LD#

ADDRESS

D(A4)

COMMAND

Q(A5)

WRITE

D(A4)

STALL

WRITE

D(A1)

READ

Q(A2)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON'T CARE

UNDEFINED

KHQZ

KHQX

D(A1)

Q(A2)

Q(A3)

NOTE:

1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a "pause." A WRITE is not

performed during this cycle.

2. For this waveform, ZZ and OE# are tied LOW.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most

recent data may be from the input data register.

NOP, STALL, AND DESELECT TIMING PARAMETERS

-6

-7.5

-10

SYM

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

KHQX

1.5

KHQZ

1.5

3.5

1.5

3.5

1.5

3.5

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

100-PIN PLASTIC TQFP (JEDEC LQFP)

14.00 ±0.10

1.40 ±0.05

16.00 ±0.20

0.10

+0.10

-0.05

0.15

+0.03

-0.02

22.10

+0.10

-0.20

0.32

+0.06

-0.10

20.10 ±0.10

0.65 TYP

0.625

1.60 MAX

DETAIL A

SEE DETAIL A

0.60 ±0.15

1.00 TYP

GAGE PLANE

0.25

0.10

PIN #1 ID

NOTE: 1. All dimensions in millimeters MAX or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

165-PIN FBGA

NOTE: 1. All dimensions in millimeters MAX or typical where noted.

MIN

10.00

14.00

15.00 ±0.10

1.00

TYP

1.00

TYP

5.00 ±0.05

13.00 ±0.10

PIN A1 ID

BALL A1

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

6.50 ±0.05

7.00 ±0.05

7.50 ±0.05

1.20 MAX

SOLDER BALL MATERIAL:
EUTECTIC 62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø .33mm

SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS Ø 0.40

SEATING PLANE

0.85 ±0.075

0.12 C

165X Ø 0.45

BALL A11

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992

Micron, the Micron logo, and M logo are trademarks and/or service marks of Micron Technology, Inc.

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by

Micron Technology, Inc., and Motorola, Inc.

DATA SHEET DESIGNATIONS

No Marking: This data sheet contains minimum and maximum limits specified over the complete power supply

and temperature range for production devices. Although considered final, these specifications are
subject to change, as further product development and data characterization sometimes occur.

4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L256L18P1_F.p65 Rev. F, Pub. 1/03 EN

4Mb: 256K x 18, 128K x 32/36

PIPELINED ZBT SRAM

REVISION HISTORY

Updated package drawings ................................................................................................................................... January 9/03

Removed "Preliminary Package Data" from front page .............................................................................. February 22/02

Removed 119-pin PBGA package and references ........................................................................................ February 14/02

Removed note "Not Recommended for New Designs," Rev. 6/01 ...................................................................... June 7/01

Added Industrial Temperature note and references, Rev. 3/01, FINAL ......................................................... March 6/01

Added 119-pin PBGA package, Rev. 1/01, FINAL ........................................................................................... January 10/01

Removed FBGA Part Marking Guide, REV 8/00-A, FINAL .............................................................................. August 22/00

Changed FBGA capacitance values, REV 8/00, FINAL ....................................................................................... August 7/00
C

; TYP 2.5pF from 4pF; MAX. 3.5pF from 5pF

; TYP 4pF from 6pF; MAX. 5pF from 7pF

; TYP 2.5pF from 5pF; MAX. 3.5pF from 6pF

Added FBGA Part Marking Guide, Rev. 7/00, Preliminary ................................................................................... July 13/00
Removed 119-pin PBGA package and references

Added 165-pin FBGA package, Rev. 6/00, Preliminary ........................................................................................ May 23/00
Removed all "Smart ZBT" references

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT55L128L32P1