18Mb: 2.5V V

, HSTL, QDRb4 SRAM

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb QDR

SRAM

4-WORD BURST

MT54V1MH18E
MT54V512H36E

eatures

· Separate independent read and write data ports with

concurrent transactions

· 100 percent bus utilization DDR READ and WRITE

operation

· Fast clock to valid data times
· High frequency operation with future migration to

higher clock frequencies

· Full data coherency, providing most current data
· Four-tick burst counter for reduced-address frequency
· Double data rate operation on read and write ports
· Two input clocks (K and K#) for precise DDR timing at

clock rising edges only

· Two output clocks (C and C#) for precise flight time

and clock skew matching--clock and data delivered
together to receiving device

· Optional-use echo clocks (CQ and CQ#) for flexible

receive data synchronization

· Single address bus
· Simple control logic for easy depth expansion
· Internally self-timed, registered writes
· 2.5V core and 1.5 to 1.8V (±0.1V) HSTL I/O
· Clock-stop capability
· 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA package
· User-programmable impedance output
· JTAG boundary scan

General Description

The Micron

QDRTM (Quad Data RateTM) synchro-

nous, pipelined burst SRAM employs high-speed, low-
power CMOS designs using an advanced 6T CMOS
process.

The QDR architecture consists of two separate DDR

(double data rate) ports to access the memory array.
The read port has dedicated data outputs to support
READ operations. The write port has dedicated data
inputs to support WRITE operations. This architecture
eliminates the need for high-speed bus turnaround.
Access to each port is accomplished using a common
address bus. Addresses for reads and writes are latched
on alternate rising edges of the K clock. Each address
location is associated with four words that burst
sequentially into or out of the device. Since data can be
transferred into and out of the device on every rising
edge of both clocks (K, and K# and C and C#) memory
bandwidth is maximized and system design is simpli-
fied by eliminating bus turnarounds.

Options

Marking

NOTE:

1. A Part Marking Guide for the FBGA devices can be found on

Micron's Web site--

http://www.micron.com/numberguide

· Clock Cycle Timing

5ns (200 MHz)

-5

6ns (167 MHz)

-6

7.5ns (133 MHz)

-7.5

10ns (100 MHz)

-10

· Configurations

1 Meg x 18

MT54V1MH18E

512K x 36

MT54V512H36E

· Package

165-ball, 13mm x 15mm FBGA

· Operating Temperature Range

Commercial (0°C

£ T

£ +70°C)

None

Table 1:

Valid Part Numbers

PART NUMBER

DESCRIPTION

MT54V1MH18EF-xx

1 Meg x 18, QDRb4 FBGA

MT54V512H36EF-xx

512K x 36, QDRb4 FBGA

Figure 1: 165-Ball FBGA

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Depth expansion is accomplished with port selects

for each port (read R#, write W#) which are received at
K rising edge. Port selects permit independent port
operation.

All synchronous inputs pass through registers con-

trolled by the K or K# input clock rising edges. Active
LOW byte writes (BWx#) permit byte write or nibble
write selection. Write data and byte writes are regis-
tered on the rising edges of both K and K#. The
addressing within each burst of four is fixed and
sequential, beginning with the lowest and ending with
the highest address. All synchronous data outputs pass
through output registers controlled by the rising edges
of the output clocks (C and C# if provided, otherwise K
and K#).

Four balls are used to implement JTAG test capabili-

ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 2.5V I/O levels to shift data
during this testing mode of operation.

The SRAM operates from a 2.5V power supply, and

all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that benefit
from a high-speed, fully-utilized DDR data bus.

Please refer to Micron's Web site (

www.micron.com/

sramds

) for the latest data sheet.

READ/WRITE Operations

All bus transactions operate on an uninterruptable

burst of four data, requiring two full clock cycles of bus
utilization. Any request that attempts to interrupt a
burst-in-progress is ignored. The resulting benefit is
that the address rate is kept down to the clock fre-
quency even when both buses are 100 percent utilized.

READ cycles are pipelined. The request is initiated

by asserting R# LOW at K rising edge. Data is delivered
after the next rising edge of K, using C and C# as the
output timing references, or using K and K# if C and C#
are tied HIGH. If C and C# are tied HIGH, they may not
be toggled during device operation. Output tri-stating
is automatically controlled such that the bus is
released if no data is being delivered. This permits
banked SRAM systems with no complex output enable
(OE) timing generation. Back-to-back READ cycles are
initiated every second K rising edge. Any command in
between is ignored, since the burst sequence may not
be interrupted and requires two full clock cycles.

WRITE cycles are initiated by W# LOW at K rising

edge. Data is expected at both rising edges of K and K#,
beginning one clock period later. Write registers are
incorporated to facilitate pipelined self-timed WRITE
cycles and provide fully coherent data for all combina-
tions of reads and writes. A read can immediately fol-
low a write even if they are to the same address.
Although the write data has not been written to the
memory array, the SRAM will deliver the data from the
write register instead of using the older data from the
memory array. The latest data is always utilized for all
bus transactions. WRITE cycles are initiated every sec-
ond K rising edge. Any command is ignored, since the
burst sequence may not be interrupted.

BYTE WRITE Operations

BYTE WRITE operations are supported. The active

LOW byte write controls are registered coincident with
their corresponding data. This feature can eliminate
the need for some READ-MODIFY-WRITE cycles, col-
lapsing it to a single BYTE WRITE operation in some
instances.

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Programmable Impedance Output
Buffer

The QDR SRAM is equipped with programmable

impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V

. The value of the

resistor must be five times the desired impedance. For
example, a 350

W resistor is required for an output

impedance of 70

W . To ensure that output impedance

is one-fifth the value of RQ (within 15 percent), the
range of RQ is 175

W to 350W . Alternately, the ZQ ball

can be connected directly to V

Q, which will place

the device in a minimum impedance mode.

Output impedance updates may be required

because over time variations may occur in supply volt-
age and temperature. The device samples the value of
RQ. Impedance updates are transparent to the system;
they do not affect device operation, and all data sheet
timing and current specifications are met during an
update.

The device will power up with an output impedance

set at 50

W . To guarantee optimum output driver

impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.

Clock Considerations

This device does not utilize internal phase-locked

loops and can therefore be placed into a stopped-clock
state to minimize power without lengthy restart times.

It is strontly recommended that the clocks operate for
a number of cycles prior to initiating commands to the
SRAM. This delay permits transmission line charging
effects to be overcome and allows the clock timing to
be nearer to its steady-state value.

Single Clock Mode

The SRAM can be used with the single K, K# clock

pair by tying C and C# HIGH. In this mode, the SRAM
will use K and K# in place of C and C#. This mode pro-
vides the most rapid data output but does not com-
pensate for system clock skew and flight times.

The output echo clocks are precise references to

output data. CQ and CQ# are both rising edge and fall-
ing edge accurate and are 180° out of phase. Either or
both may be used for output data capture. K or C rising
edge triggers CQ rising and CQ# falling edge. CQ rising
edge indicates first data response for QDRI and DDRI
(version 1, non-DLL) SRAM, while CQ# rising edge
indicates first data response for QDRII and DDRII (ver-
sion 2, DLL) SRAM.

Depth Expansion

Port select inputs are provided for the read and

write ports. This allows for easy depth expansion. Both
port selects are sampled on the rising edge of K only.
Each port can be independently selected and dese-
lected and does not affect the operation of the oppo-
site port. All pending transactions are completed prior
to a port deselect.

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Figure 2: Functional Block Diagram

1 Meg x 18; 512K x 36

NOTE:

1. Figure 2 illustrates simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed

information.

2. For 1 Meg x 18, n = 18, a = 18.

For 512K x 36, n = 17, a = 36.

ADDRESS

D (Data In)

BW0#
BW1#

x a

MEMORY

ARRAY

ADDRESS

REGISTRY

& LOGIC

DATA

REGISTRY

& LOGIC

C,C#

K,K#

(Data Out)

CQ, CQ#

(Echo Clock Out)

R
E

T
E

MUX

E
R

T
E

O
U

T
P

O
U

T
P

R
E

F
F
E

P
S

S
E

O
U

T
P

S
E
L
E

C
T

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Figure 3: Application Example

NOTE:

1. Consult Micron Technical Notes for more thorough discussions of clocking schemes.
2. Data capture is possible using only one of the two signals. CQ and CQ# clocks are optional use outputs.
3. For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended

over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs.

Vt = V

REF

C C#

CQ#

D
SA

C C#

D
SA

BUS

MASTER

(CPU

ASIC)

SRAM 1

SRAM 2

DATA IN

DATA OUT

Address

Read#

Write#

BW#

SRAM 1 Input CQ

SRAM 1 Input CQ#

SRAM 2 Input CQ

SRAM 2 Input CQ#

Source K

Source K#

Delayed K

Delayed K#

R = 50

R = 250

CQ#

R = 250

R
#

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Table 2:

1 Meg x 18 Ball Layout (Top View)
165-Ball FBGA

CQ#

NC/

BW1#

BW0#

D10

D11

Q10

Q11

Q12

D12

D13

Q13

REF

D14

Q14

Q15

D15

D16

D17

Q16

Q17

TDO

TCK

TMS

TDI

NOTE:

1. Expansion address: 3A for 36Mb

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Table 3:

512K x 36 Ball Layout (Top View)
165-Ball FBGA

CQ#

BW2#

BW1#

Q27

Q18

D18

BW3#

BW0#

D17

Q17

D27

Q28

D19

D16

D28

D20

Q19

Q16

D15

Q29

D29

Q20

Q15

Q30

Q21

D21

D14

Q14

D30

D22

Q22

Q13

D13

REF

D31

Q31

D23

D12

Q32

D32

Q23

Q12

Q33

Q24

D24

D11

Q11

D33

Q34

D25

D10

D34

D26

Q25

Q10

Q35

D35

Q26

TDO

TCK

TMS

TDI

NOTE:

1. BW2# controls writes to D18:D26
2. BW1# controls writes to D9:D17
3. Expansion address: 9A for 36Mb
4. BW3# controls writes to D27:D35
5. BW0# controls writes to D0:D8

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Table 4:

Ball Descriptions

SYMBOL

TYPE

DESCRIPTION

BW_#

Input

Synchronous Byte Writes: When LOW, these inputs cause their respective bytes to be registered and
written if W# had initiated a WRITE cycle. These signals must meet setup and hold times around the
rising edges of K and K# for each of the four rising edges comprising the WRITE cycle. See Ball Layout
figures for signal to data relationships.

Input

Output Clock: This clock pair provides a user-controlled means of tuning device output data. The rising
edge of C# is used as the output timing reference for first output data. The rising edge of C is used as
the output reference for second output data. Ideally, C# is 180 degrees out of phase with C. C and C#
may be tied HIGH to force the use of K and K# as the output reference clocks instead of having to
provide C and C# clocks. If tied HIGH, these inputs may not be allowed to toggle during device
operation.

Input

Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and
K# during WRITE operations. See Ball Layout figures for ball site location of individual signals. The x18
device uses D0:D17, and the x36 device uses D0:D35.

Input

Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase
with K. All synchronous inputs must meet setup and hold times around the clock rising edges.

Input

Synchronous Read: When LOW, this input causes the address inputs to be registered and a READ cycle
to be initiated. This input must meet setup and hold times around the rising edge of K and is ignored
on the subsequent rising edge of K.

Input

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. See Ball Layout figures for address expansion inputs. All transactions
operate on a burst of four words (two clock periods of bus activity). These inputs are ignored when
both ports are deselected.

TCK

Input

IEEE 1149.1 Clock Input: 2.5V I/O levels. This ball must be tied to V

if the JTAG function is not used in

the circuit.

TMS

TDI

Input

IEEE 1149.1 Test Inputs: 2.5V I/O levels. These balls may be left as No Connects if the JTAG function is
not used in the circuit.

REF

Input

HSTL Input Reference Voltage: Nominally V

Q/2, but may be adjusted to improve system noise

margin. Provides a reference voltage for the HSTL input buffer trip point.

Input

Synchronous Write: When LOW, this input causes the address inputs to be registered and a WRITE
cycle to be initiated. This input must meet setup and hold times around the rising edge of K and is
ignored on the subsequent rising edge of K. This input is also ignored if a READ cycle is being initiated.

Input

Output Impedance Matching Input: This input is used to tune the device outputs to the system data
bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a resistor from this ball to
ground. Alternately, this ball can be connected directly to V

Q to enable the minimum impedance

mode. This ball cannot be connected directly to GND or left unconnected.

CQ#, CQ Output Synchronous Echo Clock Outputs: The edges of these outputs are tightly matched to the synchronous

data outputs and can be used as data valid indication. These signals run freely and do not stop when Q
tri-states.

Output Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K#

rising edges if C and C# are tied HIGH. This bus operates in response to R# commands. See Ball Layout
figures for ball site location of individual signals. The x18 device uses Q0:Q17, and the x36 device uses
Q0:35.

TDO

Output IEEE 1149.1 Test Output: 2.5V I/0 level.

Supply Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions for range.

Supply Power Supply: Isolated Output Buffer Supply. Nominally, 1.5V. 1.8V is also permissible. See DC Electrical

Characteristics and Operating Conditions for range.

Supply Power Supply: GND.

No Connect: These balls are internally connected to the die, but have no function and may be left not
connected to the board to minimize ball count.

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Figure 4:

Bus Cycle State Diagram

NOTE:

1. The address is concatenated with two additional internal LSBs to facilitate BURST operation. The address order is

always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3. Bus cycle is terminated at the end of this sequence
(burst count = 4).

2. State transitions: RD = (R# = LOW); WT = (W# = LOW).
3. Read and write state machines can be simultaneously active. Read and write cannot be simultaneously initiated;

read takes precendence.

4. State machine, control timing sequence is controlled by K.

LOAD NEW

READ ADDRESS;

R_Count=0;

R_Init=1

READ DOUBLE;

R_Count=R_Count+2

INCREMENT READ

ADDRESS BY TWO1

R_Init=0

POWER-UP

Supply

voltage

provided

READ PORT NOP

R_Init=0

RD & R_Count=4

R_Count=2

always

/RD & R_Count=4

/RD

LOAD NEW

WRITE ADDRESS;

W_Count=0

WRITE DOUBLE;

W_Count=W_Count+2

INCREMENT WRITE

ADDRESS BY TWO1

Supply

voltage

provided

WRITE PORT NOP

WT & W_Count=4

WT & R_Init=0

W_Count=2

always

/WT

/WT & W_Count=4

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

NOTE:

1. X means "Don't Care." H means logic HIGH. L means logic LOW.

means rising edge; ¯ means falling edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C

and C# are HIGH, then data outputs are delivered at K and K# rising edges.

3. R# and W# must meet setup and hold times around the rising edge (LOW to HIGH) of K and are registered at the ris-

ing edge of K.

4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification. A0 refers to the initial address input during a WRITE or

READ cycle. A0+1 refers to the next internal burst address in accordance with the burst sequence.

6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential, but permits most rapid restart by

overcoming transmission line charging symmetrically.

7. If this signal was LOW to initiate the previous cycle, this signal becomes a "Don't Care" for this operation; however,

it is strongly recommended that this signal is brought HIGH, as shown in the truth table.

8. This signal was HIGH on previous K clock rising edge. Initiating consecutive READ or WRITE operations on consecu-

tive K clock rising edges is not permitted. The device will ignore the second request.

9. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation,

provided that the setup and hold requirements are satisfied.

10.This table illustrates operation for x18 devices. The x36 device operation is similar except for the addition of BW2#

(controls D18:D26) and BW3# (controls D27:D35).

Table 5:

Truth Table

Notes 18

OPERATION

D or Q

WRITE Cycle:
Load address, input write data on
two consecutive K and K# rising
edges

®H

(A0)

K(t)

(A0 + 1)

K#(t + 1

)

(A0 + 2)

K(t+ 2)

(A0 + 3)

K#(t + 3

)

READ Cycle:
Load address, output data on two
consecutive C and C# rising edges

®H

(A0)

C#(t)

(A0 + 1)

C(t + 1)

(A0 + 2)

C#(t

+ 2)

(A0 + 3)

C(t

+ 3)

NOP: No operation

®H

D = X

Q = High-Z

D = X

Q = High-Z

D = X

Q = High-Z

D = X

Q = High-Z

STANDBY: Clock stopped

Stopped

State

Table 6:

BYTE WRITE Operation

Notes 9, 10

OPERATION

BW0#

BW1#

WRITE D017 at K rising edge

®H

WRITE D017 at K# rising edge

®H

WRITE D08 at K rising edge

®H

WRITE D08 at K# rising edge

®H

WRITE D917 at K rising edge

®H

WRITE D917 at K# rising edge

®H

WRITE nothing at K rising edge

®H

WRITE nothing at K# rising edge

®H

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Absolute Maximum Ratings

Voltage on V

Supply Relative to V

..... -0.5V to +3.4V

Voltage on V

Q Supply

Relative to V

....................................... -0.5V to +V

...................................................... -0.5V to V

+0.5V

Storage Temperature ..............................-55ºC to +125ºC
Junction Temperature .......................................... +125ºC
Short Circuit Output Current .............................. ±70mA

Stresses greater than those listed under Absolute

Maximum Ratings may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.

Maximum Junction Temperature depends upon

package type, cycle time, loading, ambient tempera-
ture, and airflow.

Table 7:

DC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 14; 0°C

£ T

£ +70°C; V

= 2.5V ±0.1V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

IH(DC)

REF

+ 0.1

Q + 0.3

3, 4

Input Low (Logic 0) Voltage

IL(DC)

-0.3

REF

- 0.1

3, 4

Clock Input Signal Voltage

-0.3

Q + 0.3

3, 4

Input Leakage Current

£ V

-5

µA

Output Leakage Current

Output(s) disabled,

£ V

Q (Q)

-5

µA

Output High Voltage

£ 0.1mA

(

LOW

)

Q - 0.2

3, 5, 6

Note 1

Q/2 - 0.12 V

Q/2 + 0.12

3, 5, 6

Output Low Voltage

£ 0.1mA

(

LOW

)

0.2

3, 5, 6

Note 2

Q/2 - 0.12 V

Q/2 + 0.12

3, 5, 6

Supply Voltage

2.4

2.6

Isolated Output Buffer Supply

1.4

1.9

3, 7

Reference Voltage

REF

0.68

0.95

Table 8:

AC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 14; 0°C

£ T

£ +70°C; V

= 2.5V ±0.1V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

+ 0.2

3, 4, 8

Input Low (Logic 1) Voltage

(

)

REF

- 0.2

3, 4, 8

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Table 10: Capacitance

Note 13; notes appear following parameter tables on page 14

Table 11: Thermal Resistance

Note 13; notes appear following parameter tables on page 14

Table 9:

Operating Conditions and Maximum Limits

Notes appear following parameter tables on page 14; 0°C

£ T

£ +70°C; V

= 2.5V ±0.1V unless otherwise noted

MAX

DESCRIPTION

CONDITIONS

SYM

TYP

-5

-6

-7.5

-10

UNITS

NOTES

Operating Supply
Current: DDR

All inputs

£ V

; Cycle time

KHKH (MIN

); Outputs open;

100% bus utilization; 50% address

and data bits toggling on each

clock cycle

x18
x36

TBD

300
410

250
350

230
300

200
260

8, 10

Standby Supply
Current: NOP

KHKH =

KHKH (MIN);

Device in NOP state;

All addresses/data static

SB1

x18
x36

TBD

170
180

145
155

125
135

110
120

10, 11

Stop Clock Current

Cycle time = 0;

Input Static

TBD

Output Supply
Current: DDR
(Information only)

= 15pF

x18
x36

TBD

25
57

21
47

17
38

13
19

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

Address/Control Input Capacitance

= 25ºC; f = 1 MHz

4.5

5.5

Output Capacitance (Q)

Clock Capacitance

5.5

6.5

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS

NOTES

Junction to Ambient
(Airflow of 1m/s)

Soldered on a 4.25 x 1.125 inch,

4-layer printed circuit board

19.4

ºC/W

Junction to Case (Top)

1.0

ºC/W

Junction to Balls (Bottom)

9.6

ºC/W

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Table 12: AC Electrical Characteristics and Recommended Operating Conditions

Notes 13, 1619, notes appear following paramater tables on page 14; °C

£ T

£ +70°C; T

£ +95°C; V

= 2.5V ±0.1V

DESCRIPTION

SYM

-5

-6

-7.5

-10

UNITS

NOTES

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Clock

Clock cycle time (K, K#, C, C#)

KHKH

5.0

6.0

7.5

Clock HIGH time (K, K#, C, C#)

KHKL

2.0

2.4

3.0

3.5

Clock LOW time (K, K#, C, C#)

KLKH

2.0

2.4

3.0

3.5

Clock to clock#

)

KHK#H

2.4

2.7

3.4

4.6

Clock# to clock

(K#

)

K#HKH

2.4

2.7

3.4

4.6

Clock to data clock

)

KHCH

0.0

1.5

0.0

2.00

0.04

2.5

0.0

3.0

Output Times

C, C# HIGH to output valid

CHQV

2.2

2.5

3.0

C, C# HIGH to output hold

CHQX

1.2

C HIGH to output High-Z

CHQZ

2.2

2.5

3.0

C HIGH to output Low-Z

CHQX1

1.2

C, C# HIGH to CQ, CQ# HIGH

CHCQH

1.2

2.3

1.2

2.6

1.2

3.2

1.2

3.2

CQ, CQ# HIGH to output valid

CQHQV

0.35

0.40

0.45

0.50

CQ, CQ# HIGH to output hold

CQHQX

-0.35

-0.40

-0.45

-0.50

CQ HIGH to output High-Z

CQHQZ

0.35

0.40

0.45

0.50

CQ HIGH to output Low-Z

CQHQX1

-0.35

-0.40

-0.45

-0.50

Setup Times

Address valid to K rising edge

AVKH

0.6

0.7

0.8

1.0

Control inputs valid to K rising
edge

IVKH

0.6

0.7

0.8

1.0

Data-in valid to K, K# rising
edge

DVKH

0.6

0.7

0.8

1.0

Hold Times

K rising edge to address hold

KHAX

0.6

0.7

0.8

1.0

K rising edge to control inputs
hold

KHIX

0.6

0.7

0.8

1.0

K, K# rising edge to data-in
hold

KHDX

0.6

0.7

0.8

1.0

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Notes

1. Outputs are impedance-controlled. |I

| =

Q/2)/(RQ/5) for values of 175

W £ RQ £ 350W .

2. Outputs are impedance-controlled. I

= (V

2)/(RQ/5) for values of 175

W £ RQ £ 350W .

3. All voltages referenced to Vss (GND).
4. Overshoot: VIH(

)

£ V

+ 0.7V for t

KHKH/2

Undershoot: VIL(

)

³ -0.5V for t £

KHKH/2

Power-up:

VIH

£ V

Q + 0.3V and V

£ 2.4V

and V

£ 1.4V for t £ 200ms

During normal operation, V

Q must not exceed

. R#, W#, and address signals may not have

pulse widths less than

KHKL (MIN) or operate at

cycle rates less than

KHKH (MIN).

5. AC load current is higher than the shown DC val-

ues. AC I/O curves are available upon request.

6. HSTL outputs meet JEDEC HSTL Class I and Class

II standards.

7. The nominal value of V

Q may be set within the

range of 1.5V to 1.8V DC, and the variation of
V

Q must be limited to ±0.1V DC.

8. To maintain a valid level, the transitioning edge of

the input must:
a. Sustain a constant slew rate from the current AC

level through the target AC level, V

(

) or

(

b. Reach at least the target AC level.
c. After the AC target level is reached, continue to

maintain at least the target DC level, V

(

) or

(

9. I

is specified with no output current and

increases with faster cycle times. I

increases

with faster cycle times and greater output loading.
Typical value is measured at 6ns cycle time.

10. Typical values are measured at V

=2.5V, V

Q =

1.5V, and temperature = 25°C.

11. NOP currents are valid when entering NOP after

all pending READ and WRITE cycles are com-
pleted.

12. Average I/O current and power is provided for

informational purposes only and is not tested.
Calculation assumes that all outputs are loaded
with C

(in farads), f = input clock frequency, half

of outputs toggle at each transition (n = 18 for the
x36), C

= 6pF, V

Q = 1.5V and uses the equa-

tions: Average I/O Power as dissipated by the
SRAM is: P = 0.5 × n × f × V

+ 2C

Average IDDQ = n × f × V

Q x (C

+ C

13. This parameter is sampled.
14. Average thermal resistance between the die and

the case top surface per MIL SPEC 883 Method
1012.1.

15. Junction temperature is a function of total device

power dissipation and device mounting environ-
ment. Measured per SEMI G38-87.8.

16. This is a synchronous device. All addresses, data,

and control lines must meet the specified setup
and hold times for all latching clock edges.

17. Test conditons specified with the output loading,

as shown in Figure 5 unless otherwise noted.

18. Control input signals may not be operated with

pulse widths less than

KHKL (MIN).

19. If C and C# are tied HIGH, then K and K# become

the references for C and C# timing parameters.

20.

CHQX1 is greater than

CHQZ at any given volt-

age and temperature.

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Figure 6:

READ/WRITE Timing

NOTE:

1. Q00 refers to output from address A0 + 1. Q01 refers to output from the next internal burst address following

A0, i.e., A0 + 1.

2. Outputs are disabled (High-Z) one clock cycle after a NOP.
3. In this example, if address A2

= A1, then data Q20 = D10, Q21 = D11, Q22 = D12, Q23 = D13. Write data is forwarded

immediately as read results. (This note applies to whole diagram.)

READ

WRITE

Q00

Q03

D10

D11

D12

D13

tKHKL

tKHK#H

tKHCH

tCHQV

tCHQX

tKLKH

tKHKH

tKHIX

tAVKH tKHAX

tDVKH

tKHDX

tKHCH

Q01

Q02

NOP

Qx2

tDVKH

tKHDX

DON'T CARE

UNDEFINED

tCHQX1

tCQHQX

tCHQV

tCHQX

tCHQZ

IVKH

tKHIX

IVKH

tKHK#H

tKLKH

tKHKH

D30

D31

D32

D33

Q20

Q23

Q21

Q22

CQ#

tCHCQV

tCHCQX

tCQHQX1

tCHCQX

KHKL

tCQHQV

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

IEEE 1149.1 Serial Boundary Scan
(JTAG)

The SRAM incorporates a serial boundary scan test

access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the
set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are
excluded because their inclusion places an added
delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not
conflict with the operation of other devices using
1149.1 fully-compliant TAPs. The TAP operates using
JEDEC-standard 2.5V I/O logic levels.

The SRAM contains a TAP controller, instruction

Disabling the JTAG Feature

It is possible to operate the SRAM without using the

JTAG feature. To disable the TAP controller, TCK must
be tied LOW (V

) to prevent clocking of the device.

TDI and TMS are internally pulled up and may be
unconnected. Alternately, they may be connected to
V

through a pull-up resistor. TDO should be left

unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the opera-
tion of the device.

Test Access Port (TAP)
Test Clock (TCK)

The test clock is used only with the TAP controller.

All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.

Figure 7:

TAP Controller State Diagram

NOTE:

The 0/1 next to each state represents the value
of TMS at the rising edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP

controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information

into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 7. TDI is pulled up
internally and can be unconnected if the TAP is
unused in an application. TDI is connected to the most
significant bit (MSB) of any register, as illustrated in
Figure 8.

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-

out from the registers. The output is active depending
upon the current state of the TAP state machine, as

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

illustrated in Figure 7. The output changes on the fall-
ing edge of TCK. TDO is connected to the least signifi
cant bit (LSB) of any register, as depicted in Figure 8.

Performing a TAP RESET

A RESET is performed by forcing TMS HIGH (V

)

for five rising edges of TCK. This RESET does not affect
the operation of the SRAM and may be performed
while the SRAM is operating.

At power-up, the TAP is reset internally to ensure

that TDO comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO

balls and allow data to be scanned into and out of the
SRAM test circuitry. Only one register can be selected
at a time through the instruction register. Data is seri-
ally loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of
TCK.

Instruction Register

Three-bit instructions can be serially loaded into

the instruction register. This register is loaded when it
is placed between the TDI and TDO balls, as shown in
Figure 8. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state, as described in the previous section.

When the TAP controller is in the Capture-IR state,

the two LSBs are loaded with a binary "01" pattern to
allow for fault isolation of the board-level serial test
data path.

Bypass Register

To save time when serially shifting data through reg-

isters, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the SRAM with mini-
mal delay. The bypass register is set LOW (Vss) when
the BYPASS instruction is executed.

Figure 8:

TAP Controller Block Diagram

NOTE:

X = 106.

Boundary Scan Register

The boundary scan register is connected to all the

input and bidirectional balls on the SRAM. The SRAM
has a 107-bit-long register.

The boundary scan register is loaded with the con-

tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and
SAMPLE Z instructions can be used to capture the
contents of the I/O ring.

The Boundary Scan Order tables show the order in

which the bits are connected. Each bit corresponds to
one of the balls on the SRAM package. The MSB of the
register is connected to TDI, and the LSB is connected
to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-

bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction regis-
ter. The IDCODE is hardwired into the SRAM and can
be shifted out when the TAP controller is in the Shift-
DR state. The ID register has a vendor code and other
information described in the Identification Register
Definitions table.

Bypass Register

Instruction Register

Identification Register

Boundary Scan Register

Selection

Circuitry

Selection

Circuitry

TCK

TMS

TAP CONTROLLER

TDI

TDO

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

TAP Instruction Set
Overview

Eight different instructions are possible with the

three-bit instruction register. All combinations are
listed in the Instruction Codes table. Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.

The TAP controller used in this SRAM is not fully

compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EXTEST or INTEST
or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is

to be executed whenever the instruction register is
loaded with all 0s. EXTEST is not implemented in this
SRAM TAP controller; therefore, this device is not
1149.1-compliant.

The TAP controller does recognize an all-0 instruc-

tion. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a
SAMPLE/PRELOAD instruction has been loaded.
EXTEST does not place the SRAM outputs (including
CQ and CQ#) in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific,

32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI

and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into
the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary

scan register to be connected between the TDI and
TDO balls when the TAP controller is in a Shift-DR
state. It also places all SRAM outputs into a High-Z
state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruc-

tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.

Note that since the PRELOAD part of the command

is not implemented, putting the TAP into the Update-
DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.

BYPASS

When the BYPASS instruction is loaded in the

instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between the TDI
and TDO balls. The advantage of the BYPASS instruc-
tion is that it shortens the boundary scan path when
multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are

reserved for future use. Do not use these instructions.

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Figure 9: TAP Timing

NOTE:

Timing for SRAM inputs and outputs is congruent with TDI and TDO, respectively, as shown in Figure 9.

NOTE:

CS and

CH refer to the setup and hold time requirements of latching data from the boundary scan register.

2. Test conditions are specified using the load in Figure 10.

TLTH

Test Clock

(TCK)

Test Mode Select

(TMS)

tTHTL

Test Data-Out

(TDO)

tTHTH

Test Data-In

(TDI)

tTHMX

tMVTH

tTHDX

tDVTH

tTLOX

tTLOV

DON'T CARE

UNDEFINED

Table 13: TAP DC Electrical Characteristics

Notes 1, 2; 0°C

£ T

£ +70°C; V

= 2.5V ±0.1V

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

Clock

Clock cycle time

THTH

100

Clock frequency

MHz

Clock HIGH time

THTL

Clock LOW time

TLTH

Output Times

TCK LOW to TDO unknown

TLOX

TCK LOW to TDO valid

TLOV

TDI valid to TCK HIGH

DVTH

TCK HIGH to TDI invalid

THDX

Setup Times

TMS setup

MVTH

Capture setup

Hold Times

TMS hold

THMX

Capture hold

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

TAP AC Test Conditions

Input pulse levels........................................V

to 1.8V

Input rise and fall times ......................................... 1ns
Input timing reference levels............................... 0.9V
Output reference levels ........................................ 0.9V
Test load termination supply voltage ................. 0.9V

Figure 10:

TAP AC Output Load Equivalent

NOTE:

1. All voltages referenced to V

(GND).

2. This table defines DC values for TAP control and data balls only. The DQ SRAM balls used in JTAG operation will have

the DC values as defined in Table 7, "DC Electrical Characteristics and Operating Conditions," on page 11.

TDO

0.9V

20pF

Z = 50

Table 14: TAP DC Electrical Characteristics and Operating Conditions

Note 2; 0°C

£ T

£ +70°C; V

= 2.5V ±0.1V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

1.7

+ 0.3

1, 2

Input Low (Logic 0) Voltage

-0.3

0.7

1, 2

Input Leakage Current

£ V

-5.0

5.0

µA

Output Leakage Current

Output(s) disabled,

£ V

-5.0

5.0

µA

Output Low Voltage

OLC

= 100µA

0.2

1, 2

Output Low Voltage

OLT

= 2mA

0.4

1, 2

Output High Voltage

OHC

= -100µA

2.1

1, 2

Output High Voltage

OHT

= -2mA

1.7

1, 2

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Table 15: Identification Register Definitions

INSTRUCTION FIELD

ALL DEVICES

DESCRIPTION

REVISION NUMBER (31:28)

000

Revision number.

DEVICE ID (28:12)

00def0wx0t0q0b0s0

def = 010 for 36Mb density
def = 001 for 18Mb density
wx = 11 for x36 width
wx = 10 for x18 width
wx = 01 for x8 width
t = 1 for DLL version
t = 0 for non-DLL version
q = 1 for QDR
q = 0 for DDR
b = 1 for 4-word burst
b = 0 for 2-word burst
s = 1 for separate I/O
s = 0 for common I/O

MICRON JEDEC ID CODE
(11:1)

00000101100

Allows unique identification of SRAM vendor.

ID Register Presence
Indicator (0)

Indicates the presence of an ID register.

Table 16: Scan Register Sizes

BIT SIZE

Instruction

Bypass

Boundary Scan

107

Table 17: Instruction Codes

INSTRUCTION

CODE

DESCRIPTION

EXTEST

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This
instruction is not 1149.1-compliant.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.

SAMPLE Z

010

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/
PRELOAD

100

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This
instruction does not implement 1149.1 preload function and is therefore not 1149.1-
compliant.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

RESERVED

110

Do Not Use: This instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Table 18: Boundary Scan (Exit) Order

BIT#

FBGA BALL

BIT#

FBGA BALL

BIT#

FBGA BALL

10D

10C

11D

11B

11C

11P

10B

10P

11A

10N

10A

10M

11N

11L

11M

10L

11K

10K

10J

11J

11H

100

10G

101

102

11F

103

11G

104

105

10F

106

11E

107

10E

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.,

NEC, and Samsung.

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Figure 11:

165-Ball FBGA

NOTE:

1. All dimensions are in millimeters.
2. Molding dimensions do not include protrusion; allowable mold protrusion is 0.25mm per side.

Data Sheet Designation

No Marking: This data sheet contains minimum and maximum limits specified over the complete power

supply and temperature range for production devices. Although considered final, these specifications are sub-
ject to change, as further product development and data characterization sometimes occur.

10.00

14.00

15.00 ±0.10

1.00

TYP

1.00

TYP

5.00 ±0.05

13.00 ±0.10

PIN A1 ID

BALL A1

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

6.50 ±0.05

7.00 ±0.05

7.50 ±0.05

1.20 MAX

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb
SOLDER BALL PAD: Ø .33mm

SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS Ø 0.40

SEATING PLANE

0.85 ±0.075

0.12 C

165X Ø 0.45

BALL A11

1 MEG x 18, 512K x 36

2.5V V

, HSTL, QDRb4 SRAM

18Mb: 2.5V V

, HSTL, QDRb4 SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT54V1MH18E_16_F.fm Rev. F, Pub. 3/03

Document Revision History

Rev. F, Pub 3/03 ................................................................................................................................................................3/03

· Updated JTAG Section
· Removed Preliminary Status

Rev. E, Pub 2/03 ...............................................................................................................................................................2/03

· Added definitive notes to Figure 3
· Added definitive note to Table 9
· Updated Truth Table for clarity
· Added 1.5V references
· Update READ/WRITE Timing Diagram
· Updated JTAG section to reflect 1149.1 specification compliance with EXTEST features
· Updated JTAG description to reflect 1149.1 specification compliance with EXTEST feature
· Added definitive note concerning SRAM (DQ) I/O balls used for JTAG DC values and timing
· Changed process information in header to die revision indicator
· Updated Thermal Resistance Values to Table 12:

= 4.5 TYP; 5.5 MAX

= 6 TYP; 7 MAX

= 5.5 TYP; 6.5 MAX

· Updated Thermal Resistance values to Table 12:

= 19.4 TYP

= 1.0 TYP

= 9.6 TYP

· Added T

£ +95°C to Table 13

· Modified Figure 2 regarding depth, configuration, and byte controls

· Added definitive notes regarding I/O behavior during JTAG operation
· Added definitive notes regarding I

test conditions for read to write ratio

· Removed note regarding AC derating information for full I/O range
· Remove references to JTAG scan chain logic levels being at logic zero for NC pins in Tables 5 and 19
· Revised ball description for NC balls:

These balls are internally connected to the die, but have no function and may be left not connected to the
board to minimize ball count.

Rev. D, Pub 6/02...............................................................................................................................................................6/02

· Removed ADVANCE designation
· Added CQ, CQ# to Ball Description table on page 5
· Added note 10 on page 8
· Deleted note 6 on page 9
· Revised note 5 on page 10
· Added "t" and description to Device ID code
· Deleted Boundary Scan (Exit) Order note on page 20

Rev. C, Pub. 5/02, ADVANCE...........................................................................................................................................5/02

· Fixed voltage range error in AC Electrical Characteristics and Operating Conditions table

Rev. B, Pub. 5/02, ADVANCE...........................................................................................................................................8/02

· Updated DC Electrical Characteristics and Operating Conditions table
· Added AC Electrical Characteristics and Operating Conditions table

Rev. A, Pub. 4/02, ADVANCE...........................................................................................................................................4/02

· New ADVANCE data sheet

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT54V1MH18E

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT54V1MH18E