7-54
December 1997
MIC5891
Micrel
MIC5891
Features
High-voltage, high-current outputs
Output transient protection diodes
CMOS-, PMOS-, NMOS-, and TTL-compatible inputs
5MHz typical data input rate
Low-power CMOS latches
Applications
Alphanumeric and bar graph displays
LED and incandescent displays
Relay and solenoid drivers
Other high-power loads
General Description
The MIC5891 latched driver is a high-voltage, high current
integrated circuit comprised of eight CMOS data latches,
CMOS control circuitry for the common STROBE and OUTPUT
ENABLE, and bipolar Darlington transistor drivers for each
latch.
Bipolar/MOS construction provides extremely low power
latches with maximum interface flexibility.
The MIC5891 will typically operate at 5MHz with a 5V logic
supply.
The CMOS inputs are compatible with standard CMOS,
PMOS, and NMOS logic levels. TTL circuits may be used with
appropriate pull-up resistors to ensure a proper logic-high
input.
A CMOS serial data output allows additional drivers to be
cascaded when more than 8 bits are required.
The MIC5891 has open-emitter outputs with suppression
diodes for protection against inductive load transients. The
output transistors are capable of sourcing 500mA and will
sustain at least 35V in the on-state.
Simultaneous operation of all drivers at maximum rated
current requires a reduction in duty cycle due to package
power limitations. Outputs may be paralleled for higher load
current capability.
The MIC5891 is available in a 16-pin plastic DIP package (N)
and 16-pin wide SOIC package (WM).
8-Bit Serial-Input Latched Source Driver
STROBE
4
SERIAL
DATA IN
3
CLOCK
2
GROUND
1
OUT
3
7
OUT
2
6
OUT
1
5
OUT
4
8
LOAD SUPPLY
13
OUTPUT
ENABLE
14
LOGIC SUPPLY
15
SERIAL
DATA OUT
16
OUT
6
10
OUT
7
11
OUT
8
12
OUT
5
9
V
BB
V
DD
OE
SHIFT
REGISTER
LATCHES
Functional Diagram
Pin Configurations
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
SERIAL
DATA OUT
OUTPUT
ENABLE
CLOCK
SERIAL
DATA IN
STROBE
GROUND
8-BIT SERIAL PARALLEL SHIFT REGISTER
LATCHES
MOS
BIPOLAR
Part Number
Temperature Range Package
MIC5891BN
40
C to +85
C
16-Pin Plastic DIP
MIC5891BWM
40
C to +85
C
16-pin Wide SOIC
Ordering Information
December 1997
7-55
MIC5891
Micrel
7
Absolute Maximum Ratings
(Notes 1, 2, 3)
8
53%
47%
41%
7
60%
54%
48%
6
70%
64%
56%
5
83%
75%
67%
4
100%
94%
84%
3
100%
100%
100%
2
100%
100%
100%
1
100%
100%
100%
50
C
60
C
70
C
Number of
Outputs ON at
I
OUT
= 200 mA
Max. Allowable Duty Cycles
at T
A
of:
Allowable Duty Cycles
Typical Circuits
IN
V
DD
Output Voltage (V
OUT
) .............................................. 50V
Logic Supply Voltage Range (V
DD
) ............... 4.5V to 15V
Load Supply Voltage Range (V
BB
) ................ 5.0V to 50V
Input Voltage Range (V
IN
) ................. 0.3V to V
DD
+0.3V
Continuous Collector Current (I
C
) ........................ 500mA
Package Power Dissipation .............................
see graph
Operating Temperature Range (T
A
) ...... 55
C to +125
C
Storage Temperature Range (T
S
) ......... 65
C to +150
C
Note 1:
T
A
= 25
C
Note 2:
Derate at the rate of 20mW/
C above T
A
= 25
C.
Note 3:
Micrel CMOS devices have input-static protection but are
susceptible to damage when exposed to extremely high static
electrical charges.
Typical Output Circuit
V
BB
V
OUT
Typical Input Circuit
0
0.5
1
1.5
2
2.5
25
50
75
100
125
150
PACKAGE POWER DISSIPATION (W)
AMBIENT TEMPERATURE (C)
Allowable Package Power
Dissipation vs. Temp.
PDIP
JA
= 60C/W
CerDIP
JA
= 90C/W
7-56
December 1997
MIC5891
Micrel
Electrical Characteristics
V
BB
= 50V, V
DD
= 5V to 12V; T
A
= +25
C; unless noted.
Limits
Characteristic
Symbol
V
BB
Test Conditions
Min.
Max.
Units
Output Leakage Current
I
CEX
50V
T
A
= +25
C
50
A
T
A
= +85
C
100
A
Output Saturation Voltage
V
CE(SAT)
50V
I
OUT
= 100mA, T
A
= +85
C
1.8
V
I
OUT
= 225mA, T
A
= +85
C
1.9
V
I
OUT
= 350mA, T
A
= +85
C
2.0
V
Output Sustaining Voltage
V
CE(SUS)
50V
I
OUT
= 350mA, L = 2mH
35
V
Input Voltage
V
IN(1)
50V
V
DD
= 5.0V
3.5
V
DD
+0.3
V
V
DD
= 12V
10.5
V
DD
+0.3
V
V
IN(0)
50V
V
DD
= 5V to 12V
V
SS
0.3
0.8
V
Input Current
I
IN(1)
50V
V
DD
= V
IN
= 5.0V
50
A
V
DD
= 12V
240
A
Input Impedance
Z
IN
50V
V
DD
= 5.0V
100
k
V
DD
= 12V
50
k
Maximum Clock Frequency
f
c
50V
3.3
MHz
Serial Data Output Resistance
R
OUT
50V
V
DD
= 5.0V
20
k
V
DD
= 12V
6.0
k
Turn-On Delay
t
PLH
50V
Output Enable to Output, I
OUT
= 350mA
2.0
s
Turnoff Delay
t
PHL
50V
Output Enable to Output, I
OUT
= 350mA
10
s
Supply Current
I
BB
50V
all outputs on, all outputs open
10
mA
all outputs off
200
A
I
DD
50V
V
DD
= 5V, all outputs off, inputs = 0V
100
A
V
DD
= 12V, all outputs off, inputs = 0V
200
A
V
DD
= 5V, one output on, all inputs = 0V
1.0
mA
V
DD
= 12V, one output on, all inputs = 0V
3.0
mA
Diode Leakage Current
I
H
Max
T
A
= +25
C
50
A
T
A
= +85
C
100
A
Diode Forward Voltage
V
F
Open
I
F
= 350mA
2.0
V
Note 4: Positive (negative) current is defined as going into (coming out of) the specified device pin.
Note 5: Operation of these devices with standard TTL may require the use of appropriate pull-up resistors.
Timing Conditions
(V
DD
= 5.0V, Logic Levels are V
DD
and Ground)
A.
Minimum data active time before clock pulse (data set-up time) ........................................................................75ns
B.
Minimum data active time after clock pulse (data hold time) ..............................................................................75ns
C.
Minimum data pulse width .................................................................................................................................150ns
D.
Minimum clock pulse width ...............................................................................................................................150ns
E.
Minimum time between clock activation and strobe .......................................................................................... 300ns
F.
Minimum strobe pulse width ..............................................................................................................................100ns
G.
Typical time between strobe activation and output transition .............................................................................1.0
s
H.
Turnoff delay ................................................................................................................ see Electrical Characteristics
I.
Turn-on delay ............................................................................................................... see Electrical Characteristics
December 1997
7-57
MIC5891
Micrel
7
Applications Information
Serial data present at the input is transferred into the shift
register on the rising edge of the CLOCK input pulse. Additional
CLOCK pulses shift data information towards the SERIAL
DATA OUTPUT. The serial data must appear at the input prior
to the rising edge of the CLOCK input waveform.
The 8 bits present in the shift register are transferred to the
respective latches when the STROBE is high (serial-to-
parallel conversion). The latches will continue to accept new
Truth Table
Serial
Shift Register Contents
Serial
Latch Contents
Output Content
Data
Clock
Data
Strobe
Output
Input
Input
I
1
I
2
I
3
...
I
N-1
I
N
Output
Input
I
1
I
2
I
3
... I
N-1
I
n
Enable
I
1
I
2
I
3
... I
N-1
I
n
H
H
R
1
R
2
... R
N-2
R
N-1
R
N-1
L
L
R
1
R
2
... R
N-2
R
N-1
R
N-1
X
R
1
R
2
R
3
... R
N-1
R
N
R
N
X
X
X
...
X
X
X
L
R
1
R
2
R
3
... R
N-1
R
N
P
1
P
2
P
3
...
P
N-1
P
N
P
N
H
P
1
P
2
P
3
... P
N-1
P
N
L
P
1
P
2
P
3
... P
N-1
P
N
X
X
X
...
X
X
H
L
L
L ...
L
L
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
CLOCK
DATA IN
STROBE
OUTPUT
ENABLE
OUTN
B
D
F
E
C
G
A
H
I
Timing Conditions
data as long as the STROBE is held high. Most applications
where the latching feature is not used (STROBE tied high)
require the OUTPUT ENABLE input to be high during serial
data entry.
Outputs are active (controlled by the latch state) when the
OUTPUT ENABLE is low. All Outputs are low (disabled) when
the OUTPUT ENABLE is high. OUTPUT ENABLE does not
affect the data in the shift register or latch.
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