General Description
The MAX9217 digital video parallel-to-serial converter
serializes 27 bits of parallel data into a serial data stream.
Eighteen bits of video data and 9 bits of control data are
encoded and multiplexed onto the serial interface, reduc-
ing the serial data rate. The data enable input determines
when the video or control data is serialized.
The MAX9217 pairs with the MAX9218 deserializer to
form a complete digital video serial link. Interconnect
can be controlled-impedance PC board traces or twisted-
pair cable. Proprietary data encoding reduces EMI and
provides DC balance. DC balance allows AC-coupling,
providing isolation between the transmitting and receiv-
ing ends of the interface. The LVDS output is internally
terminated with 100
.
ESD tolerance is specified for ISO 10605 with
10kV
contact discharge and
30kV air discharge.
The MAX9217 operates from a +3.3V core supply and
features a separate input supply for interfacing to 1.8V
to 3.3V logic levels. This device is available in 48-lead
Thin QFN and TQFP packages and is specified from
-40C to +85C.
Applications
Navigation System Display
In-Vehicle Entertainment System
Video Camera
LCD Displays
Features
o Proprietary Data Encoding for DC Balance and
Reduced EMI
o Control Data Sent During Video Blanking
o Five Control Data Inputs Are Single-Bit-Error
Tolerant
o Programmable Phase-Shifted LVDS Signaling
Reduces EMI
o Output Common-Mode Filter Reduces EMI
o Greater than 10m STP Cable Drive
o Wide 2% Reference Clock Tolerance
o ISO 10605 ESD Protection
o Separate Input Supply Allows Interface to 1.8V to
3.3V Logic
o +3.3V Core Supply
o Space-Saving Thin QFN and TQFP Packages
o -40C to +85C Operating Temperature
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
________________________________________________________________ Maxim Integrated Products
1
RNG0
RNG1
V
CCLVDS
OUT+
OUT-
LVDS GND
LVDS GND
CMF
PWRDWN
V
CCPLL
PLL GND
MOD1
GND
V
CCIN
RGB_IN10
RGB_IN11
RGB_IN12
RGB_IN13
RGB_IN14
RGB_IN15
RGB_IN16
RGB_IN17
CNTL_IN0
CNTL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
GND
V
CC
CNTL_IN2
CNTL_IN3
CNTL_IN4
CNTL_IN5
CNTL_IN6
CNTL_IN7
CNTL_IN8
DE_IN
PCLK_IN
MOD0
TQFP
MAX9217
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
RGB_IN9
RGB_IN8
RGB_IN7
RGB_IN6
RGB_IN5
RGB_IN4
RGB_IN3
RGB_IN2
RGB_IN1
RGB_IN0
V
CC
GND
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
MAX9217
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
RNG0
RNG1
V
CCLVDS
OUT+
OUT-
LVDS GND
LVDS GND
CMF
PWRDWN
V
CCPLL
PLL GND
MOD1
GND
V
CCIN
RGB_IN10
RGB_IN11
RGB_IN12
RGB_IN13
RGB_IN14
RGB_IN15
RGB_IN16
RGB_IN17
CNTL_IN0
CNTL_IN1
GND
V
CC
CNTL_IN2
CNTL_IN3
CNTL_IN4
CNTL_IN5
CNTL_IN6
CNTL_IN7
CNTL_IN8
DE_IN
PCLK_IN
MOD0
THIN QFN-EP
RGB_IN9
RGB_IN8
RGB_IN7
RGB_IN6
RGB_IN5
RGB_IN4
RGB_IN3
RGB_IN2
RGB_IN1
RGB_IN0
V
CC
GND
TOP VIEW
PART
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
MAX9217ECM
-40
C to +85C 48 TQFP
C48-5
MAX9217ETM
-40
C to +85C 48 Thin QFN-EP* T4866-1
Pin Configurations
Ordering Information
19-3558; Rev 2; 10/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
*EP = Exposed pad.
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, R
L
= 100
1%, PWRDWN = high, T
A
= -40C to +85C, unless otherwise noted. Typical values are at
V
CC_
= +3.3V, T
A
= +25C.) (Notes 1, 2)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC_
to _GND........................................................-0.5V to +4.0V
Any Ground to Any Ground...................................-0.5V to +0.5V
OUT+, OUT- to LVDS GND ...................................-0.5V to +4.0V
OUT+, OUT- Short Circuit to LVDS GND
or V
CCLVDS
.............................................................Continuous
OUT+, OUT- Short Through 0.125F (or smaller),
25V Series Capacitor..........................................-0.5V to +16V
RGB_IN[17:0], CNTL_IN[8:0], DE_IN,
RNG0, RNG1, MOD0, MOD1, PCLK_IN,
PWRDWN, CMF to GND......................-0.5V to (V
CCIN
+ 0.5V)
Continuous Power Dissipation (T
A
= +70C)
48-Lead TQFP (derate 20.8mW/C above +70C) ....1667mW
48-Lead Thin QFN (derate 37mW/C above +70C) .2963mW
ESD Protection
Human Body Model (R
D
= 1.5k
, CS = 100pF)
All Pins to GND.................................................................
2kV
ISO 10605 (R
D
= 2k
, C
S
= 330pF)
Contact Discharge (OUT+, OUT-) to GND.....................
10kV
Air Discharge (OUT+, OUT-) to GND.............................
30kV
Storage Temperature Range .............................-65C to +150C
Junction Temperature ......................................................+150C
Lead Temperature (soldering, 10s) .................................+300C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN,
PWRDWN, RNG_, MOD_)
V
CCIN
= 1.71V to <3V
0.65V
CCIN
V
CCIN
+ 0.3
High-Level Input Voltage
V
IH
2
V
CCIN
+ 0.3
V
V
CCIN
= 1.71V to <3V
-0.3
0.3V
CCIN
Low-Level Input Voltage
V
IL
-0.3
+0.8
V
Input Current
I
IN
V
IN
= -0.3V to (V
CCIN
+ 0.3V),
V
CCIN
= 1.71V to 3.6V,
PWRDWN = high or low
-70
+70
A
Input Clamp Voltage
V
CL
I
CL
= -18mA
-1.5
V
LVDS OUTPUTS (OUT+, OUT-)
Differential Output Voltage
V
OD
Figure 1
250
335
450
mV
Change in V
OD
Between
Complementary Output States
V
OD
Figure 1
20
mV
Common-Mode Voltage
V
OS
Figure 1
1.125
1.29
1.375
V
Change in V
OS
Between
Complementary Output States
V
OS
Figure 1
20
mV
Output Short-Circuit Current
I
OS
V
OUT+
or V
OUT-
= 0 or 3.6V
-15
8
+15
mA
Magnitude of Differential Output
Short-Circuit Current
I
OSD
V
OD
= 0
5.5
15
mA
OUT+ = 0,
OUT- = 3.6V
Output High-Impedance Current
I
OZ
PWRDWN = low
or
V
CC_
= 0
OUT+ = 3.6V,
OUT- = 0
-1
+1
A
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
_______________________________________________________________________________________
3
AC ELECTRICAL CHARACTERISTICS
(V
CC_
= +3.0V to +3.6V, R
L
= 100
1%, C
L
= 5pF, PWRDWN = high, T
A
= -40
C to +85C, unless otherwise noted. Typical values
are at V
CC_
= +3.3V, T
A
= +25
C.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PCLK_IN TIMING REQUIREMENTS
Clock Period
t
T
Figure 2
28.57
333.00
ns
Clock Frequency
f
CLK
3
35
MHz
Clock Frequency Difference from
Deserializer Reference Clock
f
CLK
-2
+2
%
Clock Duty Cycle
DC
t
HIGH
/t
T
or t
LOW
/t
T,
Figure 2
35
50
65
%
Clock Transition Time
t
R
, t
F
Figure 2
2.5
ns
SWITCHING CHARACTERISTICS
Output Rise Time
t
RISE
20% to 80%, V
OD
250mV,
modulation off, Figure 3
215
350
ps
Output Fall Time
t
FALL
80% to 20%, V
OD
250mV,
modulation off, Figure 3
206
350
ps
Input Setup Time
t
SET
Figure 4
3
ns
Input Hold Time
t
HOLD
Figure 4
3
ns
Serializer Delay
t
SD
Figure 5
3.15 x
t
T
3.2 x
t
T
ns
PLL Lock Time
t
LOCK
Figure 6
16385 x
t
T
ns
Power-Down Delay
t
PD
Figure 7
1
s
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, R
L
= 100
1%, PWRDWN = high, T
A
= -40C to +85C, unless otherwise noted. Typical values are at
V
CC_
= +3.3V, T
A
= +25C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Output Resistance
R
O
78
110
147
3MHz
15
25
5MHz
18
25
10MHz
23
28
20MHz
33
39
Worst-Case Supply Current
I
CCW
R
L
= 100
1%,
C
L
= 5pF,
continuous 10
transition words,
modulation off
35MHz
50
70
mA
Power-Down Supply Current
I
CCZ
(Note 3)
50
A
WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY
MAX9217 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
31
27
23
19
15
11
7
10
20
30
40
50
60
0
3
35
Typical Operating Characteristics
(T
A
= +25
C, V
CC_
= +3.3V, R
L
= 100
, modulation off, unless otherwise noted.)
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC_
= +3.0V to +3.6V, R
L
= 100
1%, C
L
= 5pF, PWRDWN = high, T
A
= -40
C to +85C, unless otherwise noted. Typical values
are at V
CC_
= +3.3V, T
A
= +25
C.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
700Mbps data rate,
CMF open, Figure 8
22
70
Peak-to-Peak Output Offset
Voltage
V
OSp-p
700Mbps data rate,
CMF 0.1F to ground, Figure 8
12
50
mV
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
OD
,
V
OD
, and
V
OS
.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +25C.
Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at
0.3V or V
CCIN
- 0.3V. PWRDWN is
0.3V.
Note 4: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at
6 sigma.
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
_______________________________________________________________________________________
5
Pin Description
PIN
NAME
FUNCTION
1, 13, 37
GND
Input Buffer Supply and Digital Supply Ground
2
V
CCIN
Input Buffer Supply Voltage. Bypass to GND with 0.1F and 0.001F capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
310,
3948
RGB_IN[17:0]
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
GND.
11, 12, 1521
CNTL_IN[8:0]
LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
when DE_IN is low. Internally pulled down to GND.
14, 38
V
CC
Digital Supply Voltage. Bypass to GND with 0.1F and 0.001F capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
22
DE_IN
LVTTL/LVCMOS Data Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low
selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to GND.
23
PCLK_IN
LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
reference clock. Internally pulled down to GND.
24
MOD0
LVTTL/LVCMOS Modulation Rate Input. Selects the phase-modulation step size. Internally pulled
down to GND.
25
MOD1
LVTTL/LVCMOS Modulation Rate Input. Selects the phase-modulation step size. Internally pulled
down to GND.
26
PLL GND
PLL Supply Ground
27
V
CCPLL
PLL Supply Voltage. Bypass to PLL GND with 0.1F and 0.001F capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.
28
PWRDWN
LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
29
CMF
Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter
common-mode switching noise.
30, 31
LVDS GND
LVDS Supply Ground
32
OUT-
Inverting LVDS Serial Data Output
33
OUT+
Noninverting LVDS Serial Data Output
34
V
CCLVDS
LVDS Supply Voltage. Bypass to LVDS GND with 0.1F and 0.001F capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
35
RNG1
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
36
RNG0
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
EP
GND
Exposed Pad (Thin QFN Package Only). Connect Thin QFN exposed pad to PC board GND.
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