General Description
The MAX5885 is an advanced, 16-bit, 200Msps digital-
to-analog converter (DAC) designed to meet the
demanding performance requirements of signal synthe-
sis applications found in wireless base stations and
other communications applications. Operating from a
single 3.3V supply, this DAC offers exceptional dyna-
mic performance such as 77dBc spurious-free dynamic
range (SFDR) at f
OUT
= 10MHz. The DAC supports
update rates of 200Msps at a power dissipation of less
than 200mW.
The MAX5885 utilizes a current-steering architecture,
which supports a full-scale output current range of 2mA
to 20mA, and allows a differential output voltage swing
between 0.1V
P-P
and 1V
P-P
.
The MAX5885 features an integrated 1.2V bandgap
reference and control amplifier to ensure high accuracy
and low noise performance. Additionally, a separate
reference input pin enables the user to apply an exter-
nal reference source for optimum flexibility and to
improve gain accuracy.
The digital and clock inputs of the MAX5885 are
designed for CMOS-compatible voltage levels. The
MAX5885 is available in a 48-pin QFN package with an
exposed paddle (EP) and is specified for the extended
industrial temperature range (-40C to +85C).
Refer to the MAX5883 and MAX5884 data sheets for
pin-compatible 12- and 14-bit versions of the MAX5885.
For LVDS high-speed versions, refer to the MAX5886/
MAX5887/MAX5888 data sheet.
Applications
Base Stations: Single/Multicarrier UMTS,
CDMA, GSM
Communications: LMDS, MMDS, Point-to-Point
Microwave
Digital Signal Synthesis
Automated Test Equipment (ATE)
Instrumentation
Features
200Msps Output Update Rate
Single 3.3V Supply Operation
Excellent SFDR and IMD Performance
SFDR = 77dBc at f
OUT
= 10MHz (to Nyquist)
IMD = -88dBc at f
OUT
= 10MHz
ACLR = 74dB at f
OUT
= 30.72MHz
2mA to 20mA Full-Scale Output Current
CMOS-Compatible Digital and Clock Inputs
On-Chip 1.2V Bandgap Reference
Low Power Dissipation
48-Pin QFN-EP Package
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
________________________________________________________________ Maxim Integrated Products
1
Ordering Information
19-2786; Rev 1; 12/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
PART
TEMP RANGE
PIN-PACKAGE
MAX5885EGM
-40
C to +85C
48 QFN-EP*
B12
B13
B15
DGND
N.C.
N.C.
N.C.
N.C.
N.C.
DV
DD
SEL0
B14
XOR
VCLK
CLKGND
CLKP
CLKN
CLKGND
VCLK
PD
AV
DD
AGND
B0
B1
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
AGND
IOUTN
IOUTP
AV
DD
AGND
AV
DD
AGND
N.C.
DACREF
FSADJ
REFIO
B3
B4
B5
B6
DV
DD
DGND
B7
B8
B9
B11
B10
B2
QFN
MAX5885
AGND
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
Pin Configuration
*EP = Exposed paddle.
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, R
L
= 50
, I
OUT
= 20mA,
f
CLK
= 200Msps, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
+25C guaranteed by production test, <+25C guaranteed by design
and characterization. Typical values are at T
A
= +25C.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
DD
, DV
DD
, VCLK to AGND................................-0.3V to +3.9V
AV
DD
, DV
DD
, VCLK to DGND ...............................-0.3V to +3.9V
AV
DD
, DV
DD
, VCLK to CLKGND ...........................-0.3V to +3.9V
AGND, CLKGND to DGND....................................-0.3V to +0.3V
DACREF, REFIO, FSADJ to AGND.............-0.3V to AV
DD
+ 0.3V
IOUTP, IOUTN to AGND................................-1V to AV
DD
+ 0.3V
CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V
B0B15, SEL0, PD, XOR to DGND.............-0.3V to DV
DD
+ 0.3V
Continuous Power Dissipation (T
A
= +70C)
48-Pin QFN (derate 27mW/C above +70C)............2162.2mW
Thermal Resistance (
JA
) ..............................................+37C/W
Operating Temperature Range ...........................-40C to +85C
Junction Temperature ......................................................+150C
Storage Temperature Range .............................-60C to +150C
Lead Temperature (soldering, 10s) .................................+300C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
16
Bits
Integral Nonlinearity
INL
Measured differentially
0.006
%FS
Differential Nonlinearity
DNL
Measured differentially
0.003
%FS
Offset Error
OS
-0.025
0.003 +0.025
%FS
Offset Drift
50
ppm/
C
Full-Scale Gain Error
GE
FS
External reference, T
A
+25C
-3.5
+1.3
%FS
Internal reference
100
Gain Drift
External reference
50
ppm/
C
Full-Scale Output Current
I
OUT
(Note 1)
2
20
mA
Min Output Voltage
Single ended
-0.5
V
Max Output Voltage
Single ended
1.1
V
Output Resistance
R
OUT
1
M
Output Capacitance
C
OUT
5
pF
DYNAMIC PERFORMANCE
Output Update Rate
f
CLK
1
200
Msps
f
CLK
= 100MHz
f
OUT
= 16MHz, -12dB FS
-155
Noise Spectral Density
f
CLK
= 200MHz
f
OUT
= 80MHz, -12dB FS
-148
dB FS/
Hz
f
OUT
= 1MHz, 0dB FS
88
f
OUT
= 1MHz, -6dB FS
83
Spurious-Free Dynamic Range to
Nyquist
SFDR
f
CLK
= 100MHz
f
OUT
= 1MHz, -12dB FS
80
dBc
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, R
L
= 50
, I
OUT
= 20mA,
f
CLK
= 200Msps, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
+25C guaranteed by production test, <+25C guaranteed by design
and characterization. Typical values are at T
A
= +25C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
OUT
= 10MHz, -12dB FS
77
f
CLK
= 100MHz
f
OUT
= 30MHz, -12dB FS
73
f
OUT
= 10MHz, -12dB FS
72
f
OUT
= 16MHz, -12dB FS,
T
A
+25C
68
76
f
OUT
= 30MHz, -12dB FS
71
Spurious-Free Dynamic Range to
Nyquist
SFDR
f
CLK
= 200MHz
f
OUT
= 50MHz, -12dB FS
71
dBc
f
OUT1
= 9MHz, -6dB FS
f
CLK
= 100MHz
f
OUT2
= 10MHz, -6dB FS
-88
f
OU T 1
= 29M H z, - 6d B FS
Two-Tone IMD
TTIMD
f
CLK
= 200MHz
f
OU T 2
= 30M H z, - 6d B FS
-74
dBc
Four-Tone IMD, 1MHz Frequency
Spacing, GSM Model
FTIMD
f
CLK
= 150MHz
f
OUT
= 31.99MHz,
-12dB FS
-82
dBc
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
WCDMA Model
ACLR
f
CLK
=
184.32MHz
f
OUT
= 30.72MHz
74
dB
Output Bandwidth
BW
-1dB
(Note 2)
450
MHz
REFERENCE
Internal Reference Voltage Range
V
REFIO
1.1
1.21
1.34
V
Reference Input Compliance
Range
V
REFIOCR
0.125
1.25
V
Reference Input Resistance
R
REFIO
10
k
Reference Voltage Drift
TCO
REF
50
ppm/
C
ANALOG OUTPUT TIMING
Output Fall Time
t
FALL
90% to 10% (Note 3)
375
ps
Output Rise Time
t
RISE
10% to 90% (Note 3)
375
ps
Output Voltage Settling Time
t
SETTLE
Output settles to 0.025% FS (Note 3)
11
ns
Output Propagation Delay
t
PD
(Note 3)
1.8
ns
Glitch Energy
1
pV-s
I
OUT
= 2mA
30
Output Noise
N
OUT
I
OUT
= 20mA
30
pA/
Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time
t
SETUP
Referenced to rising edge of clock (Note 4)
0.4
ns
Data to Clock Hold Time
t
HOLD
Referenced to rising edge of clock (Note 4)
1.25
ns
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
4
_______________________________________________________________________________________
Note 1: Nominal full-scale current I
OUT
= 32
I
REF
.
Note 2: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5885.
Note 3: Parameter measured single ended into a 50
termination resistor.
Note 4: Parameter guaranteed by design.
Note 5: Parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage.
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, R
L
= 50
, I
OUT
= 20mA,
f
CLK
= 200Msps, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
+25C guaranteed by production test, <+25C guaranteed by design
and characterization. Typical values are at T
A
= +25C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Data Latency
3.5
Clock
cycles
Minimum Clock Pulse Width High
t
CH
CLKP, CLKN
1.5
ns
Minimum Clock Pulse Width Low
t
CL
CLKP, CLKN
1.5
ns
CMOS LOGIC INPUTS (B0B15, PD, SEL0, XOR)
Input Logic High
V
IH
0.7 x
DV
DD
V
Input Logic Low
V
IL
0.3 x
DV
DD
V
Input Leakage Current
I
IN
-15
+15
A
Input Capacitance
C
IN
5
pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
1.5
Differential Input Voltage Swing
V
CLK
Square wave
0.5
V
P-P
Differential Input Slew Rate
SR
CLK
(Note 5)
>100
V/s
Common-Mode Voltage Range
V
COM
1.5
20%
V
Input Resistance
R
CLK
5
k
Input Capacitance
C
CLK
5
pF
POWER SUPPLIES
Analog Supply Voltage Range
AV
DD
3.135
3.3
3.465
V
Digital Supply Voltage Range
DV
DD
3.135
3.3
3.465
V
Clock Supply Voltage Range
V
CLK
3.135
3.3
3.465
V
f
CLK
= 100Msps, f
OUT
= 1MHz
27
Analog Supply Current
I
AVDD
Power-down
0.3
mA
f
CLK
= 100Msps, f
OUT
= 1MHz
8.5
mA
Digital Supply Current
I
DVDD
Power-down
10
A
f
CLK
= 100Msps, f
OUT
= 1MHz
5.5
mA
Clock Supply Current
I
VCLK
Power-down
10
A
f
CLK
= 100Msps, f
OUT
= 1MHz
135
Power Dissipation
P
DISS
Power-down
1
mW
Power-Supply Rejection Ratio
PSRR
AV
DD
= VCLK = DV
DD
= 3.3V
5% (Note 5)
-0.1
+0.1
%FS/V
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
_______________________________________________________________________________________
5
Typical Operating Characteristics
(AV
DD
= DV
DD
= VCLK = 3.3V, external reference, V
REFIO
= 1.25V, R
L
= 50
, I
OUT
= 20mA, T
A
= +25C, unless otherwise noted.)
0
30
20
10
40
50
60
70
80
90
100
0
10
5
15
20
25
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 50MHz)
MAX5885 toc01
f
OUT
(MHz)
SFDR (dBc)
-12dB FS
0dB FS
-6dB FS
0
30
20
10
40
50
60
70
80
90
100
0
20
10
30
40
50
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 100MHz)
MAX5885 toc02
f
OUT
(MHz)
SFDR (dBc)
-6dB FS
-12dB FS
0dB FS
0
30
20
10
40
50
60
70
80
90
100
0
30
15
45
60
75
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 150MHz)
MAX5885 toc03
f
OUT
(MHz)
SFDR (dBc)
-12dB FS
0dB FS
-6dB FS
0
30
20
10
40
50
60
70
80
90
100
0
40
10
80
90 100
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 200MHz)
MAX5885 toc04
f
OUT
(MHz)
SFDR (dBc)
20 30
70
60
50
-12dB FS
0dB FS
-6dB FS
-40
-60
-50
-80
-70
-90
-100
0
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 100MHz)
MAX5885 toc05
f
OUT
(MHz)
TWO-TONE IMD (dBc)
10
20
50
-12dB FS
-6dB FS
30
40
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
24
28
27
26
25
34
33
36
35
TWO-TONE INTERMODULATION DISTORTION
(f
CLK
= 100MHz)
MAX5885 toc06
f
OUT
(MHz)
OUTPUT POWER (dBm)
30
29
32
31
2 x f
T1
- f
T2
f
T1
f
T2
f
T1
= 28.9429MHz
f
T2
= 29.8706MHz
2 x f
T2
- f
T1
A
OUT
= -6dB FS
BW = 12MHz
0
20
40
60
80
100
SFDR vs. OUTPUT FREQUENCY
(f
CLK
= 200MHz, A
OUT
= -6dB FS)
MAX5885 toc08
f
OUT
(MHz)
SFDR (dBc)
0
40 50
10
20 30
80
60
70
90 100
I
OUT
= 5mA
I
OUT
= 10mA
I
OUT
= 20mA
-40
-50
-60
-80
-70
-90
-100
0
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 200MHz)
MAX5885 toc07
f
OUT
(MHz)
TWO-TONE IMD (dBc)
20
10
30
80
-12dB FS
-6dB FS
40
60
70
50
0
30
20
10
40
50
60
70
80
90
100
0
40
10
70 80
90 100
SFDR vs. f
OUT
AND TEMPERATURE
(f
CLK
= 200MHz, A
OUT
= -6dB FS, I
FS
= 20mA)
MAX5885 toc09
f
OUT
(MHz)
SFDR (dBc)
20 30
60
50
T
A
= -40
C
T
A
= +25
C
T
A
= +85
C
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