DEVICES INCORPORATED
Logic Products
1
LF7710 -
DragonFly
TM
High-Speed FFT Processor
Sep 13, 2001 LDS.7710-A
ADVANCED
INFORMATION
600 MHz Core Operation
1.8 Volt Power Supply
5-Volt Tolerant I/O
Computes up to a 8192 Point
Complex FFT in 26 s*, the fastest
single-chip 1K Complex FFT
compute time yet to date!
6 Programmable Complex FFT
Point Sizes: 16 Point (40 ns), 64
Point (200 ns), 256 Point (600 ns),
and 1024 Point (3.2 s), 4096 Point
(17 s), 8192 (26 s)* **
Standby Modes Result in Signifi-
cant Power Savings While Simulta-
neously Retaining Internal Memory
Data
Supports Both Forward and Inverse
Fast Fourier Transforms
Configurable as a FIR Filter with
up to 8192 Complex Taps
Device Contains Seven Built-In
Windowing Functions in ROM
Window Buffer (16K x 16-bit)
Enables Users to Program their
own Complex Window Functions
through Independent Address and
Data Input Lines
16-bit Fixed Point Data Precision
(96 dB Dynamic Range) on Output
with 20-bit Internal Computation
Precision
2.24 M-bit Internal RAM
2.4 M-bit Internal Window ROM
Package Styles Available:
- 144-pin Plastic Quad Flatpack
- 144-pin BGA
*
8192Complex FFT Computation time based on
XY Mode with 25% Input Overlap. 8192
Complex FFT with No Overlap and Averaged
Linear or Decibel Power is computed in 32 s.
**
All Computation times based on XY Mode with
25% Input Overlap.
FEATURES
DESCRIPTION
LF7710 -
DragonFly
TM
High-Speed FFT Processor
DEVICES INCORPORATED
LF7710 B
LOCK
D
IAGRAM
The LF7710 is a high-speed Fast
Fourier Transform Processor. The
LF7710 allows extremely fast FFT
computations to take place within a
single monolithic device. All data
buffering and working storage re-
quired for up to a 8192 point complex
FFT operation are on-chip. This
eliminates the need for expensive, high-
speed external memories, while
decreasing internal computation time.
The interface to the device appears to
the user as if it were a synchronous
SRAM with all appropriate signaling.
There are several programmable
options available on the device to
perform real FFT computations,
complex input data windowing,
forward/inverse transform, transform
overlap, and exponential averaging of
power output. Block floating point
precision is achieved with internal
scaling logic. Exact specified scaling is
also an option through the use of a
scaling register.
The core transform processor is
comprised of a "Dragonfly" processor
which computes 4-point complex
transforms in approximately 2 nsec
when the pipeline is fully loaded. It
consists of several multipliers and
adders in parallel to achieve this high,
sustained computation throughput
rate. Input data and twiddle factor
coefficients are presented to the
processor core every 2 nsec and
output is clocked out at the same rate
giving the processing performances
indicated.
High-Speed
FFT
Processor
16
11
DIN
15-0
WIN
15-0
AIN
10-0
CTM
OVC
1-0
TEN
WD
2-0
SZ
1-0
INV
DBO
AVG
SCTRL
CLK
PLL
1-0
3
2
2
HOLD
WRD/WWE
FILT
CB
XYMODE
STDBY
2
CE
RESET
CPINS
CACC
1-0
DOUT
15-0
EOT
16
ADOUT
10-0
11
OE
OVF
FF
EF
DRD/DWE
16
2
OCLK
ORD/OWE
ACOP
SCL
5-0
6
DEVICES INCORPORATED
LF7710 -
DragonFly
TM
High-Speed FFT Processor
2
Logic Products
Sep 13, 2001 LDS.7710-A
Some applications of the LF7710 in the
telecommunication field are: Wireless
Base Stations, Satellite Communica-
tions, Software Defined Radios, Cable
Modems and OFDM Applications;
while some sample instrumentation
applications are: Digital Spectrum
Analyzers, Modulation Analyzers,
and Distortion Analyzers.
SIGNAL DEFINITIONS
Power
Vcc and GND
+2.5 V power supply. All pins must
be connected.
Clock
CLK -- Master Clock
The rising edge of CLK strobes all
enabled registers and memory latches.
OCLK -- Output Clock
The rising edge of OCLK strobes the
output buffer memory and the follow-
ing flags: EF, OVF, EOT.
Inputs
DIN
15-0
-- Data Input
DIN
15-0
is the 16-bit registered data
input port. This input port is actually
bidirectional. Depending on the value
present on CACC
1-0
and DRD/DWE,
this port may act as an output port.
Data is latched on the rising edge of
CLK, provided DRD/DWE is held
LOW. The data format is two's
complement.
AIN
10-0
-- Data/Window Input Address
AIN
10-0
is the input address bus for
DIN
15-0
and WIN
15-0
and controlled
by CACC
1-0
. Refer to table 5.
WIN
15-0
-- Window Input
WIN
15-0
is the 16-bit registered data
input port. This input port is actually
bidirectional. Depending on the value
present on CACC
1-0
and WRD/WWE,
this port may act as an output port.
Data is latched on the rising edge of
CLK, provided WRD/WWE is held
LOW. The data format is two's
complement.
Outputs
DOUT
15-0
-- Data Output
DOUT
15-0
is the 16-bit registered data
output port. See Figure 3.
ADOUT
10-0
-- Data Output Address
ADOUT
10-0
provides address infor-
mation for DOUT
15-0
. This bus is
bidirectional. In Continuous Mode
(CTM=1), the LF7710 outputs data
output address information automati-
cally. However, should the user desire
to read out data from DOUT
15-0
in any
order, they may present addresses to
ADOUT
10-0
, provided they are in
F
IGURE
1.
I
NPUT
AND
W
INDOW
D
ATA
F
ORMATS
15 14 13
2
1
0
2
15
(Sign)
2
14
2
13
2
2
2
1
2
0
15 14 13
2
1
0
2
15
(Sign)
2
14
2
13
2
2
2
1
2
0
Input Data
Window Data
F
IGURE
2.
I
NPUT
AND
W
INDOW
A
DDRESS
F
ORMATS
10 9
8
2
1
0
2
10
2
9
2
8
2
2
2
1
2
0
10 9
8
2
1
0
2
10
2
9
2
8
2
2
2
1
2
0
Input Data Address
Window Data Address
F
IGURE
3.
D
ATA
O
UTPUT
F
ORMATS
15 14 13
2
1
0
2
15
(Sign)
2
14
2
13
2
2
2
1
2
0
15 14 13
2
1
0
2
15
(Sign)
2
14
2
13
2
2
2
1
2
0
Real/Imaginary Mode
XY Mode (Averaged)
14 13 12
2
1
0
2
14
2
13
2
12
2
2
2
1
2
0
14 13 12
2
1
0
2
14
2
13
2
12
2
2
2
1
2
0
Linear Power Mode
Averaged Linear Power Mode
15 14 13
2
1
0
-2
15
(Sign)
2
14
2
13
2
2
2
1
2
0
15 14 13
2
1
0
-2
15
(Sign)
2
14
2
13
2
2
2
1
2
0
Decibel Mode
Averaged Decibel Mode
DEVICES INCORPORATED
Logic Products
3
LF7710 -
DragonFly
TM
High-Speed FFT Processor
Sep 13, 2001 LDS.7710-A
STDBY
HOLD
Operation
0
0
Normal Operation
0
1
Output Buffer Held
1
0
Soft Standby
1
1
Hard Stanby
Non-Continuous Mode (CTM=0).
EOT -- End of Transform
The EOT signal goes HIGH when the
transform has completed and goes
LOW again when either a new TEN is
pulsed in Non-Continuous Mode or
the window stage of the next transform
is completed in Continuous Mode.
OVF -- Overflow Flag
When OVF goes HIGH, this is indicative
of an internal data overflow. Note:
OVF will not go HIGH if SCALE has
been set to the default mode, all zeros.
In this mode, the device performs
block floating point which acts as an
automatic internal scale to prevent
overflow. If SCALE is set to any value
other than 0, the user should be
monitor OVF.
FF -- Full Flag
FF will go LOW indicating to the user
that the data input buffer is full. FF
will be asserted at all other times. FF
will automatically become asserted
upon system reset.
EF -- Empty Flag
EF will go LOW indicating to the user
that the data output buffer is empty.
EF will be asserted at all other times.
EF will automatically become
deasserted upon system reset.
Controls
CTM -- Continuous Transform Mode
When CTM is LOW, Non-Continuous
Transform operation is possible.
When TEN is pulsed LOW, the
transform starts (or restarts if the
previous transform was in mid-
computation). When CTM is HIGH,
Continuous Transform Mode is
enabled, which places the device in
synchronous operation. While in
Continuous Transform Mode, the part
acts like a "Data Pump." Data MUST
be made available on the input buffers
when expected and likewise, output
will be shifted out in a FIFO-like
WD
2-0
Configuration
0 0 0
Rectangular Window
0 0 1
Bartlett
0 1 0
Hamming
0 1 1
Hanning
1 0 0
Trapezoidl
1 0 1
Blackman-Harris
1 1 0
Welch
1 1 1
Buffer
T
ABLE
2.
W
INDOW
M
ODE
PLL
1-0
Bus Options
0 0
x1
0 1
x2
1 0
x3
1 1
x4
T
ABLE
3.
PLL M
ODE
OVC
1-0
Configuration
0 0
No Overlap
0 1
25 %
1 0
50%
1 1
75%
T
ABLE
1.
O
VERLAP
M
ODE
CACC
1-0
Active Loading Location
Active Corresponding Data Bus
0 0
Control Register
WIN
15-0
0 1
Window RAM
WIN
15-0
1 0
Data Input RAM
DIN
15-0
1 1
Data Input & Window RAM
DIN
15-0
& WIN
15-0
T
ABLE
5. A
DDRESS
L
INE
C
ONTROL
(CTM = 0 & CB =0)
SZ
2-0
Complex Transform Length
0 0 0
16
0 0 1
64
0 1 0
256
0 1 1
1024
1 0 0
4096
1 0 1
8192
T
ABLE
4. L
ENGTH
C
ONTROL
CACC
1-0
Active Loading Location
Active Corresponding Data Bus
0 0
Control Register
WIN
15-0
0 1
Window RAM
WIN
15-0
1 0
N/A
N/A
1 1
Window RAM
WIN
15-0
T
ABLE
6. A
DDRESS
L
INE
C
ONTROL
(CTM = 1 & CB=0)
CACC
1-0
Location to be Cleared
0 0
Control Register
0 1
Window RAM
1 0
Input RAM
1 1
Output RAM
T
ABLE
7. B
UFFER
R
ESET
(CB=1)
T
ABLE
8. S
TANDBY
M
ODES
DEVICES INCORPORATED
LF7710 -
DragonFly
TM
High-Speed FFT Processor
4
Logic Products
Sep 13, 2001 LDS.7710-A
HOLD -- Hold Output Buffer Data
Holds output buffer contents steady
while HOLD is held HIGH. When
HOLD is held LOW, the output buffer
allows data to be changed. When the
device is in Standby Mode, the data in
all the buffers is static, regardless of
the status of HOLD. If HOLD and
STDBY are HIGH, the device is in a
"hard stanbdy mode". Refer to table 8
for standby modes.
SCTRL -- Scale Control
When SCTRL is LOW, scaling is
automatically handled internally
through block floating point. When
SCTRL is HIGH, scaling is achieved
through the scaling registers and is
under user control.
T
ABLE
8. V
ALID
C
OMBINATIONS
OF
O
VERLAP
M
ODES
(OVC
1-0
)
AND
PLL M
ODES
(PLL
1-0
)
FOR
CTM=1
Full Complex Transform
Real Transform
Imaginary Transform
OVC
1-0
PLL
1-0
Mode x1
OVC
1-0
PLL
1-0
Mode x1
OVC
1-0
PLL
1-0
Mode x1
00
Valid Operation
00
Valid Operation
00
Valid Operation
01
Valid Operation
01
Valid Operation
01
Valid Operation
10
Valid Operation
10
Valid Operation
10
Valid Operation
11
Valid Operation
11
Valid Operation
11
Valid Operation
OVC
1-0
PLL
1-0
Mode x2
OVC
1-0
PLL
1-0
Mode x2
OVC
1-0
PLL
1-0
Mode x2
00
Data Starvation
00
Valid Operation
00
Valid Operation
01
Data Starvation
01
Valid Operation
01
Valid Operation
10
Valid Operation
10
Valid Operation
10
Valid Operation
11
Valid Operation
11
Valid Operation
11
Valid Operation
OVC
1-0
PLL
1-0
Mode x3
OVC
1-0
PLL
1-0
Mode x3
OVC
1-0
PLL
1-0
Mode x3
00
Data Starvation
00
Data Starvation
00
Data Starvation
01
Data Starvation
01
Data Starvation
01
Data Starvation
10
Data Starvation
10
Valid Operation
10
Valid Operation
11
Valid Operation
11
Valid Operation
11
Valid Operation
OVC
1-0
PLL
1-0
Mode x4
OVC
1-0
PLL
1-0
Mode x4
OVC
1-0
PLL
1-0
Mode x4
00
Data Starvation
00
Data Starvation
00
Data Starvation
01
Data Starvation
01
Data Starvation
01
Data Starvation
10
Data Starvation
10
Valid Operation
10
Valid Operation
11
Valid Operation
11
Valid Operation
11
Valid Operation
autonomous fashion. Note: In either
mode, the user should follow the
recommended combinations of
Overlap Modes (OVC
1-0
) and PLL
Modes (PLL
1-0
) in order to avoid
unexpected data on the output. See
Table 8.
TEN -- Transform Enable Control
When the device is in Continous
Transform Mode (CTM=1), TEN
should be held LOW. When the device
is in Non-Continuous Mode (CTM=0),
TEN can be pulsed LOW to start a
transform. Should TEN be pulsed
LOW in the middle of a transform
computation, the transform will restart.
DBO -- Linear Power/dB Output
When DBO is HIGH, dB Output
format is selected. When DBO is
LOW, Linear Power format is selected.
See Table 9.
XYMODE -- XY Mode
When XYMODE is HIGH, the device
is in XY Mode. The output mode can
be either Real/Imaginary or XY Mode
(Averaged), depending on the value
of AVG. If XYMODE is LOW the
device is in Power Mode. The output
can be in one of the following modes:
Linear Power, Decibel, Averaged
Linear Power, and Averaged Decibel
Power.
DEVICES INCORPORATED
Logic Products
5
LF7710 -
DragonFly
TM
High-Speed FFT Processor
Sep 13, 2001 LDS.7710-A
INV -- Forward/Inverse Transform Control
When INV is LOW, Forward Transform
is selected. When INV is HIGH, Inverse
Transform is selected. This signal is
internally automatically controlled
when the device is in Filter Mode.
SZ
1-0
-- Complex Transform Length
SZ
1-0
is the 2-bit Transform Length
selector and is selected from the four
predefined configurations. See Table 4.
OVC
1-0
-- Overlap Control
OVC
1-0
is the 2-bit Overlap Control
which determines the type of overlap
used and is selected from the four
predefined configurations. See Table 1.
PLL
1-0
-- PLL Mode
PLL
1-0
is the 2-bit PLL mode selector
and is selected from the four pre-
defined configurations. See Table 3.
CACC
1-0
determines the active buffer
loading location (i.e. Control Register,
Window RAM and/or Data Input
RAM) depending on the value of
CTM. It also determines the buffer
location to be cleared depending on
the value of CB. For instance, in order
for the user to read the Control
Register 1, CACC
1-0
should be set to
AVG -- Average Real and Imaginary
When AVG is enabled, Exponential
Window Averaging on Power is
performed. See Table 9.
FILT -- FFT/FIR Operation Mode
When FILT is held LOW, the device is
in FFT Mode. When FILT is held
HIGH, the device is in FIR Mode.
WD
2-0
-- Window Configuration
WD
2-0
is the 3-bit Window Configuration
mode select which determines the type
of Window used and is selected from
the seven predefined configurations
stored in the Window Configuration
ROM or user-definable Window RAM.
See Table 2.
00. The value 001h would then be
loaded through AIN
10-0
. Data from
Control Register 1 would then be
made available at WIN
15-0
. Refer to
Tables 5-7 for CACC
1-0
mapping. See
Figure 4 for the Control Register Map.
See Figures 5 and 6 for Control
Register 0 and 1 Internal Mapping.
CPINS -- Control Pins
CPINS changes control from the
external control pins to the control
registers. If CPINS is HIGH, control
of the device is determined by the
external control pins. If CPINS is LOW,
control of the device is determined by
the internal control registers.
OE -- Output Enable
Data is available on the output port
(DOUT
15-0
) on the falling edge of CLK
while OE is held LOW. When OE is
HIGH, DOUT
15-0
is placed in a high-
impedance state. CLKOUT is not
affected by OE.
DRD/DWE -- Data Read/Write Enable
If DRD/DWE is held LOW while CE
is held LOW, data on DIN
15-0
is written
to the corresponding location associ-
ated with CACC
1-0
on the rising edge
of CLK. If DRD/DWE is HIGH while
F
IGURE
4. C
ONTROL
R
EGISTER
M
AP
(CACC
1-0
=00)
CR
0
CR
1
SCALE
ALPHA
000h
7FFh
15
0
XX
XX
XX
XX
001h
002h
003h
004h
F
IGURE
5. C
ONTROL
R
EGISTER
0 M
APPING
F
IGURE
6. C
ONTROL
R
EGISTER
1 M
APPING
2
1
0
SZ
0
SZ
1
SZ
2
0
0
OVC
1
3
4
5
6
7
PLL
0
PLL
1
8
9
10
11
0
12
13
0
0
0
14
15
RESERVED BITS: 15 - 10, 7, 6, 3,
ALL BITS ARE READ/WRITABLE
OVC
0
0
0
0
2
1
0
CTM
TEN
INV
EOT
DBO
XYMODE
3
4
5
6
AVG
7
HOLD
SCTRL
8
9
10
11
OVF
12
13
FILT
0
0
14
15
RESERVED BITS: 15, 14
EOT AND OVF ARE READ-ONLY BITS, THE REST ARE READ-WRITEABLE
WD
0
WD
2
WD
1
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