LTC1668

16-Bit, 50Msps DAC

February 2000

50Msps Update Rate

16-Bit Resolution

High Spectral Purity: 87dB SFDR at 1MHz f

OUT

Differential Current Outputs

30ns Settling Time

5pV-s Glitch Impulse

Low Power: 180mW from

5V Supplies

TTL/CMOS (3.3V or 5V) Inputs

Small Package: 28-Pin SSOP

The LTC

1668 is a 16-bit, 50Msps differential current

output DAC implemented on a high performance BiCMOS
process with laser trimmed, thin-film resistors. The com-
bination of a novel current-steering architecture and a
high performance process produces a DAC with excep-
tional AC and DC performance. This is the first 16-bit DAC
in the marketplace to exhibit an SFDR (spurious free
dynamic range) of 87dB for an output signal frequency of
1MHz.

Operating from

5V supplies, the LTC1668 can be con-

figured to provide full-scale output currents up to 10mA.
The differential current outputs of the DAC allow single-
ended or true differential operation. The 1V to 1V output
compliance of the LTC1668 allows the outputs to be con-
nected directly to external resistors to produce a differ-
ential output voltage without degrading the converter's
linearity. Alternatively, the outputs can be connected to the
summing junction of a high speed operational amplifier,
or to a transformer.

The LTC1668 is available in a 28-pin SSOP and is fully
specified over the industrial temperature range.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Cellular Base Stations

Multicarrier Base Stations

Wireless Communication

Direct Digital Synthesis (DDS)

xDSL Modems

Arbitrary Waveform Generation

Automated Test Equipment

Instrumentation

16-Bit, 50Msps DAC

Final Electrical Specifications

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

16-BIT

HIGH SPEED

DAC

2.5V

REFERENCE

CLOCK

INPUT

16-BIT DATA

INPUT

LADCOM

AGND DGND

CLK

DB15

DB0

1668 TA01

OUT A

0.1

LTC1668

52.3

REFIN

REFOUT

COMP1

COMP2

0.1

SET

OUT B

52.3

OUT

P-P

DIFFERENTIAL

0.1

FREQUENCY (1.25MHz/DIV)

0.05

SIGNAL AMPLITUDE (dBm)

1668 G01

105

6.3

12.55

CLOCK

= 25Msps

OUT

= 1.007MHz

AMPLITUDE = 0dBFS
= 8.5dBm
SFDR = 86dBc

Single Tone SFDR

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

LTC1668

LTC1668CG
LTC1668IG

JMAX

= 110

= 100

C/W

ORDER PART

NUMBER

Consult factory for Military grade parts.

TOP VIEW

G PACKAGE

28-LEAD PLASTIC SSOP

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0 (LSB)

DB14

DB15 (MSB)

CLK

DGND

COMP2

COMP1

OUT A

OUT B

LADCOM

AGND

REFIN

REFOUT

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 5V, V

= 5V, LADCOM = AGND = DGND = 0V, I

OUTFS

= 10mA.

(Note 1)

Supply Voltage (V

) ................................................ 6V

Negative Supply Voltage (V

) ............................... 6V

Total Supply Voltage (V

to V

) .......................... 12V

Digital Input Voltage .................... 0.3V to (V

+ 0.3V)

Analog Output Voltage

OUT A

and I

OUT B

) ........ (V

0.3V) to (V

+ 0.3V)

Power Dissipation ............................................. 500mW
Operating Temperature Range

LTC1668C .............................................. 0

C to 70

LTC1668I ........................................... 40

C to 85

Storage Temperature Range ................ 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DC Accuracy (Measured at I

OUTA

, Driving a Virtual Ground)

Resolution

Bits

Monotonicity

Bits

INL

Integral Nonlinearity

LSB

DNL

Differential Nonlinearity

LSB

Offset Error

0.1

0.2

% FSR

Offset Error Drift

ppm/

Gain Error

Internal Reference, R

IREFIN

= 2k

% FSR

External Reference, V

REF

= 2.5V, R

IREFIN

= 2k

% FSR

Gain Error Drift

Internal Reference

ppm/

External Reference

ppm/

PSRR

Power Supply Rejection Ratio

= 5V

0.1

% FSR/V

= 5V

0.1

% FSR/V

Analog Output

OUTFS

Full-Scale Output Current

Output Compliance Range

= 10mA

Output Resistance; R

IOUTA

, R

IOUTB

OUTA, B

to LADCOM

0.7

1.1

1.5

Output Capacitance

Reference Output

Reference Voltage

REFOUT Tied to I

REFIN

Through 2k

2.475

2.5

2.525

Reference Output Drift

ppm/

Reference Output Load Regulation

LOAD

= 0mA to 5mA

mV/mA

PACKAGE/ORDER I FOR ATIO

ABSOLUTE AXI U RATI GS

ELECTRICAL CHARACTERISTICS

LTC1668

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 5V, V

= 5V, LADCOM = AGND = DGND = 0V, I

OUTFS

= 10mA.

Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Reference Input

Reference Small-Signal Bandwidth

= 10mA, C

COMP1

= 0.1

kHz

Power Supply

Positive Supply Voltage

4.75

5.25

Negative Supply Voltage

4.75

5.25

Positive Supply Current

= 10mA, f

CLK

= 25Msps, f

OUT

= 1MHz

Negative Supply Current

= 10mA, f

CLK

= 25Msps, f

OUT

= 1MHz

DIS

Power Dissipation

= 10mA, f

CLK

= 25Msps, f

OUT

= 1MHz

180

= 1mA, f

CLK

= 25Msps, f

OUT

= 1MHz

Dynamic Performance (Differential Transformer Coupled Output, 50

Double Terminated, Unless Otherwise Noted)

CLOCK

Maximum Update Rate

Msps

Output Settling Time

To 0.1% FSR

Output Propagation Delay

Glitch Impulse

Single Ended

pV-s

Differential

pV-s

Output Rise Time

Output Fall Time

Output Noise

= 10mA

pA/

= 1mA

pA/

AC Linearity

SFDR

Spurious Free Dynamic Range

CLK

= 25Msps, f

OUT

= 1MHz

to Nyquist

0dB FS Output

6dB FS Output

12dB FS Output

18dB FS Output

CLK

= 50Msps, f

OUT

= 1MHz

CLK

= 50Msps, f

OUT

= 2.5MHz

CLK

= 50Msps, f

OUT

= 5MHz

CLK

= 50Msps, f

OUT

= 20MHz

Spurious Free Dynamic Range

CLK

= 25Msps, f

OUT

= 1MHz, 2MHz Span

Within a Window

CLK

= 50Msps, f

OUT

= 5MHz, 4MHz Span

THD

Total Harmonic Distortion

CLK

= 25Msps, f

OUT

= 1MHz

CLK

= 50Msps, f

OUT

= 5MHz

Digital Inputs

Digital High Input Voltage

2.4

Digital Low Input Voltage

0.8

Digital Input Current

Digital Input Capacitance

Input Setup Time

Input Hold Time

CLKH

Clock High Time

CLKL

Clock Low Time

LTC1668

TYPICAL PERFOR A CE CHARACTERISTICS

FREQUENCY (1.25MHz/DIV)

0.05

SIGNAL AMPLITUDE (dBm)

1668 G01

105

6.3

12.55

CLOCK

= 25Msps

OUT

= 1.007MHz

AMPLITUDE = 0dBFS
= 8.5dBm
SFDR = 86dBc

Single Tone SFDR

2-Tone SFDR

FREQUENCY (0.2MHz/DIV)

3.2

SIGNAL AMPLITUDE (dBm)

1668 G02

100

110

4.2

5.2

CLOCK

= 50Msps

OUT1

4.028MHz
f

OUT2

4.419MHz
AMPLITUDE 1, 2
= 6dBFS
= 14.5dBm
SFDR > 77dBc

Integral Nonlinearity

Differential Nonlinearity

DIGITAL INPUT CODE

INTEGRAL NONLINEARITY (LSB)

16384

32768

1668 G03

49152

65535

DIGITAL INPUT CODE

DIFFERENTIAL NONLINEARITY (LSB)

1.0

65535

1668 G04

1.0

2.0

16384

32768

49152

2.0

0.5

1.5

PI FU CTIO S

REFOUT (Pin 15): Internal Reference Voltage Output.
Nominal value is 2.5V. Requires a 0.1

F bypass capacitor

to AGND.

REFIN

(Pin 16): Reference Input Current. Nominal value is

1.25mA for I

= 10mA. I

= I

REFIN

· 8.

AGND (Pin 17): Analog Ground.

LADCOM (Pin 18): Attenuator Ladder Common. Normally
tied to GND.

OUT B

(Pin 19): Complementary DAC Output Current. Full-

scale output current occurs when all data bits are 0s.

OUT A

(Pin 20): DAC Output Current. Full-scale output

current occurs when all data bits are 1s.

COMP1 (Pin 21): Current Source Control Amplifier Com-
pensation. Bypass to V

with 0.1

COMP2 (Pin 22): Internal Bypass Point. Bypass to V

with 0.1

(Pin 23): Negative Supply Voltage. Nominal value is

5V.

DGND (Pin 24): Digital Ground.

(Pin 25): Positive Supply Voltage. Nominal value is 5V.

CLK (Pin 26): Clock Input. Data is latched and the output
is updated on positive edge of clock.

DB15 to DB0 (Pins 27, 28, 1 to 14): Digital Input Data Bits.

LTC1668

APPLICATIO S I FOR ATIO

Theory of Operation

The LTC1668 is a high speed current steering 16-Bit DAC
made on an advanced BiCMOS process. Precision thin
film resistors and well matched bipolar transistors result
in excellent DC linearity and stability. A low glitch current
switching design gives excellent AC performance at sample
rates up to 50Msps. The device is complete with a 2.5V
internal bandgap reference and edge triggered latches,
and sets a new standard for DAC applications requiring
very high dynamic range at output frequencies up to
several megahertz.

Referring to the Block Diagram, the DAC contains an array
of current sources that are steered to I

OUTA

or I

OUTB

with

NMOS differential current switches. The four most signifi-
cant bits, DB15 to DB12 are made up of 15 current
segments of equal weight. The lower bits, DB11 to DB0 are
binary weighted, using a combination of current scaling
and a differential resistive attenuator ladder. All bits and
segments are precisely matched, both in current weight
for DC linearity, and in switch timing for low glitch impulse
and low spurious tone AC performance.

Setting the Full-Scale Current, I

OUTFS

The full-scale DAC output current, I

OUTFS

, is nominally

10mA, and can be adjusted down to 1mA. Placing a
resistor, R

SET

, between the REFOUT pin, and the I

REFIN

sets I

OUTFS

as follows.

The internal reference control loop amplifier maintains a
virtual ground at I

REFIN

by servoing the internal current

source, I

INT

, to sink the exact current flowing into I

REFIN

INT

is a scaled replica of the DAC current sources and

OUTFS

= 8 · (I

INT

), therefore:

OUTFS

= 8 · (I

REFIN

) = 8 · (V

REF

SET

)

(1)

For example, if R

SET

= 2k and is tied to V

REF

= REFOUT =

2.5V, I

REFIN

= 2.5/2k = 1.25mA and I

OUTFS

= 8 · (1.25mA)

= 10mA.

The reference control loop requires a capacitor on the
COMP1 pin for compensation. For optimal AC perfor-
mance, C

COMP1

should be connected to V

and be placed

very close to the package (less than 0.1").

For fixed reference voltage applications, C

COMP1

should

be 0.1

F or more. The reference control loop small-signal

bandwidth is approximately 1/(2

) · C

COMP1

· 80 or 20kHz

for C

COMP1

= 0.1

Internal Reference Output--REFOUT

The onboard 2.5V bandgap voltage reference drives the
REFOUT pin. It is trimmed and specified to drive a 2k
resistor tied from REFOUT to I

REFIN

, corresponding to a

1.25mA load (I

OUTFS

= 10mA). REFOUT has nominal

output impedance of 6

, or 0.24% per mA, so it must be

buffered to drive any additional external load. A 0.1

capacitor is required on the REFOUT pin for compensa-
tion. Note that this capacitor is required for stability, even
if the internal reference is not being used.

DAC Transfer Function

The LTC1668 uses straight binary digital coding. The
complementary current outputs, I

OUT A

and I

OUT B

, sink

current from 0 to I

OUTFS

. For I

OUTFS

= 10mA (nominal),

OUT A

swings from 0mA when all bits are low (i.e., Code =

0) to 10mA when all bits are high (i.e., Code = 65535) (deci-
mal representation). I

OUT B

is complementary to I

OUT A

and I

OUT B

are given by the following formulas:

OUT A

= I

OUTFS

· (DAC Code/65536)

(2)

OUT B

= I

OUTFS

· (65535-DAC Code)/65536

(3)

In typical applications, the LTC1668 differential output
currents either drive a resistive load directly or drive an
equivalent resistive load through a transformer, or as the
feedback resistor of an I-to-V converter. The voltage
outputs generated by the I

OUT A

and I

OUT B

output currents

are then:

OUT A

= I

OUT A

· R

LOAD

(4)

OUT B

= I

OUT B

· R

LOAD

(5)

The differential voltage is:

DIFF

= V

OUT A

OUT B

(6)

= (I

OUT A

OUT B

) · (R

LOAD

)

LTC1668

APPLICATIO S I FOR ATIO

Substituting the values found earlier for I

OUT A

, I

OUT B

and

OUTFS

DIFF

= {2 · DAC Code 65535)/65536} · 8 ·

LOAD

SET

) · (V

REF

)

(7)

From these equations some of the advantages of differen-
tial mode operation can be seen. First, any common mode
noise or error on I

OUT A

and I

OUT B

is cancelled. Second, the

signal power is twice as large as in the single-ended case.
Third, any errors and noise that multiply times I

OUT A

and

OUT B

, such as reference or I

OUTFS

noise, cancel near

midscale, where AC signal waveforms tend to spend the
most time. Fourth, this transfer function is bipolar; e.g. the
output swings positive and negative around a zero output
at mid-scale input, which is more convenient for AC
applications.

Note that the term (R

LOAD

SET

) appears in both the

differential and single-ended transfer functions. This means
that the Gain Error of the DAC depends on the ratio of
R

LOAD

to R

SET

, and the Gain Error tempco is affected by the

temperature tracking of R

LOAD

with R

SET

. Note also that

the absolute tempco of R

LOAD

is very critical for DC

nonlinearity. As the DAC output changes from 0mA to
10mA the R

LOAD

resistor will heat up slightly, and even a

very low tempco can produce enough INL bowing to be
significant at the 16-bit level. This effect disappears with
medium to high frequency AC signals due to the slow
thermal time constant of the load resistor.

Analog Outputs

The LTC1668 has two complementary current outputs,
I

OUT A

and I

OUT B

(see DAC Transfer Function). The output

impedance of I

OUT A

and I

OUT B

IOUT A

and R

IOUT B

) is

typically 1.1k

to LADCOM. (See the Equivalent Analog

Output Circuit, Figure 1.) The LADCOM pin is the com-
mon connection for the internal DAC attenuator ladder. It
usually is tied to analog ground, but more generally it
should connect to the same potential as the lead resistors
on I

OUT A

and I

OUT B

. The LADCOM pin carries a constant

current to V

of approximately 0.32 · (I

OUTFS

), plus any

current that flows from I

OUT A

and I

OUT B

through the

IOUT A

and R

IOUT B

resistors.

The specified output compliance voltage range is

1V. The

DC linearity specifications, INL and DNL, are trimmed and
guaranteed on I

OUT A

into the virtual ground of an

I-to-V converter, but are typically very good over the full
output compliance range. Above 1V the output current will
start to increase as the DAC current steering switch
impedance decreases, degrading both DC and AC linear-
ity. Below 1V, the DAC switches will start to approach the
transition from saturation to linear region. This will de-
grade AC performance first, due to nonlinear capacitance
and increased glitch impulse. AC distortion performance
is optimal at amplitudes less than

0.5V

P-P

on I

OUT A

and

OUT B

due to nonlinear capacitance and other large-signal

effects. At first glance, it may seem counter-intuitive to
decrease the signal amplitude when trying to optimize
SFDR. However, the error sources that affect AC perfor-
mance generally behave as additive currents, so decreas-
ing the load impedance to reduce signal voltage amplitude
will reduce most spurious signals by the same amount.

The LTC1668 is specified to operate with full-scale output
current, I

OUTFS

, from the nominal 10mA down to 1mA.

This can be useful to reduce power dissipation or to adjust
full-scale value. However, that the LTC1668 DC and AC
accuracy is specified only at I

OUTFS

= 10mA, and DC and

AC accuracy will fall off significantly at lower I

OUTFS

values.

At I

OUTFS

= 1mA, INL and DNL typically degrade to the 14-

bit to 13-bit level, compared to 16-bit to 15-bit typical
accuracy at 10mA I

OUTFS

. Increasing I

OUTFS

from 1mA, the

IOUT B

1.1k

5pF

LTC1668

5pF

1668 F01

IOUT A

1.1k

LADCOM

OUT A

OUT B

52.3

Figure 1. Equivalent Analog Output Circuit

LTC1668

APPLICATIO S I FOR ATIO

accuracy improves rapidly, roughly in proportion to
1/I

OUTFS

. The AC performance tends to be less affected by

reducing I

OUTFS

, except for the unavoidable affects on

SFDR and THD due to increased INL and DNL.

Output Configurations

Based on the specific application requirements, the
LTC1668 allows a choice of the best of several output
configurations. Voltage outputs can be generated by ex-
ternal load resistors, transformer coupling or with an op
amp I-to-V converter. Single-ended DAC output configu-
rations use only one of the outputs, preferably I

OUT A

, to

produce a single-ended voltage output. Differential mode
configurations use the difference between I

OUT A

and

OUT B

to generate an output voltage, V

DIFF

, as shown in

equation 7. Differential mode gives much better accuracy
in most AC applications. Because the DAC chip is the point
of interface between the digital input signals and the
analog output, some small amount of noise coupling to
I

OUT A

and I

OUT B

is unavoidable. Most of that digital noise

is common mode and is canceled by the differential mode
circuit. Other significant digital noise components can be
modeled as V

REF

or I

OUTFS

noise. In single-ended mode,

OUTFS

noise is gone at zero scale and is fully present at full

scale. In differential mode, I

OUTFS

noise is cancelled at

midscale input, corresponding to zero analog output.
Many AC signals, including broadband and multitone
communications signals with high peak to average ratios,
stay mostly near midscale.

Differential transformer-coupled output configurations
usually give the best AC performance. An example is the
AC Characterization Setup circuit, Figure 2. The advan-
tages of transformer coupling include excellent rejection
of common mode distortion and noise over a broad
frequency range and convenient differential-to-single-
ended conversion with isolation or level shifting. Also, as
much as twice the power can be delivered to the load, and
impedance matching can be accomplished by selecting
the appropriate transformer turns ratio. The center tap on
the primary side of the transformer is tied to ground to
provide the DC current path for I

OUT A

and I

OUT B

. For low

distortion, the DC average of the I

OUT A

and I

OUT B

currents

must be exactly equal to avoid biasing the core. This is
especially important for compact RF transformers with
small cores. The circuit in Figure 2 uses a Mini-Circuits
T1-1T RF transformer with a 1:1 turns ratio. The load

16-BIT

HIGH SPEED

DAC

HP1663EA

LOGIC ANALYZER WITH

PATTERN GENERATOR

2.5V

REFERENCE

LADCOM

AGND DGND

CLK

DB15

DB0

DIGITAL
DATA

CLK
IN

1668 F02

OUT A

0.1

LTC1668

REFIN

REFOUT

COMP1

COMP2

0.1

OUT 1 OUT 2

0.1

SET

OUT B

HP8110A DUAL

PULSE GENERATOR

LOW JITTER

CLOCK SOURCE

CLK
IN

0.1

TO HP3589A
SPECTRUM
ANALYZER
50

INPUT

110

MINI-CIRCUITS

T11T

Figure 2. AC Characterization Setup

LTC1668

APPLICATIO S I FOR ATIO

resistance on I

OUT A

and I

OUT B

is equivalent to a single

differential resistor of 50

, and the 1:1 turns ratio means

the output impedance from the transformer is 50

. Note

that the load resistors are optional, and they dissipate half
of the output power. However, in lab environments or
when driving long transmission lines it is very desirable to
have a 50

output impedance. This could also be done

with a 50

resistor at the transformer secondary, but

putting the load resistors on I

OUT A

and I

OUT B

is preferred

since it reduces the current through the transformer. At
signal frequencies lower than about 1MHz, the trans-
former core size required to maintain low distortion gets
larger, and at some lower frequencies this becomes
impractical.

A differential resistor loaded output configuration is shown
in the Block Diagram. It is simple and economical, but it
can drive only differential loads with impedance levels and
amplitudes appropriate for the DAC outputs.

The recommended single-ended resistor loaded configu-
ration is essentially the same circuit as the differential
resistor loaded, case--simply use the I

OUT A

output,

referred to ground. Rather than tying the unused I

OUT B

output to ground, it is preferred to load it with the equiva-
lent R

LOAD

of I

OUT A

. Then I

OUT B

will still swing with a

waveform complementary to I

OUT A

Adding an op amp differential to single-ended converter
circuit to the differential resistor loaded output gives the
circuit of Figure 10.

This circuit complements the capabilities of the trans-
former-coupled application at lower frequencies, since
available op amps can deliver good AC distortion perfor-
mance at signal frequencies of a few MHz down to DC. The
optional capacitor adds a single real pole of filtering, and
helps reduce distortion by limiting the high frequency
signal amplitude at the op amp inputs. The circuit swings

1V around ground.

Figure 3 shows a simplified circuit for a single-ended
output using I-to-V converter to produce a unipolar
buffered voltage output. This configuration typically has
the best DC linearity performance, but its AC distortion at
higher frequencies is limited by U1's slewing capabilities.

200

1668 F03

OUT A

OUT B

LADCOM

LTC1668

200

OUT

0V TO 2V

OUTFS

10mA

OUT

1812

Figure 3. Unipolar Buffered Voltage Output

Digital Interface

The LTC1668 has 16 parallel inputs that are latched on the
rising edge of the clock input. They accept CMOS levels
from either 5V or 3.3V logic and can accept clock rates of
up to 50MHz.

Referring to the Timing Diagram and Block Diagram, the
data inputs go to master-slave latches that update on the
rising edge of the clock. The input logic thresholds, V

2.4V min, V

= 0.8V max, work with 3.3V or 5V CMOS

levels over temperature. The guaranteed setup time, t

is 8ns minimum and the hold time, t

, is 4ns minimum.

The minimum clock high and low times are guaranteed at
6ns and 8ns, respectively. These specifications allow the
LTC1668 to be clocked at up to 50Msps minimum.

For best AC performance, the data and clock waveforms
need to be clean and free of undershoot and overshoot.
Clock and data interconnect lines should be twisted pair,
coax or microstrip, and proper line termination is impor-
tant. If the digital input signals to the DAC are considered
as analog AC voltage signals, they are rich in spectral
components over a broad frequency range, usually in-
cluding the output signal band of interest. Therefore, any
direct coupling of the digital signals to the analog output
will produce spurious tones that vary with the exact digital
input pattern.

Clock jitter should be minimized to avoid degrading the
noise floor of the device in AC applications, especially
where high output frequencies are being generated. Any
noise coupling from the digital inputs to the clock input will

LTC1668

APPLICATIO S I FOR ATIO

cause phase modulation of the clock signal and the DAC
waveform, and can produce spurious tones. It is normally
best to place the digital data transitions near the falling
clock edge, well away from the active rising clock edge.
Because the clock signal contains spectral components
only at the sampling frequency and its multiples, it is
usually not a source of in band spurious tones. Overall, it
is better to treat the clock as you would an analog signal
and route it separately from the digital data input signals.
The clock trace should be routed either over the analog
ground plane or over its own section of the ground plane.
The clock line needs to have accurately controlled imped-
ance and should be well terminated near the LTC1668.

Printed Circuit Board Layout Considerations--
Grounding, Bypassing and Output Signal Routing

The close proximity of high frequency digital data lines and
high dynamic range, wide-band analog signals makes
clean printed circuit board design and layout an absolute
necessity. Figures 5 to 9 are the printed circuit board layers
for an AC evaluation circuit for the LTC1668. Ground
planes should be split between digital and analog sections
as shown. All bypass capacitors should have minimum
trace length and be ceramic 0.1

F or larger with low ESR.

Bypass capacitors are required on V

, V

and REFOUT,

and all connected to the AGND plane. The COMP2 pin ties
to a node in the output current switching circuitry, and it
requires a 0.1

F bypass capacitor. It should be bypassed

to V

along with COMP1. The AGND and DGND pins

should both tie directly to the AGND plane, and the tie point
between the AGND and DGND planes should nominally be
near the DGND pin. LADCOM should either be tied directly
to the AGND plane or be bypassed to AGND. The I

OUT A

and

OUT B

traces should be close together, short, and well

matched for good AC CMRR. The transformer output
ground should be capable of optionally being isolated or
being tied to the AGND plane, depending on which gives
better performance in the system.

Suggested Evaluation Circuit

Figure 4 is the schematic and Figures 5 to 9 are the circuit
board layouts for a suggested evaluation circuit, DC245A.
The circuit can be programmed with component selection
and jumpers for a variety of differentially coupled trans-
former output and differential and single-ended resistor
loaded output configurations.

LTC1668

APPLICATIO S I FOR ATIO

Figure 4. Suggested Evaluation Circuit

OUT

OUT B

EXTCLK

JP9

1.91k

0.1%

200

JP1

C17

0.1

L
TC1668-28

0.1

TP5

TESTPOINT WHT

0.1

C18

0.1

C10

0.1

C11

0.1

0.1%

R12

49.9

JP6

R10

0.1%

C12

22pF

C12

22pF

0.1

JP5

TP3

TESTPOINT

WHT

JP7

JP3

110

JP4

JP2

REFOUT

REFIN

DB15 (MSB)

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

CLK

OUT A

OUT B

COMP1

COMP2

LADCOM

AGND

DGND

OUT A

MINI-

CIRCUITS

T11T

JP8

TP4

TESTPOINT WHT

RN5

5VD

J10

TP6

TESTPOINT RED

L
T1460DCS8-2.5

AMP

102159-9

RN6

TP2

TESTPOINT WHT

2.5V

REF

TP10

TESTPOINT BLK

TP1

OUT

GND

0.1

EXTREF

C19

0.1

C14

25V

AGND

DGND

TP8

TESTPOINT RED

GROUND PLANE

TIE POINT

C20

0.1

C16

25V

1668 F04

C22

0.1

J11

TP7

TESTPOINT RED

TP9

TESTPOINT BLK

C23

0.1

C15

25V

C21

0.1

OPTIONAL

SIP

PULL-UP/

PULL-DOWN

RESISTORS

(NOT

INST

ALLED)

OPTIONAL

SIP

PULL-UP/

PULL-DOWN

RESISTORS

(NOT

INST

ALLED)

5VD

LTC1668

LINEAR TECHNOLOGY CORPORATION 2000

1668i LT/TP 0200 4K · PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear-tech.com

PART NUMBER

DESCRIPTION

COMMENTS

LTC1406

8-Bit, 20Msps ADC

Undersampling Capability Up to 70MHz Input

LTC1414

14-Bit, 2.2Msps ADC

84dB SFDR at 1.1MHz f

LTC1420

12-Bit, 10Msps ADC

72dB SINAD at 5MHz f

LTC1604

16-Bit, 333ksps ADC

16-Bit, No Missing Codes, 90dB SINAD, 100dB THD

RELATED PARTS

TYPICAL APPLICATIO

Figure 10. High Speed Buffered V

OUT

DAC

16-BIT

HIGH SPEED

DAC

2.5V

REFERENCE

CLOCK

INPUT

16-BIT DATA

INPUT

LADCOM

AGND DGND

CLK

DB15

DB0

1668 F10

OUT A

0.1

LTC1668

REFIN

REFOUT

COMP1

COMP2

0.1

SET

OUT B

0.1

500

OUT

10dBm

1812

200

OPT

52.3

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1668

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1668