LTC1421/LTC1421-2.5

Hot Swap Controller

FEATURES

Allows Safe Board Insertion and Removal from a
Live Backplane

System Reset and Power Good Control Outputs

Programmable Electronic Circuit Breaker

User Programmable Supply Voltage Power-Up Rate

High Side Driver for Two External N-Channels

Controls Supply Voltages from 3V to 12V

Connection Inputs Detect Board Insertion or Removal

Undervoltage Lockout

Power-On Reset Input

DESCRIPTIO

Hot Board Insertion

Electronic Circuit Breaker

APPLICATIO

The LTC

1421/LTC1421-2.5 are Hot Swap

controllers

that allow a board to be safely inserted and removed from a
live backplane. Using external N-channel pass transistors,
the board supply voltages can be ramped up at a program-
mable rate. Two high side switch drivers control the N-
channel gates for supply voltages ranging from 3V to 12V.

A programmable electronic circuit breaker protects against
shorts. Warning signals indicate that the circuit breaker
has tripped, a power failure has occurred or that the switch
drivers are turned off. The reset output can be used to
generate a system reset when the power cycles or a fault
occurs. The two connect inputs can be used with stag-
gered connector pins to indicate board insertion or re-
moval. The power-on reset input can be used to cycle the
board power or clear the circuit breaker.

The trip point of the ground sense comparator is set at
0.1V for LTC1421 and 2.5V for LTC1421-2.5.

The LTC1421/LTC1421-2.5 are available in 24-pin SO and
SSOP packages.

TYPICAL APPLICATIO

RAMP

CPON

COMP

REF

COMPOUT

PWRGD

RESET

CON2

AUXV

FAULT

POR

CON1

CCLO

SETLO GATELO V

OUTLO

LTC1421

GND

DISABLE

CCHI

SETHI GATEHI V

OUTHI

C2
0.1

C1
1

R5
16k
5%

MTB50N06E

0.005

R3
1k

STAGGERED CONNECTOR

R6
20k
1%

C3
220

R4
20k
5%

R7
7.15k
1%

1/2 Si4936DY

0.47

0.025

C5
220

12V
1A

5V
5A

C4
220

I/O

RESET

BEA

BEB

GND

QS3384

QuickSwitch

QuickSwitch IS A REGISTERED TRADEMARK
OF QUALITY SEMICONDUCTOR CORPORATION.

1421 TA01

DATA BUS

PC BOARD

BACKPLANE

DATA

BUS

GND

POR

FAULT

, LTC and LT are registered trademarks of Linear Technology Corporation.

Hot Swap is a trademark of Linear Technology Corporation.

LTC1421/LTC1421-2.5

ABSOLUTE

AXI

RATINGS

PACKAGE/ORDER I FOR ATIO

Consult factory for Industrial and Military grade parts.

(Note 1)

Supply Voltage (V

CCLO

CCHI

, AUXV

) .............. 13.2V

Input Voltage (Analog Pins) ..... 0.3V to (V

CCHI

+ 0.3V)

Input Voltage (Digital Pins) ................... 0.3V to 13.2V
Output Voltage (Digital Pins) .. 0.3V to (V

CCLO

+ 0.3V)

Output Voltage (CPON) ......... 13.2V to (V

CCLO

+ 0.3V)

Output Voltage (V

OUTLO

, V

OUTHI

) ........... 0.3V to 13.2V

Output Voltage (GATELO, GATEHI) ........... 0.3V to 20V
Operating Temperature Range .................... 0

C to 70

Storage Temperature Range ................ 65

C to 150

Lead Temperature (Soldering, 10 sec)................. 300

ORDER PART

NUMBER

JMAX

= 125

= 100

C/W (G)

JMAX

= 125

= 85

C/W (SW)

TOP VIEW

SW PACKAGE

24-LEAD PLASTIC SO

G PACKAGE

24-LEAD PLASTIC SSOP

CON1

CON2

POR

FAULT

DISABLE

PWRGD

RESET

REF

CPON

RAMP

GND

AUXV

CCLO

SETLO

GATELO

OUTLO

CCHI

SETHI

GATEHI

OUTHI

COMPOUT

COMP

ELECTRICAL CHARACTERISTICS

CCHI

= 12V, V

CCLO

= 5V, T

= 25

C unless otherwise noted (Note 2).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DC Characteristics

CCLO

Supply Current

CON1 = CON2 = GND, POR = V

CCLO

1.5

CCHI

Supply Current

CON1 = CON2 = GND, POR = V

CCLO

0.6

LKO

Undervoltage Lockout

CCLO

and V

CCHI

2.28

2.45

2.60

LKH

Undervoltage Lockout Hysteresis

CCLO

and V

CCHI

100

REF

Reference Output Voltage

No Load

1.220

1.232

1.244

LNR

Reference Line Regulation

CCLO

12V, No Load

LDR

Reference Load Regulation

0mA to 5mA, Sourcing Only

RSC

Reference Short-Circuit Current

REF

= 0V

COF

Comparator Offset Voltage

CCLO

1.3V)

CPSR

Comparator Power Supply Rejection

CCLO

1.3V), 3V

CCLO

12V

mV/V

CHST

Comparator Hysteresis

CCLO

1.3V)

RST

Reset Voltage Threshold (V

OUTLO

)

FB = V

OUTLO

2.80

2.90

3.00

FB = Floating

4.50

4.65

4.75

FB = GND

5.75

5.88

6.01

RHST

Reset Threshold Hysteresis (V

OUTLO

)

FB = V

OUTLO

FB = Floating

FB = GND

FB Pin Input Resistance

CCLO

Circuit Breaker Trip Voltage

= (V

CCLO

SETLO

) or V

= (V

CCHI

SETHI

)

TRIP

Output Voltage for Re-Power-Up

LTC1421 (Note 3)

0.1

LTC1421-2.5 (Note 4)

2.5

LTC1421CG
LTC1421CSW
LTC1421-2.5CG
LTC1421-2.5CSW

LTC1421/LTC1421-2.5

ELECTRICAL CHARACTERISTICS

CCHI

= 12V, V

CCLO

= 5V, T

= 25

C unless otherwise noted (Note 2).

Note 3: After power-on reset, the V

OUTLO

and V

OUTHI

have to drop below the

TRIP

point before the charge pump is restarted.

Note 4: After power-on reset, the V

OUTLO

has to drop below the V

TRIP

point

before the charge pump is restarted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

RAMP

RAMP Pin Output Current

Charge Pump On, V

RAMP

0.4V

Charge Pump Output Current

Charge Pump On, GATEHI = 0V

600

GATELO = 0V

300

GATEHI

GATEHI N-Channel Gate Drive

GATEHI

OUTHI

GATELO

GATELO N-Channel Gate Drive

GATELO

OUTLO

AUXVCC

Auxiliary V

Output Voltage

CCLO

= 5V, Unloaded

4.5

Input Low Voltage

CON1, CON2, POR

0.8

Input High Voltage

CON1, CON2, POR

Input Current

CON1, CON2, POR = GND

Output Low Voltage

RESET, COMPOUT, PWRGD, DISABLE, FAULT,

0.4

= 3mA

CPON, I

= 3mA

1.45

Output High Voltage

DISABLE, I

= 3mA

CPON, I

= 1mA

3.4

Logic Output Pull-Up Current

RESET, PWRGD, FAULT = GND

AC CHARACTERISTICS

CON1 or CON2

to CPON

Figure 1, C

= 15pF

PWRGD

to RESET

Figure 1, R

= 10k to V

CCLO

, C

= 15pF

160

200

240

140

200

280

PWRGD

to DISABLE

Figure 1, C

= 15pF

160

200

240

140

200

280

POR

to CPON

Figure 1, C

= 15pF

PWRGD

to RESET

Figure 1, R

= 10k to V

CCLO

, C

= 15pF

POR

to CPON

Figure 1, C

= 15pF

CON1 or CON2

to CPON

Figure 1, C

= 15pF

Short-Circuit Detect

to FAULT

Figure 1, R

= 10k to V

CCLO

, C

= 15pF

CCLO

SETLO = 0mV to 100mV

Short-Circuit Detect

to CPON

Figure 2, C

= 15pF

CCLO

SETLO = 0mV to 100mV

POR

to FAULT

Figure 2, R

= 10k to V

CCLO

, C

= 15pF

CHL

Comparator High to Low

COMP

= 1.232V, 10mV Overdrive

0.25

0.5

= 10k to V

CCLO

, C

= 15pF

CLH

Comparator Low to High

COMP

= 1.232V, 10mV Overdrive

1.5

= 10k to V

CCLO

, C

= 15pF

The

denotes specifications which apply over the full operating temperature

range.

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are reference to ground unless otherwise
specified.

LTC1421/LTC1421-2.5

TYPICAL PERFOR

CE CHARACTERISTICS

TEMPERATURE (

1.232

1.234

1.238

1421 G01

1.230

1.228

100

125

1.226

1.224

1.236

REFERENCE VOLTAGE (V)

CCLO

= 5V

CCHI

= 12V

Reference Voltage vs
Temperature

SOURCE CURRENT (mA)

REFERENCE VOLTAGE (V)

1.235

1.240

1.245

1421 G03

1.230

1.225

1.220

CCLO

= 5V

CCHI

= 12V

Reference Voltage
vs Source Current

Gate Voltage vs Temperature

TEMPERATURE (

1421 G02

100

125

GATE VOLTAGE (V)

CCLO

= 5V

CCHI

= 12V

GATEHI

GATELO

GATELO Voltage vs V

CCLO

Voltage

CCLO

VOLTAGE (V)

1421 G04

GATELO VOLTAGE (V)

CCHI

= 12V

GATEHI Voltage vs V

CCHI

Voltage

CCHI

VOLTAGE (V)

1421 G05

GATEHI VOLTAGE (V)

CCLO

= 5V

CCLO

Supply Current

vs Temperature

TEMPERATURE (

1400

1421 G06

1300

100

125

1200

1500

CCLO

SUPPLY CURRENT (

CCLO

= 5V

CCHI

= 12V

vs I

SINK

CPON Voltage vs Sink Current
(Charge Pump Off)

CCHI

Supply Current

vs Temperature

TEMPERATURE (

540

1421 G07

530

100

125

520

550

545

535

525

555

CCHI

SUPPLY CURRENT (

CCLO

= 5V

CCHI

= 12V

SINK CURRENT (mA)

VOLTAGE (mV)

100

200

300

400

500

FAULT

600

1421 G08

CCLO

= 5V

CCHI

= 12V

COMPOUT

PWRGD

RESET

SINK CURRENT (mA)

CPON VOLTAGE (V)

0.5

1.0

1.5

2.0

2.5

0.5

1.0

1.5

2.0

1421 G09

2.5

3.0

CCLO

= 5V

CCHI

= 12V

LTC1421/LTC1421-2.5

TYPICAL PERFOR

CE CHARACTERISTICS

CPON Voltage vs Source Current
(Charge Pump On)

SOURCE CURRENT (mA)

CPON VOLTAGE (V)

0.5

1.0

1.5

2.0

1421 G10

2.5

3.0

CCLO

= 5V

CCHI

= 12V

CCLO

Supply Current

vs V

CCLO

Voltage

CCLO

VOLTAGE (V)

1421 G11

CCLO

SUPPLY CURRENT (mA)

CCHI

= 12V

CTIO

CON1 (Pin 1): TTL Level Input with a Pull-Up to V

CCLO

Together with CON2, it is used to indicate board connec-
tion. The pin must be tied to ground on the host side of the
connector. When using staggered connector pins, CON1
and CON2 must be the shortest and must be placed at
opposite corners of the connector. Board insertion is
assumed after CON1 and CON2 are both held low for 20ms
after power-up.

CON2 (Pin 2): TTL Level Input with a Pull-Up to V

CCLO

Together with CON1 it is used to indicate board connec-
tion.

POR (Pin 3): TTL Level Input with a Pull-Up to V

CCLO

When the pin is pulled low for at least 20ms, a hard reset
is generated. Both V

OUTLO

and V

OUTHI

will turn off at a

controlled rate. A power-up sequence will not start until
the POR pin is pulled high. If POR is pulled high before
V

OUTLO

and V

OUTHI

are fully discharged, a power-up

sequence will not begin until the voltage at V

OUTLO

and

OUTHI

are below V

TRIP

. The electronic circuit breaker will

be reset by pulling POR low.

FAULT (Pin 4): Open Drain Output to GND with a Weak
Pull-Up to V

CCLO

. The pin is pulled low when an overcur-

rent fault is detected at V

OUTLO

or V

OUTHI

DISABLE (Pin 5): CMOS Output. The signal is used to
disable the board's data bus during insertion or removal.

PWRGD (Pin 6): Open Drain Output to GND with a Weak
Pull-Up to V

CCLO

. The pin is pulled low immediately after

OUTLO

falls below its reset threshold voltage. The pin is

pulled high immediately after V

OUTLO

rises above its reset

threshold voltage.

RESET (Pin 7): Open Drain Output to GND with a Weak
Pull-Up to V

CCLO

. The pin is pulled low when a reset

condition is detected. A reset will be generated when any
of the following conditions are met: Either CON1 or CON2
is high, POR is pulled low, V

CCLO

or V

CCHI

are below their

respective undervoltage lockout thresholds, PWRGD goes
low or an overcurrent fault is detected at V

OUTLO

OUTHI

. RESET will go high 200ms after PWRGD goes

high. On power failure, RESET will go low 32

s after

PWRGD goes low.

REF (Pin 8): The Reference Voltage Output. V

OUT

= 1.232V

1%. The reference can source up to 5mA of current. A

F bypass capacitor is recommended.

CPON (Pin 9): CMOS Output That Can Be Pulled Below
Ground. CPON is pulled high when the internal charge
pumps for GATELO and GATEHI are turned on. CPON is
pulled low when the charge pumps are turned off. The pin
can be used to control an external MOSFET for a 5V to
12V supply.

LTC1421/LTC1421-2.5

CTIO

RAMP (Pin 10): Analog Power-Up Ramp Control Pin. By
connecting an external capacitor between the RAMP and
GATEHI, a positive linear voltage ramp on GATEHI and
GATELO is generated on power-up with a slope equal to
20

A/C

RAMP.

FB (Pin 11): Analog Feedback Input. FB is used to set the
reset threshold voltage on V

CCLO

. For a 5V supply leave FB

floating. For a 3.3V supply, short FB to V

CCLO

GND (Pin 12): Ground

COMP + (Pin 13): Noninverting Comparator Input.

COMP (Pin 14): Inverting Comparator Input.

COMPOUT (Pin 15): Open Drain Comparator Output.

OUTHI

(Pin 16): High Supply Voltage Output. This must be

the higher of the two supply voltage outputs.

GATEHI (Pin 17): The High Side Gate Drive for the High
Supply N-Channel. An internal charge pump guarantees at
least 6V of gate drive. The slope of the voltage rise at
GATEHI is set by the external capacitor connected between
GATEHI and RAMP. When the circuit breaker trips, GATEHI
is immediately pulled to GND.

SETHI (Pin 18): The Circuit Breaker Set Pin for the High
Supply. With a sense resistor placed in the supply path
between V

CCHI

and SETHI, the circuit breaker will trip when

the voltage across the resistor exceeds 50mV for more
than 20

s. To disable the circuit breaker, V

CCHI

and SETHI

should be shorted together.

CCHI

(Pin 19): The Positive Supply Input. This must be the

higher of the two input supply voltages. An undervoltage
lockout circuit disables the chip until the voltage at V

CCHI

is greater than 2.45V.

OUTLO

(Pin 20): Low Supply Voltage Output. This must be

the lower of the two supply voltage outputs.

GATELO (Pin 21): The High Side Gate Drive for the Low
Supply N-Channel Pass Transistor. An internal charge
pump guarantees at least 10V of gate drive. The slope of
the voltage rise at GATELO is set by the external capacitor
connected between GATEHI and RAMP. When the circuit
breaker trips GATELO is immediately pulled to GND.

SETLO (Pin 22): The Circuit Breaker Set Pin for the Low
Supply. With a sense resistor placed in the supply path
between V

CCLO

and SETLO, the circuit breaker will trip

when the voltage across the resistor exceeds 50mV for
more than 20

s. To disable the circuit breaker, V

CCLO

and

SETLO should be shorted together.

CCLO

(Pin 23): The Positive Supply Input. V

CCLO

must be

equal to or lower voltage than V

CCHI

. An undervoltage

lockout circuit disables the chip until the voltage at V

CCLO

is greater than 2.45V.

AUXV

(Pin 24): The supply input for the GATELO and

GATEHI discharge circuitry. Connect a 1

F capacitor to

ground. AUXV

is powered from V

CCLO

via an internal

Schottky diode and series resistor.

LTC1421/LTC1421-2.5

BLOCK DIAGRA

Figure 1. Nominal Operation Switching Waveforms

Figure 2. Fault Detection Switching

CPON

CON1

CON2

RESET

DISABLE

POR

1421 F01

PWRGD

CPON

CCLO

SETLO

FAULT

RESET

POR

1421 F02

PWRGD

SWITCHI G TI E WAVEFOR S

+
+

TRIP

50mV

CPON

AUXV

CCHI

SETLO

CP1

CP2

CCLO

SETHI

GATELO

RAMP

GATEHI

OUTHI

OUTLO

FAULT

CON1

CON2

POR

DISABLE

CP3

CP4

CP5

73.5k

AUXV

REF

PWRGD

RESET

COMPOUT

COMP

1421 BD

71.5k

26.7k

1.232V

REFERENCE

CHARGE

PUMP

UNDERVOLTAGE

LOCKOUT

RESET

TIMING

GND

DIGITAL CONTROL

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

Hot Circuit Insertion

When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the board can draw huge
transient currents from the backplane power bus as they
charge up. The transient currents can cause permanent
damage to the connector pins and cause glitches on the
system supply, causing other boards in the system to
reset. At the same time, the system data bus can be
disrupted when the board's data pins make or break
connection.

The LTC1421 is designed to turn a board's supply voltages
on and off in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
also provides a disable signal for the board's data bus
buffer during insertion or removal and provides all the
necessary supply supervisory functions for the board.

Power Supply Ramping

The power supplies on a board are controlled by placing
external N-channel pass transistors in the power path
(Figure 3). R1 and R2 provide current fault detection. By
ramping the gate of the pass transistor up at a controlled
rate, the transient surge current (I = C · dV/dt) drawn from
the main backplane supply can be limited to a safe value
when the board makes connection.

Figure 3: Supply Control Circuitry

12V

CCLO

SETLO GATELO V

OUTLO

LTC1421

1421 F03

CCHI

SETHI GATEHI V

OUTHI

RAMP

CON1

CON2

RAMP

OUTHI

OUTLO

When power is first applied to the chip, the gates of both
N-channels, GATELO and GATEHI are pulled low. After the
connection sense pins, CON1 and CON2 are both held low
for at least 20ms, a 20

A reference current is connected

from the RAMP pin to GND. The voltage at GATEHI begins
to rise with a slope equal to 20

A/C

RAMP

(Figure 4), where

RAMP

is an external capacitor connected between the

Figure 4. Supplies Turning On

12V

1421 F4a

OUTHI

OUTLO

SLOPE = 20

A/C

RAMP

12V

~1ms

12V

CPON

R5
16k
5%

~1ms

1421 F05

R4
20k
5%

C2
0.047

C5
220

12V
1A

1/2 MMDF3N0HD

12V FROM

CONNECTOR

CPON

LTC1421

Figure 5. Negative Supply Control

RAMP and GATEHI pins. The voltage at the GATELO pin is
clamped one Schottky diode drop below GATEHI.

The ramp time for each supply is equal to: t = (V

)

RAMP

)/20

A. During power down the gates are actively

pulled down by two internal NFETs.

A negative supply voltage can be controlled using the
CPON pin as shown in Figure 5.

When the board makes connection, the transistor Q3 is
turned off because it's gate is pulled low to 12V by R4.
CPON is also pulled to 12V. When the charge pump is
turned on, CPON is pulled to V

CCLO

and the gate of Q3 will

ramp up with a time constant determined by R4, R5 and
C2. When the charge pump is turned off, CPON goes into
a high impedance state, the gate of Q3 is discharged to V

with a time constant determined by R4 and C2, and Q3
turns off.

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

PWRGD and RESET

The LTC1421 uses a 1.232V bandgap reference, internal
resistive divider and a precision voltage comparator to
monitor V

OUTLO

(Figure 6).

The reset threshold voltage for V

OUTLO

is determined by

the FB pin connection as summarized in Table 1.

When V

OUTLO

drops below its reset threshold, the com-

parator output goes high, and PWRGD is immediately
pulled low (time point 2). After a 32

s delay, RESET is

pulled low. The RESET delay allows the PWRGD signal to
be used as an early warning that a reset is about to occur.
If the PWRGD signal is used as a interrupt input to a
microprocessor, a short power-down routine can be run
before the reset occurs.

If V

OUTLO

rises above the reset threshold for less than

200ms, the PWRGD output will trip, but the RESET output is
not affected (time point 3). If V

OUTLO

drops below the reset

threshold for less than 32

s, the PWRGD output will trip, but

again the RESET output will not be affected (time point 5).

Voltage Comparator

The uncommitted voltage comparator (COMP2) can be
used to monitor output voltages other than V

OUTLO

. Figure

8a shows how the comparator can be used to monitor a
12V supply (V

OUTHI

), while the 5V supply (V

OUTLO

) gener-

ates a reset when it dips below 4.65V. When the 12V
supply drops below 10.8V, COMPOUT will pull low. The FB
pin is left floating.

Figure 8b shows how the comparator can be used to
monitor the 5V supply (V

OUTHI

) while the 3.3V supply

OUTLO

) generates a reset when it dips below 2.9V. When

the 5V supply drops below 4.65V, COMPOUT will pull low.
The FB pin is tied to V

OUTLO

Figure 6. Supply Monitor Block Diagram

CCLO

OUTLO

1421 F06

1.232V

26.7k

PWRGD

RESET

COMP1

RESET

TIMING

REF

73.5k

71.5k

OUTLO

PWRGD

RESET

200ms

< 200ms

200ms

1421 F07

< 64

Table 1

FEEDBACK PIN

OUTLO

RESET VOLTAGE

Floating

4.65V

OUTLO

2.90V

GND

5.88V

When the V

OUTLO

voltage rises above its reset threshold

voltage, the comparator output goes low, and PWRGD is
immediately pulled high to V

CCLO

by a weak pull-up

current source or external resistor (Figure 7, time points
1 and 4). After a 200ms delay, RESET is pulled high. The
weak pull-up current source to V

CCLO

on PWRGD and

RESET have a series diode so the pins can be pulled above
V

CCLO

by an external pull-up resistor without forcing

current back into V

CCLO

Figure 7. Power Monitor Waveforms

Figure 8a. Monitor 12V, Reset 5V at 4.65V

1421 F08a

10k
5%

107k
1%

13.7k
1%

12V

CCLO

1.232V

LTC1421

26.7k

COMP1

COMP2

RESET

TIMING

73.5k

107k
1%

71.5k

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

A 5k resistor is tied from the FB pin to V

OUTLO

, setting the

internal threshold to about 2.9V. The new reset threshold
voltage is set by the external resistive divider connected to
COMP2. When V

OUTLO

drops below the new threshold,

COMPOUT pulls FB to ground, changing the internal
threshold at COMP1 to 5.88V and generating a reset.

Finally, the comparator may be used to monitor a negative
supply as shown in Figure 8e. The external resistor divider

Figure 8c shows how the comparator can be used to
generate a reset when the 12V supply (V

OUTHI

) drops

below 10.8V. The 5V supply (V

OUTLO

) also generates a

reset when it dips below 4.65V. When the 12V supply
drops below 10.8V, COMPOUT will pull the FB pin low
setting the internal threshold voltage for comparator 1 to
5.88V. Since V

OUTLO

is less than 5.88V, PWRGD immedi-

ately goes low and a reset is generated 200ms later.

Figure 8d shows how the comparator can be used to
override the internal reset voltage for a 5V supply on
V

OUTLO

CCLO

1421 F08c

1.232V

LTC1421

26.7k

COMP1

COMP2

RESET

TIMING

73.5k

107k
1%

13.7k
1%

71.5k

12V

Figure 8c. Reset 12V at 10.8V, Reset 5V at 4.65V

Figure 8e. Monitor 12V at 10.8V, Reset 5V at 4.65V

CCLO

1421 F08e

1.232V

LTC1421

26.7k

COMP1

COMP2

RESET

TIMING

73.5k

107k
1%

10k
5%

13.7k
1%

71.5k

12V

Figure 8d. Reset 5V at 4.5V

CCLO

1421 F08d

1.232V

LTC1421

26.7k

COMP1

COMP2

RESET

TIMING

73.5k

102k
1%

38.3k
1%

71.5k

12V

CCLO

1421 F08b

1.232V

LTC1421

26.7k

COMP1

COMP2

RESET

TIMING

73.5k

10k
5%

107k
1%

38.3k
1%

71.5k

3.3V

Figure 8b. Monitor 5V, Reset 3.3V at 2.9V

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

is connected between REF (Pin 8) and the negative supply
and the trip point of Comparator 2 set to GND.

Soft Reset Generation

A soft reset that doesn't cycle the supply voltage can be
generated externally using Pin 11 (FB) as shown in Figure
9. For a 5V supply the FB pin is left floating to set the
internal supply monitor trip voltage to 4.65V. However, if
the FB pin is pulled to ground for more than 64

s via a push

button or open-collector logic gate, the internal trip point
will go to 5.88V and the RESET pin will pull low. RESET will
remain low for 200ms after the FB pin is released. The
RESET signal will also be pulled low when the voltage at
the V

OUTLO

pin dips below 4.65V for more than 32

When using a 3.3V supply, a 1k resistor must be con-
nected from the FB pin to V

CCLO

to set the internal trip point

to 2.90V.

sense resistor is greater than 50mV for more than 20

When the circuit breaker trips, both N-channel MOSFETs
are quickly turned off, FAULT and PWRGD go low and
RESET is pulled low 32

s later. FAULT can be connected

to a LED or a logic signal back to the host to indicate a faulty
board. The chip will remain in the tripped state until a
power-on reset is generated, or the power on V

CCHI

and

CCLO

is cycled. If the circuit breaker feature is not used,

short V

CCLO

to SETLO and V

CCHI

to SETHI.

If more than 20

s of response time is needed to reject

supply noise, an external resistor and capacitor can be
added to the sense circuit as shown in Figure 10.

Figure 9. Generating a Soft Reset

Undervoltage Lockout

On power-up, an undervoltage lockout circuit prevents the
GATELO and GATEHI charge pumps from turning on until
V

CCLO

and V

CCHI

have both exceeded 2.45V.

Electronic Circuit Breaker

The LTC1421 features an electronic circuit breaker func-
tion that protects against short circuits or excessive cur-
rents on the supplies. By placing a sense resistor between
the supply input and set pin of either supply, the circuit
breaker will be tripped whenever the voltage across the

LTC1421

3.3V

1/6 LS7404

OPEN

COLLECTOR

GND

200ms

1421 F09

R1
1k

R1 USED FOR 3.3V
SUPPLY ONLY

RESET

LOGIC

SENSE

CCLO

SETLO

GATELO

OUTLO

LTC1421

1421 F10

Figure 10. Short-Circuit Protection Circuit

Figure 11. AUXV

Circuitry

GATE DRIVE

CIRCUITRY

10k

AUXV

1421 F11

CCLO

LTC1421

GATELO GATEHI

Auxiliary V

When a short circuit occurs on the board, it is possible to
draw enough current to cause the backplane supply
voltage to collapse. If the input supply voltage collapses to
a low enough voltage and the LTC1421 gate drive circuitry
is unable to shut off the N-channel pass transistors, the
system might freeze up in a permanent short condition.

To prevent this from occurring, the gate discharge cir-
cuitry inside the LTC1421 is powered from AUXV

which is in turn powered from V

CCLO

through an internal

Schottky diode and current limiting resistor (Figure 11).

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

When V

CCLO

collapses, there is enough energy stored on

the 1

F capacitor connected to AUXV

to keep the gate

discharge circuitry alive long enough to fully turn off the
external N-channels.

Power N-Channel Selection

The R

DS(ON)

of the external pass transistor must be low

enough so that the voltage drop across it is about 200mV
or less at full current. If the R

DS(ON)

is too high, the voltage

drop across the transistor might cause the output voltage
to trip the reset circuit. Table 2 lists the transistors that are
recommended for use with the LTC1421.

Table 2. N-Channel Selection Guide

CURRENT

PART

LEVEL (A)

NUMBER

MANUFACTURER

DESCRIPTION

0 to 1

MMDF2N02E

Motorola

Dual N-Channel SO-8
R

DS(ON)

= 0.1

1 to 2

MMDF3NO2HD

Motorola

Dual N-Channel SO-8
R

DS(ON)

= 0.09

2 to 5

MTB30N06

Motorola

Single 30A
N-Channel DD Pak
R

DS(ON)

= 0.05

5 to 10

MTB50N06E

Motorola

Single
N-Channel DD Pak
R

DS(ON)

= 0.025

10 to 20

MTB75N05HD

Motorola

Single
N-Channel DD Pak
R

DS(ON)

= 0.0095

Data Bus

When a board is inserted or removed from the host, care
must be given to prevent the system data bus from being
corrupted when the data pins make or break contact. One
problem is that the fully discharged input or output capaci-
tance of the logic gates on the board will draw an inrush
current when the data bus pins first make contact. The
inrush current can temporarily corrupt the data bus, but
usually will not cause long term damage. The problem can
be minimized by insuring the input or output data bus
capacitance is kept as small as possible.

The second, and more serious problem involves the
diodes to V

at the input and output of most logic families

(Figure 12).

OUT

BACKPLANE

BOARD

1421 F12

DATA

BUS

CONNECTOR

Figure 12. Typical Logic Gate Loading the Data Bus

Figure 13: Buffering the Data Bus

C4
2200

SYSTEM

DATA BUS

BOARD
DATA BUS

QS3384

GND

1421 F13

CONNECTOR

LTC1421

0.005

MTB50N06E

GND

DISABLE

With the board initially unpowered, the V

input to the

logic gate is at ground potential. When the data bus pins
make contact, the bus line is clamped to ground through
the input diode D1 to V

. Large amounts of current can

flow through the diode and cause the logic gate to latch up
and destroy itself when the power is finally applied. This

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

signal is pulled high, turning off the switches. After the
board supply voltage ramps up and RESET goes high,
DISABLE will pull low enabling the switches.

Board Insertion Timing

When the board is inserted, GND pin makes contact first,
followed by V

CCHI

and V

CCLO

(Figure 14, time point 1).

DISABLE is immediately pulled high, so the data bus
switch is disabled. At the same time CON1 and CON2 make
contact and are shorted to ground on the host side (time
point 3). Since most boards need to be rocked back and
forth to get them in place, there is a period of time when
only one side of the connector is making contact. CON1
and CON2 should be located at opposite ends of the
connector.

Figure 14. Board Insertion Timing

can usually be prevented by using logic that does not
include the clamping diodes such as the QSI 74FCTT
family from Quality Semiconductor, or by using a data bus
switch such as the 10-bit QS3384 QuickSwitch also from
Quality Semiconductor (Tel: 408-450-8000). The
QuickSwitch bus switch contains an N-channel placed in
series with the data bus. The switch is turned off when the
board is inserted and then enabled after the power is
stable. The switch inputs and outputs do not have a
parasitic diode back to V

and have very low capacitance.

The LTC1421 is designed to work directly with the
QuickSwitch bus switch as shown in Figure 13.

The DISABLE signal is connected to the enable pins of the
QS3384, and each switch is placed in series with a data
bus signal. When the board is inserted, the DISABLE

CCLO

CCHI

DISABLE

CON1

CON2

CPON

GATEHI

PWRGD

TH1

1421 F14

OUTHI

OUTLO

GATELO

RESET

FAULT

POR

200ms

20ms

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

When CON1 and CON2 are both forced to ground for more
than 20ms, the LTC1421 assumes that the board is fully
connected to the host and power-up can begin. When
V

CCLO

and V

CCHI

exceed the 2.45V undervoltage lockout

threshold, the 20

A current reference is connected from

RAMP to GND, the charge pumps are turned on and CPON
is forced high (time point 4). V

OUTHI

and V

OUTLO

begin to

ramp up. When V

OUTLO

exceeds the reset threshold volt-

age, PWRGD will immediately be forced high (time point
5). After a 200ms delay, RESET will be pulled high and
DISABLE will be pulled low, enabling the data bus (time
point 6).

Ground Sense Comparator

When POR is pulled low for more than 20ms, GATELO and
GATEHI are pulled to ground and V

OUTLO

and V

OUTHI

will

be discharged. If POR is pulled back high while V

OUTLO

and V

OUTHI

are still ramping down, the discharge will

continue. When they drop below the V

TRIP

point, a power-

up sequence will begin automatically. The trip point poten-
tial for LTC1421 is set at 0.1V and 2.5V for LTC1421-2.5.

In applications, where either V

OUTLO

or V

OUTHI

might be

forced above 100mV before power-up, the LTC1421-2.5
should be used. This could occur when leakage through
the body diode of the logic chips keeps V

OUTLO

high or in

the case where logic lines are precharged.

In other applications, where outputs need to drop to near
ground potential before ramping up again to ensure proper
initial state for the logic chips, the LTC1421 should be
used.

Power-On Reset Timing

The POR input is used to completely cycle the power
supplies on the board or to reset the electronic circuit
breaker feature. The POR pin can be connected to a
grounded push button, toggle switch or a logic signal
from the host. When POR is pulled low for more than
20ms, a power-on reset sequence begins (Figure 15,

Figure 15. Power-On Reset Timing

CCHI

CCLO

DISABLE

FAULT

POR

CON1

CON2

OUTLO

OUTHI

CPON

TH2

1421 F15

TH1

20ms

200ms

GATEHI

GATELO

RESET

PWRGD

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

time point 2). Pulses less than 20ms on POR are ignored.
CPON goes low. Both GATEHI and GATELO will be
actively pulled down to GND. When V

OUTLO

drops below

its reset threshold voltage, PWRGD will immediately pull
low (time point 3) followed by RESET and DISABLE 32

later (time point 4). Both supplies will be discharged to
ground and stay there until POR is pulled high.

The circuit breaker can be reset by pulling POR low. After
POR is low for more than 20ms, the chip will immediately
try to power up the supplies.

Circuit Breaker Timing

The waveforms for the circuit when a short occurs on
either supply during board insertion are shown in

Figure 16. Time points 1 to 4 are the same as the board
insertion example, but at time point 5, a short circuit is
detected on one of the supplies. The charge pumps are
immediately turned off, the outputs V

OUTHI

and V

OUTLO

are

actively pulled to GND and the CPON and FAULT pins are
pulled low. At time point 6, the circuit breaker is reset by
pulling POR low. After POR has been low for 20ms (time
point 7), CPON and FAULT are pulled high, the 20

reference current is connected to RAMP and the charge
pumps are enabled. V

OUTHI

and V

OUTLO

ramp up at a

controlled rate. When V

OUTLO

has exceeded its reset

threshold, the PWRGD signal is pulled high (time point 8).
After a 200ms delay, RESET is pulled high and DISABLE
goes low.

Figure 16. Circuit Breaker Timing

CCLO

CCHI

DISABLE

CON1

CON2

CPON

PWRGD

TH1

1421 F16

OUTHI

GATEHI

GATELO

OUTLO

RESET

FAULT

POR

20ms

200ms

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

CCLO

CCHI

DISABLE

CON1

CON2

CPON

PWRGD

TH2

1421 F17

OUTHI

GATEHI

GATELO

OUTLO

RESET

FAULT

POR

Figure 17. Board Removal Timing

Board Removal Timing

When the board is removed from the host, the sequence
happens in reverse (Figure 17). Since CON1 and CON2 are
the shortest pins, they break connection first and are
internally pulled high (time point 1). The charge pumps are
turned off, CPON is pulled low. V

OUTLO

and V

OUTHI

are

actively pulled down. When V

OUTLO

falls below its reset

threshold (time point 2) PWRGD is pulled low. To allow

time for power fail information to be stored in nonvolatile
memory, the falling edge of RESET (time point 3) is
delayed by 32

s from the falling edged of PWRGD.

Finally, the input supply pins V

CCHI

and V

CCLO

break

contact (time point 4). If staggered pins are not used, the
board may be powered down prior to removal by switch-
ing the POR pin to ground with a toggle switch.

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

5V Only Applications

The LTC1421 may be used in 5V only applications as shown
in Figure 18. A soft reset can be generated from the
backplane via an open-collector inverter driving the FB (Pin
11) or by a push button to ground. A hard power reset is
generated from the backplane via an open-collector inverter
driving the POR (Pin 3). A hard reset cycles the power on
the board or resets the electronic circuit breaker. The
comparator is used to monitor the board supply voltage and

will pull the POWERGOOD signal low as long as the supply
remains above 4.65V. Note that a soft reset will not affect
the POWERGOOD signal. The FAULT signal is also moni-
tored to determine that the circuit breaker has tripped.

 48V and 24V Applications

The LTC1421 may be used in 48V applications as shown
in Figure 19. The LTC1421 provides the hot insertion
protection, while the 5V supply is generated by a power

Figure 19. 48V to 5V Hot Swappable Supply

LTC1421

MTB50N06E

C1
1

C2
1

R2
28k
1%

1421 F18

POWERGOOD

FAULT

SOFT RESET

HARD RESET

0.005

R3
10.2k
1%

RESET

LOGIC

C2
2200

10k

1/6
LS7004

PC BOARD

BACKPLANE

Figure 18. 5V Only Application with Soft Reset

300

1/8W

R3
56k
1/2W

Q2
MPSA06

IRFR9110

C1
1

48V

STAGGERED CONNECTOR

C2
2.2

25V

R1
5k
1W

2.2

25V

C4
100

16V

5V
2A

C4
100

100V

1421 F19

PC BOARD

BACKPLANE

48V

R5
10k
1/2W

R6
400

1/8W

R2
15k
1/8W

ASTRODYNE

ASD 10-48S5

CONTROL

+IN

+OUT

OUT

LTC1421

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

Figure 23 shows how to use the LTC1421 with a 5V supply
and an LTC1430CS8 synchronous step-down switching
regulator to generate 3.3V output at up to 10A for micro-
processors. Resistors R4, R8 and R9 set the turn-on
voltage at 4.8V and the turn-off at 4.25V. Pushbutton
switch S1 provides users a way to reset the output while
S2 is used to soft-reset the microprocessor only.

Figure 24 shows how to use the LTC1421 with a 5V supply
and a 48V supply that is used to generate a

12V supply

using a supply module. Resistors R3 and R4 are used to
monitor the input voltage to the supply module. The
module is prevented from turning on via the optoisolator
until the input voltage reaches 36V. Zener diode D2
prevents the CPON pin of the LTC1421 from being dam-
aged by excessive voltage.

Figure 25 shows how to use the LTC1421 to do overvolt-
age protection. Resistors R3 and R4 set the trip point at
7V. When the input supply voltage rises above 7V, Q2 is
turned on and Q1 turned off while Q3 helps to discharge
the output voltage.

Figure 26 shows how to use the LTC1421 to control both
the power-up and power-down sequence of the outputs.
The 5V output would be powered up first followed by the
3V output. At power-down sequence, the 3V output would
go down first followed by the 5V supply.

Figure 27 shows how to use the LTC1421 to switch 3.3V,
5V, 12V and 12V supplies for PCI application. The ramp-
up rate for 3.3V, 5V and 12V is determined by the ramp
capacitor C2 while the 12V supply is controlled by R7 and
C3. The internal comparator is being used to do the
overcurrent protection for Q4 with the trip point set by
resistors R6 and R8. The 12V supply does not have
overcurrent protection. R10 is used to set the power good
signal trip point at 10V. When the 12V output rises above
10V, the PCI controller gets a power good signal followed
by RESET after 200ms.

module. The ground pin for the LTC1421 is connected to
48V; Zener diode D1 and resistor R1 provide the positive
supply for the chip. Bypass capacitor C4 is protected
against inrush current by P-channel Q1. When the board
is inserted into the backplane, transistor Q1 is turned off
by resistor R2. When the connection sense pins, CON1
and CON2 have been connected to 48V for more than
20ms, CPON pulls high turning on Q2 and the gate of Q1
starts to pull low with a time constant determined by R2,
R3 and C3. At the same time, the voltage at the input to the
power module starts to ramp up. When the voltage across
the inputs to the power module reaches the comparator
trip level set by R5 and R6, in this case 32V, the
comparator output pulls high and turns on the 5V supply.

A cheaper solution is shown in Figure 20 using the
LT

1170HV switcher. Again P-channel transistor Q1 pro-

tects the bypass capacitors against inrush current and
resistors R5 and R6 set the comparator trip voltage. The
LT1170HV is turned on via the V

pin. Resistors R11, R14

and transistor Q4 provide a monitoring path for the RESET
signal which is level shifted up to 5V through an optoiso-
lator.

The P-channel power FET is being replaced by an
N-channel FET in Figure 21 for the 48V application.
Again, Zener Diode D1 and resistor R1 provide the positive
supply for the chip. Capacitor C1 is to insure Q1 stays off
when the board is being hot inserted into the backplane.
The resistor divider R1 and R2, along with the internal
comparator, perform the undervoltage lock out function.
Q1 would only be turned on when the input supply voltage
is lower than 42V. The power module would then be
turned on by the optoisolator, 4N25, when the module's
input voltage reaches 47V.

Figure 22 shows how to use the LTC1421 with a 24V
supply and a LT1074CT step-down switcher. Resistors R5
and R6 set the turn-on threshold to 22V. All of the
supervisory signals can be used without level shifting.

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

LTC1421

300

1/8W

56k

1/2W

MPSA06

IRFR9110

48V

STAGGERED CONNECTOR

2.2

25V

2.2

25V

4.7

50V

0.33

50V

4.7

50V

100

100V

100

MBR3100

2N5401

MBR3100

7.5V

1421 F20

PC BOARD

BACKPLANE

48V

10k

1/2W

400

1/8W

15k

1/8W

LT1170HVCT

GND

R10

4.32k

1/8W

R11

4.32k

1/8W

R13

1.24k

1/8W

R14

4.64k

1/8W

R12

10k

1/8W

RESET

1000

25V

1000

25V

Figure 20.

48V to 5V Hot Swappable Supply Using the LT1170HVCT

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

Figure 21. 48V to 5V Hot Swappable Supply

Figure 22. 24V to 5V Hot Swappable Supply Using the LT1074CT

LTC1421

300

1/8W

R3
56k
1/8W

Q2
MPSA06

IRFR9110

C1
1

STAGGERED CONNECTOR

C2
2.2

25V

R1
5k
1/4W

2.2

25V

C4
200

50V

D4
MBR745

C5
500

25V

5V
5A

C6
0.01

1421 F22

PC BOARD

BACKPLANE

24V

POR

FAULT

R5
10k
1/2W

R9
2.7k

R6
620

1/8W

R2
15k
1/8W

R7
2.8k
1%

R8
2.21k
1%

LT1074CT

GND

LTC1421

STAGGERED CONNECTOR

4N25

10A

1421 F21

VICOR

VI-J30-CY

GATE IN

D1
4.3V

0.1

10k

300

100

1N4148

4.5k

PC BOARD

BACKPLANE

48V

0.1

100

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

LTC1421

STAGGERED CONNECTOR

16V

220

16V

0.1

16V

1N4148

MTD20N03HL

S1: HARD POWER/CIRCUIT BREAKER RESET

S2: SOFT RESET

LTC1430 POWER-UP THRESHOLD: 4.8V ON 4.25V OFF

1421 F23

PC BOARD

BACKPLANE

0.005

5%,1W

0.1

16V

LTC1430CS8

CC1

COMP

SHDN

GND

510

100k

0.01

5%,1W

MTD20N03HL

220pF

CERAMIC

4700pF

CERAMIC

0.1

16V

C10

16V

26.7k

R10

10k

7.5k

10k

338

10V

2.7

15A

RESET

3.3V

10A

MAX

= 15A

GND

Figure 23. 5V to 3.3V Hot Swappable Supply Using the LTC1430CS8

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

0.005

MTB50N06E

LTC1421

FAULT

IRF530

C1
1

STAGGERED CONNECTOR

C7
100

16V

5V
8A

12V
0.42A

1421 F24

ASTRODYNE

ASD10-48D12

CONTROL

+IN

+OUT

OUT

C2
1

C5
220

100V

340

1/8W

R4
10k
1/8W

R5
4.3k
1/8W

R6
15k
1/8W

C3
0.47

R7
1k
1/8W

C4
2200

16V

C6
100

16V

PC BOARD

BACKPLANE

48V

Q3
2N5401

Figure 24. 5V and 48V to

12V Hot Swappable Supply

7
8
14
13
15

LTC1421

Q3
VN2222

C2
0.1

C1
1

STAGGERED CONNECTOR

2200

16V

100

0.005

1/2W

MTB50N06E

VN2222

1421 F25

PC BOARD

BACKPLANE

R4
10k

R3
47.5k

5V
8A

RESET

GND

Figure 25. Hot Swappable 5V Supply with Overvoltage Protection

LTC1421/LTC1421-2.5

APPLICATIO

S I

FOR

ATIO

G Package

24-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

Dimensions in inches (millimeters) unless otherwise noted.

PACKAGE DESCRIPTIO

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

S24 (WIDE) 0996

NOTE 1

0.598 0.614*

(15.190 15.600)

0.394 0.419

(10.007 10.643)

0.037 0.045

(0.940 1.143)

0.004 0.012

(0.102 0.305)

0.093 0.104

(2.362 2.642)

0.050

(1.270)

TYP

0.014 0.019

(0.356 0.482)

TYP

NOTE 1

0.009 0.013

(0.229 0.330)

0.016 0.050

(0.406 1.270)

0.291 0.299**

(7.391 7.595)

0.010 0.029

(0.254 0.737)

NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

G24 SSOP 0595

0.068 0.078

(1.73 1.99)

0.002 0.008

(0.05 0.21)

0.0256

(0.65)

BSC

0.010 0.015

(0.25 0.38)

0.301 0.311

(7.65 7.90)

2 3

6 7 8

9 10 11 12

0.318 0.328*

(8.07 8.33)

18 17 16 15 14 13

0.005 0.009

(0.13 0.22)

0.022 0.037

(0.55 0.95)

0.205 0.212**

(5.20 5.38)

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

SW Package

24-Lead Plastic Small Outline (Wide 0.300)

(LTC DWG # 05-08-1620)

Figure 26. Power-Up and Power-Down Sequence Controller

10
11
6
7
8
14
13
15
9

LTC1421

C2
0.1

24V

C1
1

16V

0.047

STAGGERED CONNECTOR

C4
2200

16V

C5
0.1

24V

0.005

R3
1M
5%,1/8W

MTB50N06E

1421 F26

PC BOARD

BACKPLANE

R6
200k
5%
1/16W

R5
330k
5%
1/16W

3V
8A

5V
8A

0.005

C4
2200

16V

RESET

GND

R4
1k
5%
1/16W

LTC1421/LTC1421-2.5

LINEAR TECHNOLOGY CORPORATION 1996

142125fa LT/TP 1098 2K REV A · PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear-tech.com

TYPICAL APPLICATIO

LTC1421

1/2 IRF7101

PCI

CONNECTOR

Q1
IRF7413

R11
10

C2
0.22

24V

R4
30

IRF7413

12V
3.3A CIRCUIT BREAKER

3.3V
11.5A CIRCUIT BREAKER

5V
10A CIRCUIT BREAKER

R10
100k

R13
5.1k

20k

R12
10

16V

0.005

1/2W

R14
5.1k

0.015

5%
1W

R8
5.62k
1%
1/16W

0.005

5%
1W

POWER GOOD

RST #

SELECT BITS

BUS ENABLE

FAULT

12V

500mA

3.3V
7.5A

5V
5A

ON/OFF

DATA BUS

12V

100mA

PCI POWER

CONTROLLER

QuickSwitch

R7
130k

R9
10

Q5
TP0610T

C3
1

24V

R6
100

1%
1/16W

12V
NO CIRCUIT BREAKER

GND

1421 F27

ALL RESISTORS 5%, 1/16W EXCEPT WHERE NOTED

RST #

LOGIC

PCI PERIPHERAL

MOTHERBOARD OR BACKPLANE

Figure 27. PCI Power Controller

PART NUMBER

DESCRIPTION

COMMENTS

LTC1155

Dual High Side Switch Driver

Short-Circuit Protection and Micropower Standby Operation

LTC1477/LTC1478

Single and Dual Protected High Side Switches

Inrush Current Limited, Built-In 2A Short-Circuit Protection

RELATED PARTS

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1421

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1421