IT8761E
Legacy Low Pin Count I/O
(Code Name: Humming Bird)
Preliminary Specification V0.3
Copyright
2000 ITE, Inc.
This is Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous documentation issued for the related products
included herein. Please contact ITE, Inc. for the latest document(s).
All sales are subject to ITE
'
s Standard Terms and Conditions, a copy of which is included in the back of this
document.
ITE and IT8761E are trademarks of ITE, Inc.
Intel, LPC are claimed as trademarks by Intel Corp.
Microsoft is claimed as a trademark by Microsoft Corporation.
PCI
TM
is a registered trademark of PCI Special Interest Group.
All trademarks are the properties of their respective owners.
All specifications are subject to change without notice.
Additional copies of this manual or other ITE literature may be obtained from:
ITE (USA) Inc.
Phone: (408) 530-8860
Marketing Department
Fax:
(408) 530-8861
1235 Midas Way
Sunnyvale, CA 94086
U.S.A.
ITE (USA) Inc.
Phone: (512) 388-7880
Eastern U.S.A. Sales Office
Fax:
(512) 388-3108
896 Summit St., #105
Round Rock, TX 78664
U.S.A.
ITE, Inc.
Phone: (02) 2657-9896
Marketing Department
Fax:
(02) 2657-8561, 2657-8576
7F, No. 435, Nei Hu District, Jui Kuang Road,
Taipei 114, Taiwan, R.O.C.
If you have any marketing or sales questions, please contact:
Lawrence Liu, at ITE Taiwan: E-mail: lawrence.liu@ite.com.tw, Tel: 886-2-26579896 X6071,
Fax: 886-2-26578561
David Lin, at ITE U.S.A: E-mail: david.lin@iteusa.com, Tel: (408) 980-8168 X238,
Fax: (408) 980-9232
Don Gardenhire, at ITE Eastern USA Office: E-mail: don.gardenhire@iteusa.com,
Tel: (512) 388-7880, Fax: (512) 388-3108
To find out more about ITE, visit our World Wide Web at:
http://www.iteusa.com
http://www.ite.com.tw
Or e-mail itesupport@ite.com.tw for more product information/services.
IT8761E
Revision History
Section
Revision
Page No.
1
l
In the features of Keyboard Controller, the 5
th
feature item in the previous
version was removed.
1-1
6
l
In section 6.3.2.5 KBC Special Configuration Register, the bits 7-5 were
revised to "Reserved".
6-11
IT8761E
i
CONTENTS
Page
1. Features ..................................................................................................................................................... 1-1
2. General Description................................................................................................................................... 1-1
3. Pin Configuration ...................................................................................................................................... 3-1
4. Pin Description .......................................................................................................................................... 4-1
5. Functional Description.............................................................................................................................. 5-1
5.1 Reset Strapping Options....................................................................................................................... 5-1
5.2 LPC Interface ....................................................................................................................................... 5-1
5.2.1 Overview ..................................................................................................................................... 5-1
5.2.2 LPC Transactions ........................................................................................................................ 5-1
5.2.3 LPC I/F Block Diagram ................................................................................................................ 5-2
5.3 GPIO.................................................................................................................................................... 5-3
5.4 Testability............................................................................................................................................. 5-4
6. Register Description.................................................................................................................................. 6-1
6.1 Standard ISA Plug-and-Play (PnP) High Level Register Map................................................................ 6-1
6.2 Global Configuration Register Set Description...................................................................................... 6-4
6.3 PnP Configuration Registers Description .............................................................................................. 6-6
6.3.1 IT8761E Global PnP Registers .................................................................................................... 6-6
6.3.1.1 Configure Control Register .......................................................................................................... 6-6
6.3.1.2 Logical Device Number Register.................................................................................................. 6-6
6.3.1.3 Chip ID Number Register ............................................................................................................ 6-6
6.3.1.4 Chip Version Number Register .................................................................................................... 6-7
6.3.1.5 LPC to X-bus PIO Timing Register .............................................................................................. 6-7
6.3.1.6 LPC to X-bus DMA Timing Register............................................................................................. 6-7
6.3.1.7 Chip Test Mode Enable Register ................................................................................................. 6-8
6.3.1.8 Other registers not listed above with index between 00h~2Fh ...................................................... 6-8
6.3.2 IT8761E KBC PnP Registers (LDN=00h) ..................................................................................... 6-9
6.3.2.1 KBC Function Enable Control Register ........................................................................................ 6-9
6.3.2.2 KBC Module Base Address Registers .......................................................................................... 6-9
6.3.2.3 KBC Interrupt Control Register ...................................................................................................6-10
6.3.2.4 KBC Interrupt Type Register.......................................................................................................6-10
6.3.2.5 KBC Special Configuration Register ...........................................................................................6-11
6.3.2.6 Emulated KBC Host Interface Control Register...........................................................................6-12
6.3.3 IT8761E UART PnP Registers (LDN=01h) ................................................................................. 6-13
6.3.3.1 UART Module Base Address Registers.......................................................................................6-13
6.3.3.2 UART Interrupt Control Register.................................................................................................6-13
6.3.3.3 UART Interrupt Type Register ....................................................................................................6-14
6.3.3.4 UART Special Configuration Register .........................................................................................6-14
6.3.4 IT8761E GPIO PnP Registers (LDN=02h).................................................................................. 6-15
6.3.4.1 GPIO Module Base Address Registers .......................................................................................6-15
6.3.4.2 GPIO Interrupt Control Register .................................................................................................6-15
6.3.4.3 GPIO Interrupt Type Register .....................................................................................................6-16
IT8761E
ii
6.3.4.4 GPIO Input / Output Selection Registers ....................................................................................6-16
6.3.4.5 GPIO Input Interrupt Mask Registers..........................................................................................6-17
6.3.4.6 GPIO Interrupt Trigger Edge Registers .......................................................................................6-17
6.3.4.7 GPIO De-bounce Register..........................................................................................................6-18
6.3.4.8 GPIO Blinking Register ..............................................................................................................6-18
6.3.4.9 Software Interrupt Registers .......................................................................................................6-19
6.3.4.10 GPIO Special Configuration Register..........................................................................................6-21
6.3.5 IT8761E FDC PnP Registers (LDN=03h) ................................................................................... 6-22
6.3.5.1 FDC Function Enable Control Register .......................................................................................6-22
6.3.5.2 FDC Module Base Address Registers .........................................................................................6-22
6.3.5.3 FDC Interrupt Control Register ...................................................................................................6-22
6.3.5.4 FDC Interrupt Type Register.......................................................................................................6-23
6.3.5.5 FDC DMA Channel Register.......................................................................................................6-23
6.3.5.6 FDC Special Configuration Register 1......................................................................................6-24
6.3.5.7 FDC Special Configuration Register - 2 ......................................................................................6-24
6.3.6 IT8761E Mouse PnP Registers (LDN=04h) ................................................................................ 6-25
6.3.6.1 Mouse Function Enable Control Register....................................................................................6-25
6.3.6.2 Mouse Interrupt Control Register................................................................................................6-25
6.3.6.3 Mouse Interrupt Type Register....................................................................................................6-26
6.3.6.4 Mouse Special Configuration Register ........................................................................................6-26
6.4 GPIO Functional Registers Description .............................................................................................. 6-27
7. Characteristics........................................................................................................................................... 7-1
7.1 DC Electrical Characteristics ................................................................................................................ 7-1
7.2 AC Characteristics................................................................................................................................ 7-3
7.3 Waveform ............................................................................................................................................ 7-4
8. Package Information ................................................................................................................................. 8-1
9. Ordering Information................................................................................................................................. 9-1
FIGURES
Figure 2-1. IC Block Diagram............................................................................................................................ 2-1
Figure 3-1. IT8761E Pin Diagram (Top View).................................................................................................... 3-1
Figure 5-1. LPC Interface ................................................................................................................................. 5-2
Figure 5-2. Logic Diagrams of GPIO1X and GPIO2X........................................................................................ 5-3
Figure 6-1. ISA PnP Register Map.................................................................................................................... 6-1
Figure 6-2. IT8761E PnP Entry/Exit Sequence ................................................................................................. 6-5
PDF 
ZIP