Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. G
04/26/01
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.
IS93C46-3
ISSI
1,024-BIT SERIAL ELECTRICALLY
ERASABLE PROM
OVERVIEW
The IS93C46-3 is a low cost 1,024-bit, non-volatile, serial
E
2
PROM. It is fabricated using
ISSI's
advanced CMOS
E
2
PROM technology. The IS93C46-3 provides efficient
non-volatile read/write memory arranged as 64 registers
of 16 bits each. Seven 9-bit instructions control the
operation of the device, which includes read, write, and
mode enable functions. The data out pin (D
OUT
) indicates
the status of the device during in the self-timed non-
volatile programming cycle.
The self-timed write cycle includes an automatic erase-
before-write capability. To protect against inadvertent
writes, the WRITE instruction is accepted only while the
chip is in the write enabled state. Data is written in 16 bits
per write instruction into the selected register. If Chip
Select (CS) is brought HIGH after initiation of the write
cycle, the Data Output (D
OUT
) pin will indicate the READY/
BUSY
status of the chip.
APPLICATIONS
The IS93C46-3 is ideal for high-volume applications
requiring low power and low density storage. This device
uses a low cost, space saving 8-pin package. Candidate
applications include robotics, alarm devices, electronic
locks, meters and instrumentation settings.
MARCH 2001
FUNCTIONAL BLOCK DIAGRAM
FEATURES
State-of-the-art architecture
-- Non-volatile data storage
-- Low voltage operation:
3.0V (Vcc = 2.7V to 6.0V)
-- Full TTL compatible inputs and outputs
-- Auto increment for efficient data dump
Low voltage read operation
-- Down to 2.7V
Hardware and software write protection
-- Defaults to write-disabled state at power-up
-- Software instructions for write-enable/disable
Advanced low voltage CMOS E
2
PROM
technology
Versatile, easy-to-use Interface
-- Self-timed programming cycle
-- Automatic erase-before-write
-- Programming status indicator
-- Word and chip erasable
-- Stop SK anytime for power savings
Durable and reliable
-- 10-year data retention after 100K write cycles
-- 100,000 write cycles
-- Unlimited read cycles
CS
SK
D
IN
D
OUT
DUMMY
BIT
R/W
AMPS
DATA
REGISTER
(16 BITS)
ADDRESS
REGISTER
1 OF 64
DECODER
WRITE
ENABLE
HIGH VOLTAGE
GENERATOR
INSTRUCTION
DECODE,
CONTROL,
AND
CLOCK
GENERATION
INSTRUCTION
REGISTER
(9 BITS)
EEPROM
ARRAY
(64 X 16)
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. G
04/26/01
IS93C46-3
ISSI
PIN CONFIGURATION
8-Pin DIP
1
2
3
4
8
7
6
5
CS
SK
D
IN
D
OUT
VCC
NC
NC
GND
PIN CONFIGURATION
8-Pin JEDEC Small Outline "G"
PIN CONFIGURATION
8-Pin JEDEC Small Outline "GR"
1
2
3
4
8
7
6
5
NC
VCC
CS
SK
NC
GND
D
OUT
D
IN
1
2
3
4
8
7
6
5
CS
SK
D
IN
D
OUT
VCC
NC
NC
GND
PIN DESCRIPTIONS
CS
Chip Select
SK
Serial Data Clock
D
IN
Serial Data Input
D
OUT
Serial Data Output
NC
Not Connected
Vcc
Power
GND
Ground
Low Voltage Read
The IS93C46-3 has been designed to ensure that data
read operations are reliable in low voltage environments.
The IS93C46-3 is guaranteed to provide accurate data
during read operations with Vcc as low as 2.7V.
Auto Increment Read Operations
In the interest of memory transfer operation applications,
the IS93C46-3 has been designed to output a continuous
stream of memory content in response to a single read
operation instruction. To utilize this function, the system
asserts a read instruction specifying a start location
address. Once the 16 bits of the addressed word have
been clocked out, the data in consecutively higher address
locations (the address "000000" is assumed as the ad-
dress of "111111") is output. The address will wrap around
continuously with CS HIGH until the chip select (CS)
control pin is brought LOW. This allows for single instruction
data dumps to be executed with a minimum of firmware
overhead.
Write Enable (WEN)
The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL, ERASE,
and ERAL) can be done. When Vcc is applied, this device
ENDURANCE AND DATA RETENTION
The IS93C46-3 is designed for applications requiring up to
100,000 programming cycles (WRITE, WRALL, ERASE
and ERAL). It provides 10 years of secure data retention,
without power after the execution of 100,000 programming
cycles.
DEVICE OPERATION
The IS93C46-3 is controlled by seven 9-bit instructions.
Instructions are clocked in (serially) on the D
IN
pin. Each
instruction begins with a logical "1" (the start bit). This is
followed by the opcode (2 bits), the address field (6 bits),
and data, if appropriate. The clock signal (SK) may be
halted at any time and the IS93C46-3 will remain in its last
state. This allows full static flexibility and maximum
power conservation.
Read (READ)
The READ instruction is the only instruction that outputs
serial data on the D
OUT
pin. After the read instruction and
address have been decoded, data is transferred from the
selected memory register into a 16-bit serial shift register.
(Please note that one logical "0" bit precedes the actual
16-bit output data string.) The output on D
OUT
changes
during the low-to-high transitions of SK (see Figure 3).
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
Rev. G
04/26/01
IS93C46-3
ISSI
becomes a sequence of "Don't Care" bits (see Figure 6).
As with the WRITE instruction, if CS is brought HIGH after
a minimum wait of 250 ns (t
CS
), the D
OUT
pin indicates the
READY/
BUSY
status of the chip (see Figure 6).
Write Disable (WDS)
The write disable (WDS) instruction disables all programming
capabilities. This protects the entire part against acciden-
tal modification of data until a WEN instruction is exe-
cuted. (When Vcc is applied, this part powers up in the
write disabled state.) To protect data, a WDS instruction
should be executed upon completion of each programming
operation. (NOTE: Neither the WEN nor the WDS instruction
has any effect on the READ instruction.) (See Figure 7.)
Erase Register (ERASE)
After the erase instruction is entered, CS must be brought
LOW. The falling edge of CS initiates the self-timed
internal programming cycle. Bringing CS HIGH after a
minimum of t
CS
, will cause D
OUT
to indicate the READ/
BUSY
status of the chip: a logical "0" indicates programming is
still in progress; a logical "1" indicates the erase cycle is
complete and the part is ready for another instruction (see
Figure 8).
Erase All (ERAL)
Full chip erase is provided for ease of programming.
Erasing the entire chip involves setting all bits in the entire
memory array to a logical "1" (see Figure 9).
powers up in the write disabled state. The device then
remains in a write disabled state until a WEN instruction
is executed. Thereafter, the device remains enabled until
a WDS instruction is executed or until Vcc is removed.
(NOTE: Neither the WEN nor the WDS instruction has any
effect on the READ instruction.) (See Figure 4.)
Write (WRITE)
The WRITE instruction includes 16 bits of data to be
written into the specified register. After the last data bit
has been applied to D
IN
, and before the next rising edge of
SK, CS must be brought LOW. The falling edge of CS
initiates the self-timed programming cycle.
After a minimum wait of 250 ns (5V operation) from the
falling edge of CS (t
CS
), if CS is brought HIGH, D
OUT
will
indicate the READY/
BUSY
status of the chip: logical "0"
means programming is still in progress; logical "1" means
the selected register has been written, and the part is
ready for another instruction (see Figure 5). (NOTE: The
combination of CS HIGH, D
IN
HIGH and the rising edge of
the SK clock, resets the READY/
BUSY
flag. Therefore, it
is important if you want to access the READY/
BUSY
flag
, not to reset it through this combination of control
signals.) Before a WRITE instruction can be executed, the
device must be write enabled (see WEN).
Write All (WRALL)
The write all (WRALL) instruction programs all registers
with the data pattern specified in the instruction. While the
WRALL instruction is being loaded, the address field
INSTRUCTION SET
Instruction
Start Bit
OP Code
Address
Input Data
READ
1
10
(A5-A0)
WEN
1
00
11XXXX
(Write Enable)
WRITE
1
01
(A5-A0)
D15-D0
(1)
WRALL
1
00
01XXXX
D15-D0
(1)
(Write All Registers)
WDS
1
00
00XXXX
(Write Disable)
ERASE
1
11
(A5-A0)
ERAL
1
00
10XXXX
(Erase All Registers)
Note: 1. If input data is not 16 bits exactly, the last 16 bits will be taken as input data (a word).
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. G
04/26/01
IS93C46-3
ISSI
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
GND
Voltage with Respect to GND
0.3 tp +6.5
V
T
BIAS
Temperature Under Bias (IS93C46-3)
0 to +70
C
T
BIAS
Temperature Under Bias (IS93C46-3I)
40 to +85
C
T
STG
Storage Temperature
65 to +125
C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5
pF
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0C to +70C
2.7V to 6.0V
Industrial
40C to +85C
2.7V to 6.0V
FIGURE 1. AC TEST CONDITIONS
800
100 pF
+2.08V
D
OUT
Vcc = 5.0V
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. G
04/26/01
IS93C46-3
ISSI
DC ELECTRICAL CHARACTERISTICS
T
A
= 0C to +70C for IS93C46-3 and 40C to +85C for IS93C46-3I.
Symbol
Parameter
Test Conditions
Vcc
Min.
Max.
Unit
V
OL
Output LOW Voltage
I
OL
= 10 A CMOS
2.7V to 3.3V
--
0.2
V
V
OL1
Output LOW Voltage
I
OL
= 2.1 mA TTL
4.5V to 5.5V
--
0.4
V
V
OH
Output HIGH Voltage
I
OH
= 10 A CMOS
2.7V to 3.3V
V
CC
0.2
--
V
V
OH1
Output HIGH Voltage
I
OH
= 400 A TTL
4.5V to 5.5V
2.4
--
V
V
IH
Input HIGH Voltage
2.7V to 3.3V
2.4
V
CC
V
4.5V to 5.5V
2
V
CC
V
IL
Input LOW Voltage
2.7V to 3.3V
0.1
0.6
V
4.5V to 5.5V
0.1
0.8
I
LI
Input Leakage
V
IN
= 0V to V
CC
(CS, SK, D
IN
)
1
1
A
I
LO
Output Leakage
V
OUT
= 0V to V
CC
, CS = 0V
1
1
A
POWER SUPPLY CHARACTERISTICS
T
A
= 0C to +70C for IS93C46-3 and 40C to +85C for IS93C46-3I.
IS93C46-3
IS93C46-3I
Symbol Parameter
Test Conditions
Vcc
Min. Typ. Max.
Min. Typ. Max.
Unit
I
CC
Vcc Operating
CS = V
IH
, SK = 500 KHz
2.7V to 3.3V
--
0.5
2
--
0.5
2
mA
Supply Current
CMOS Input Levels
I
CC
Vcc Operating
CS = V
IH
, SK = 1 MHz
4.5V to 5.5V
--
4
6
--
4
6
mA
Supply Current
CMOS Input Levels
I
SB
Standby Current
CS = D
IN
= SK = 0V
2.7V to 3.3V
--
2
10
--
2
10
A
4.5V to 5.5V
--
10
50
--
10
50
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