Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. B
04/14/05
IS41LV16100B
ISSI
Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
TTL compatible inputs and outputs; tristate I/O
Refresh Interval:
-- Auto refresh Mode: 1,024 cycles /16 ms
--
RAS
-Only,
CAS
-before-
RAS
(CBR), and Hidden
JEDEC standard pinout
Single power supply: 3.3V 10%
Byte Write and Byte Read operation via two
CAS
Industrial Temperature Range: -40
o
C to +85
o
C
Lead-free available
DESCRIPTION
The
ISSI
IS41LV16100B is 1,048,576 x 16-bit high-perfor-
mance CMOS Dynamic Random Access Memories. These
devices offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 1,024 random ac-
cesses within a single row with access cycle time as short
as 20 ns per 16-bit word.
These features make the IS41LV16100B ideally suited for
high-bandwidth graphics, digital signal processing, high-
performance computing systems, and peripheral
applications.
The IS41LV16100B is packaged in a 42-pin 400-mil SOJ
and 400-mil 50- (44-) pin TSOP (Type II).
1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
KEY TIMING PARAMETERS
Parameter
-50
-60
Unit
Max.
RAS
Access Time (t
RAC
)
50
60
ns
Max.
CAS
Access Time (t
CAC
)
14
15
ns
Max. Column Address Access Time (t
AA
)
25
30
ns
Min. EDO Page Mode Cycle Time (t
PC
)
30
40
ns
Min. Read/Write Cycle Time (t
RC
)
85
110
ns
PIN CONFIGURATIONS
50(44)-Pin TSOP (Type II)
42-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9
Address Inputs
I/O0-15
Data Inputs/Outputs
WE
Write Enable
OE
Output Enable
RAS
Row Address Strobe
UCAS
Upper Column Address Strobe
LCAS
Lower Column Address Strobe
V
DD
Power
GND
Ground
NC
No Connection
APRIL 2005
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
IS41LV16100B
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. B
04/13/05
ISSI
Functional Description
The IS41LV16100B is a CMOS DRAM optimized for high-
speed bandwidth, low power applications. During READ or
WRITE cycles, each bit is uniquely addressed through the
16 address bits. These are entered ten bits (A0-A9) at time.
The row address is latched by the Row Address Strobe
(
RAS
). The column address is latched by the Column
Address Strobe (
CAS
).
RAS
is used to latch the first nine bits
and
CAS
is used to latch the latter nine bits.
The IS41LV16100B has two
CAS
controls,
LCAS
and
UCAS
.
The
LCAS
and
UCAS
inputs internally generates a
CAS
signal
functioning in an identical manner to the single
CAS
input on
the other 1M x 16 DRAMs. The key difference is that each
CAS
controls its corresponding I/O tristate logic (in conjunction with
OE
and
WE
and
RAS
).
LCAS
controls I/O0 through I/O7 and
UCAS
controls I/O8 through I/O15.
The IS41LV16100B
CAS
function is determined by the first
CAS
(
LCAS
or
UCAS
) transitioning LOW and the last
transitioning back HIGH. The two
CAS
controls give the
IS41LV16100B both BYTE READ and BYTE WRITE cycle
capabilities.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The column
address must be held for a minimum time specified by t
AR
.
Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE
, whichever occurs first.
Auto Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0 through A9)
with
RAS
at least once every 128 ms. Any read, write, read-
modify-write or
RAS
-only cycle refreshes the addressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
,
while holding
CAS
LOW. In
CAS
-before-
RAS
refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns within
a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycle's falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS
cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the
CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS
cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the V
DD
supply, an initial pause of
200 s is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
DD
or be held at a valid V
IH
to avoid current surges.
IS41LV16100B
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. B
04/13/05
ISSI
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameters
Rating
Unit
V
T
Voltage on Any Pin Relative to GND
3.3V
0.5 to +4.6
V
V
DD
Supply Voltage
3.3V
0.5 to +4.6
V
I
OUT
Output Current
50
mA
P
D
Power Dissipation
1
W
T
A
Commercial Operation Temperature
0 to +70
C
Industrial Operation Temperature
-40 to +85
C
T
STG
Storage Temperature
55 to +125
C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Supply Voltage
3.3V
3.0
3.3
3.6
V
V
IH
Input High Voltage
3.3V
2.0
--
V
DD
+ 0.3
V
V
IL
Input Low Voltage
3.3V
0.3
--
0.8
V
T
A
Commercial Ambient Temperature
0
--
70
C
Industrial Ambient Temperature
40
--
85
C
CAPACITANCE
(1,2)
Symbol
Parameter
Max.
Unit
C
IN
1
Input Capacitance: A0-A9
5
pF
C
IN
2
Input Capacitance:
RAS
,
UCAS
,
LCAS
,
WE
,
OE
7
pF
C
IO
Data Input/Output Capacitance: I/O0-I/O15
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz.
PDF 
ZIP
