6-56
Features
Industry Standard Pinout
Very Low Operating Current . . . . . . . . . . . . . . . . . . 8mA
at V
DD
= 5V and Cycle Time = 1
s
Two Chip Select Inputs Simple Memory Expansion
Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)
Battery Voltage
Output Disable for Common I/O Systems
Three-State Data Output for Bus Oriented Systems
Separate Data Inputs and Outputs
TTL Compatible (MWS5101A)
Pinout
MWS5101, MWS5101A
(PDIP, SBDIP)
TOP VIEW
Description
The MWS5101 and MWS5101A are 256 word by 4-bit static
random access memories designed for use in memory
systems where high speed, very low operating current, and
simplicity in use are desirable. They have separate data
inputs and outputs and utilize a single power supply of 4V to
6.5V. The MWS5101 and MWS5101A differ in input voltage
characteristics (MWS5101A is TTL compatible).
Two Chip Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems by forcing the output into a high impedance state
during a write operation independent of the Chip Select input
condition. The output assumes a high impedance state
when the Output Disable is at high level or when the chip is
deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
For applications requiring wider temperature and operating
voltage ranges, the mechanically and functionally equivalent
static RAM, CDP1822 may be used.
The MWS5101 and MWS5101A types are supplied in 22
lead hermetic dual-in-line, sidebrazed ceramic packages (D
suffix), in 22 lead dual-in-line plastic packages (E suffix), and
in chip form (H suffix).
Ordering Information
1
11
10
9
8
7
6
5
3
2
4
22
12
13
14
15
16
17
18
19
21
20
A2
A1
A0
A5
A6
A7
DI1
V
SS
DO1
DI2
A4
CSI
O.D.
CS2
R/W
DO4
DI4
DO3
DI3
DO2
A3
V
DD
PACKAGE
TEMP. RANGE
MWS5101
350ns
MWS5101A
350ns
PKG. NO.
250ns
250ns
PDIP
Burn-In
0
o
C to +70
o
C
MWS5101EL2
MWS5101ELS
MWS5101AEL2
MWS5101AEL3
E22.4
MWS5101AEL3X E22.4
SBDIP
Burn-In
0
o
C to +70
o
C
-
MWS5101DL3X
-
MWS5101ADL3
D22.4A
D22.4A
March 1997
MWS5101,
MWS5101A
256-Word x 4-Bit
LSI Static RAM
File Number
1106.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
6-57
Functional Block Diagram
OPERATIONAL MODES
MODE
INPUTS
OUTPUT
CHIP SELECT 1
(CS
1
)
CHIP SELECT 2
(CS
2
)
OUTPUT
DISABLE (OD)
READ/WRITE
(R/W)
Read
0
1
0
1
Read
Write
0
1
0
0
Data In
Write
0
1
1
0
High Impedance
Standby
1
X
X
X
High Impedance
Standby
X
0
X
X
High Impedance
Output Disable
X
X
1
X
High Impedance
NOTE: Logic 1 = High, Logic 0 = Low, X = Don't Care.
(8 x 32)
STORAGE
ARRAY
(5)
INPUT
BUFFERS
AND
ALL ROWS
DESELECT
FUNCTION
A0
A1
A2
A3
A4
21
1
2
3
4
(4)
GATES
DI1
DI2
DI3
DI4
15
13
11
9
(3)
INPUT
BUFFERS
AND
ALL COLUMNS
DESELECT
FUNCTION
A5
A6
A7
7
6
5
CSI
CS2
INPUT PROTECTION
18
17
19
CONTROL
A
CONTROL
C
CONTROL
B
(32)
ROW
DECODERS
BIT (1)
(8 x 32)
STORAGE
ARRAY
BIT (2)
(8 x 32)
STORAGE
ARRAY
BIT (3)
(8 x 32)
STORAGE
ARRAY
BIT (4)
BUFFER
DRIVERS
(4)
D01
D02
D03
D04
16
14
12
10
BITS
(1-4)
(8)
COLUMN
DECODERS
(8)
COLUMN
DECODERS
(8)
COLUMN
DECODERS
(8)
COLUMN
DECODERS
22
V
DD
R/W
20
8
V
SS
OUTPUT
NETWORK
PROTECTION
CIRCUIT
OVER VOLTAGE
PROTECTION
CIRCUIT
V
SS
V
SS
V
SS
OD
V
DD
V
DD
V
DD
MWS5101, MWS5101A
6-58
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (V
DD
)
(All Voltages Referenced to V
SS
Terminal) . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
DD
+0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . . .
10mA
Thermal Resistance (Typical)
JA
(
o
C/W)
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
75
N/A
SBDIP Package . . . . . . . . . . . . . . . . . .
80
21
Operating Temperature Range (T
A
)
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55
o
C to +125
o
C
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40
o
C to +85
o
C
Maximum Storage Temperature Range (T
STG
) . . .-65
o
C to +150
o
C
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150
o
C
Maximum Lead Temperature (During Soldering)
At distance 1/16
1/32 In. (1.59
0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265
o
C
Recommended Operating Conditions
At T
A
= Full Package Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges:
PARAMETER
LIMITS
UNITS
MIN
MAX
DC Operating Voltage Range
4
6.5
V
Input Voltage Range
V
SS
V
DD
V
Static Electrical Specifications
At T
A
= 0
o
C to +70
o
C, V
DD
= 5V
5%
PARAMETER
SYMBOL
CONDITIONS
LIMITS
UNITS
V
O
(V)
V
IN
(V)
MWS5101
MWS5101A
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
Quiescent Device
Current
L2 Types
I
DD
-
0, 5
-
25
50
-
25
50
A
L3 Types
-
0, 10
-
100
200
-
100
200
A
Output Low (Sink) Current
I
OL
0.4
0, 5
2
4
-
2
4
-
mA
Output High (Source) Current
I
OH
4.6
0, 5
-1
-2
-
-1
-2
-
mA
Output Voltage Low-Level
V
OL
-
0, 5
-
0
0.1
-
0
0.1
V
Output Voltage High-Level
V
OH
-
0, 5
4.9
5
-
4.9
5
-
V
Input Low Voltage
V
IL
-
-
-
-
1.5
-
-
0.65
V
Input High Voltage
V
IH
-
-
3.5
-
-
2.2
-
-
V
Input Leakage Current
I
IN
-
0, 5
-
-
5
-
-
5
A
Operating Current (Note 2)
I
DD1
-
0, 5
-
4
8
-
4
8
mA
Three-State Output
Leakage Current
L2 Types
I
OUT
0, 5
0, 5
-
-
5
-
-
5
A
L3 Types
0, 5
0, 5
-
-
5
-
-
5
A
Input Capacitance
C
IN
-
-
-
5
7.5
-
5
7.5
pF
Output Capacitance
C
OUT
-
-
-
10
15
-
10
15
pF
NOTES:
1. Typical values are for T
A
= +25
o
C and nominal V
DD
.
2. Outputs open circuited; Cycle time = 1
s.
MWS5101, MWS5101A
6-59
Dynamic Electrical Specifications
at T
A
= 0
o
C to +70
o
C, V
DD
= 5V
5%
PARAMETER
SYMBOL
LIMITS (NOTE 1)
UNITS
L2 TYPES
L3 TYPES
(NOTE 2)
MIN
(NOTE 3)
TYP
MAX
(NOTE 2)
MIN
(NOTE 3)
TYP
MAX
READ CYCLE TIMES (FIGURE 1)
Read Cycle
t
RC
250
-
-
350
-
-
ns
Access from Address
t
AA
-
150
250
-
200
350
ns
Output Valid from Chip Select 1
t
DOA1
-
150
250
-
200
350
ns
Output Valid from Chip Select 2
t
DOA2
-
150
250
-
200
350
ns
Output Valid from Output Disable
t
DOA3
-
-
110
-
-
150
ns
Output Hold from Chip Select 1
t
DOH1
20
-
-
20
-
-
ns
Output Hold from Chip Select 2
t
DOH2
20
-
-
20
-
-
ns
Output Hold from Output Disable
t
DOH3
20
-
-
20
-
-
ns
WRITE CYCLE TIMES (FIGURE 2)
Write Cycle
t
WC
300
-
-
400
-
-
ns
Address Setup
t
AS
110
-
-
150
-
-
ns
Write Recovery
t
WR
40
-
-
50
-
-
ns
Write Width
t
WRW
150
-
-
200
-
-
ns
Input Data Setup Time
t
DS
150
-
-
200
-
-
ns
Data in Hold
t
DH
40
-
-
50
-
-
ns
Chip Select 1 Setup
t
CS1S
110
-
-
150
-
-
ns
Chip Select 2 Setup
t
CS2S
110
-
-
150
-
-
ns
Chip Select 1 Hold
t
CS1H
0
-
-
0
-
-
ns
Chip Select 2 Hold
t
CS2H
0
-
-
0
-
-
ns
Output Disable Setup
t
ODS
110
-
-
150
-
-
ns
NOTES:
1. MWS5101: t
R
, t
F
= 20ns, V
IH
= 0.7V
DD
, V
IL
= 0.3V
DD
; C
L
= 100pF and MWS5101A: t
R
, t
F
= 20ns, V
IH
= 2.2V, V
IL
= 0.65V; C
L
= 50pF
and 1 TTL Load.
2. Time required by a limit device to allow for the indicated function.
3. Typical values are for T
A
= 25
o
C and nominal V
DD.
MWS5101, MWS5101A
6-60
t
DOA1
t
DOA2
t
DOH1
t
RC
t
DOH3
t
AA
DATA OUT
VALID
HIGH
IMPEDANCE
HIGH
IMPEDANCE
CHIP SELECT 1
A0 - A7
CHIP SELECT 2
OUTPUT DISABLE
READ/WRITE
DATA OUT
t
DOH2
t
DOA3
FIGURE 1. READ CYCLE TIMING WAVEFORMS
A0-A7
t
WC
t
CS1S
t
CS1H
t
CS2S
t
CS2H
t
ODS
t
DS
t
DH
t
WRW
t
AS
DON'T CARE
CHIP SELECT 1
CHIP SELECT 2
OUTPUT DISABLE
DI1-DI4
READ/WRITE
t
WR
DATA IN STABLE
NOTE: t
ODS
is required for common I/O operation only; for separate I/O operations, output disable is "don't care".
FIGURE 2. WRITE CYCLE TIME WAVEFORMS
(NOTE)
MWS5101, MWS5101A
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