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Электронный компонент: HCTS245DTR

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
Satellite Applications FlowTM (SAF) is a trademark of Intersil Corporation.
HCTS245T
Radiation Hardened Octal Bus
Transceiver, Three-State, Non-Inverting
Intersil's Satellite Applications Flow
TM
(SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
The Intersil HCTS245T is a Radiation Hardened Non-
Inverting Octal Bidirectional Bus Transceiver, Three-State,
intended for two-way asynchronous communication between
data busses. The HCTS245T allows data transmission from
the A bus to the B bus or from the B bus to the A bus. The
logic level at the direction input (DIR) determines the data
direction. The output enable input (OE) puts the I/O port in
the high-impedance state when high.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HCTS245T are
contained in SMD 5962-95745.
A "hot-link" is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil's Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Features
QML Class T, Per MIL-PRF-38535
Radiation Performance
- Gamma Dose (
) 1 x 10
5
RAD(Si)
- Latch-Up Free Under Any Conditions
- SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
- Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day (Typ)
3 Micron Radiation Hardened CMOS SOS
Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- V
IL
= 0.8V Max
- V
IH
= V
CC/2
Min
Input Current Levels Ii
5mA at V
OL
, V
OH
Pinouts
HCTS245DTR (SBDIP), CDIP2-T20
TOP VIEW
HCTS245KTR (FLATPACK), CDFP4-F20
TOP VIEW
Ordering Information
ORDERING
NUMBER
PART
NUMBER
TEMP.
RANGE
(
o
C)
5962R9574501TRC
HCTS245DTR
-55 to 125
5962R9574501TXC
HCTS245KTR
-55 to 125
NOTE:
Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
DIR
A0
A1
A2
A3
A4
A6
A5
A7
GND
V
CC
B0
B1
B2
OE
B3
B4
B5
B6
B7
2
3
4
5
6
7
8
1
20
19
18
17
16
15
14
13
9
10
12
11
DIR
A0
A1
A2
A3
A4
A6
A5
A7
GND
V
CC
B0
B1
B2
OE
B3
B4
B5
B6
B7
Data Sheet
July 1999
File Number
4619.1
2
Functional Diagram
TRUTH TABLE
CONTROL
INPUTS
OPERATION
OE
DIR
L
L
B Data to A Bus
L
H
A Data to B Bus
H
X
Isolation
H = High Voltage Level, L = Low Voltage Level,
X = Immaterial
To prevent excess currents in the High-Z (Isolation) modes, all I/O terminals
should be terminated with 10k
to 1M
resistors.
ONE OF 8 TRANSCEIVERS
B DATA
(18, 17, 16, 15,
14, 13, 12)
DIR
OUTPUT
ENABLE
1
11
19
A DATA
9
(2, 3, 4, 5,
6, 7, 8)
TO OTHER
7 CIRCUITS
P
N
N
P
HCTS245T
3
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Die Characteristics
DIE DIMENSIONS:
(3149
m x 2794
m x 533
m
51
m)
124 x 110 x 21mils
2mil
METALLIZATION:
Type: Al Si
Thickness: 11.0k
1k
SUBSTRATE POTENTIAL:
Unbiased Silicon on Sapphire
BACKSIDE FINISH:
Sapphire
PASSIVATION:
Type: Silox (S
i
O
2
)
Thickness: 13k
2.6k
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
274
PROCESS:
CMOS SOS
Metallization Mask Layout
HCTS245T
(18) B0
(17) B1
(16) B2
(15) B3
(14) B4
(13) B5
A0 (2)
A1 (3)
A2 (4)
A3 (5)
A4 (6)
A5 (7)
A6
(8)
A7
(9)
GND
(10)
B7
(11)
B6
(12)
NC
NC
(1)
DIR
(20)
V
CC
NC
NC
(19)
OE
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask
series for the HCTS245 is TA14417A.
HCTS245T