Mobile Intel
Pentium
III Processor-M
Datasheet
January 2003
Order Number: 298340-006
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Introduction
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Mobile Intel
Pentium
III Processor-M Datasheet
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Copyright Intel Corporation 2000-2002
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III Processor-M Datasheet
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Contents
1.
Introduction .................................................................................................................................... 11
1.1
Overview .............................................................................................................. 12
1.2
State of the Data .................................................................................................. 12
1.3
Terminology ......................................................................................................... 13
1.4
References........................................................................................................... 13
2.
Mobile Intel Pentium III Processor-M Features.............................................................................. 14
2.1
New Features in the Mobile Pentium III Processor-M ......................................... 14
2.1.1
133-MHz PSB With AGTL Signaling....................................................... 14
2.1.2
512-K On-die Integrated L2 Cache......................................................... 14
2.1.3
Data Prefetch Logic ................................................................................ 14
2.1.4
Differential Clocking ................................................................................ 14
2.1.5
Deeper Sleep State................................................................................. 15
2.1.6
Signal Differences Between the Mobile Pentium III Processor (in
BGA2 and Micro-PGA2 Packages) and the Mobile Intel Pentium III
Processor-M............................................................................................ 15
2.2
Power Management............................................................................................. 15
2.2.1
Clock Control Architecture ...................................................................... 15
2.2.2
Normal State ........................................................................................... 15
2.2.3
Auto Halt State........................................................................................ 16
2.2.4
Quick Start State..................................................................................... 17
2.2.5
HALT/Grant Snoop State ........................................................................ 18
2.2.6
Deep Sleep State.................................................................................... 18
2.2.7
Deeper Sleep State................................................................................. 18
2.2.8
Operating System Implications of Low-power States ............................. 19
2.2.9
Enhanced Intel SpeedStep Technology ................................................. 19
2.3
AGTL Signals ....................................................................................................... 19
2.4
Mobile Intel Pentium III Processor-M CPUID....................................................... 20
3.
Electrical Specifications ................................................................................................................. 21
3.1
Processor System Signals ................................................................................... 21
3.1.1
Power Sequencing Requirements .......................................................... 22
3.1.2
Test Access Port (TAP) Connection ....................................................... 23
3.1.3
Catastrophic Thermal Protection ............................................................ 23
3.1.4
Unused Signals....................................................................................... 23
3.1.5
Signal State in Low-power States........................................................... 23
3.1.5.1
System Bus Signals .............................................................. 23
3.1.5.2
CMOS and Open-drain Signals ............................................ 24
3.1.5.3
Other Signals ........................................................................ 24
3.2
Power Supply Requirements ............................................................................... 24
3.2.1
Decoupling Guidelines ............................................................................ 24
3.2.2
Voltage Planes........................................................................................ 25
3.2.3
Voltage Identification............................................................................... 25
3.3
System Bus Clock and Processor Clocking......................................................... 26
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3.4
Enhanced Intel SpeedStep Technology ...............................................................26
3.5
Maximum Ratings.................................................................................................27
3.6
DC Specifications .................................................................................................27
3.7
AC Specifications .................................................................................................37
3.7.1
System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC
Specifications ..........................................................................................37
4.
System Signal Simulations .............................................................................................................53
4.1
System Bus Clock (BCLK) and PICCLK DC Specifications and AC Signal
Quality
Specifications ...........................................................................................53
4.2
AGTL AC Signal Quality Specifications................................................................55
4.3
Non-AGTL Signal Quality Specifications..............................................................56
4.3.1
PWRGOOD, VTTPWRGD Signal Quality Specifications........................57
4.3.1.1.1
VTTPWRGD Noise Parameter Specification...........57
4.3.1.2
VTTPWRGD Transition Parameter Recommendation..........58
4.3.1.2.1
Transition Region.....................................................58
4.3.1.2.2
Transition Time ........................................................58
4.3.1.2.3
Noise ........................................................................58
5.
Mechanical Specifications ..............................................................................................................60
5.1
Socketable Micro-FCPGA Package .....................................................................60
5.2
Surface Mount Micro-FCBGA Package................................................................64
5.3
Signal Listings ......................................................................................................68
6.
V
CC
Thermal Specifications ............................................................................................................75
6.1
Thermal Diode ......................................................................................................76
7.
Processor Initialization and Configuration ......................................................................................78
7.1
Description............................................................................................................78
7.1.1
Quick Start Enable...................................................................................78
7.1.2
System Bus Frequency ...........................................................................78
7.1.3
APIC Enable ............................................................................................78
7.2
Clock Frequencies and Ratios .............................................................................78
8.
Processor Interface ........................................................................................................................79
8.1
Alphabetical Signal Reference .............................................................................79
8.2
Signal Summaries ................................................................................................89
Appendix A. PLL RLC Filter Specification ...................................................................................................91
A1.
Introduction..........................................................................................................91
A2.
Filter Specification ...............................................................................................91
A3.
Recommendation for Mobile Systems.................................................................92
A4.
Comments ...........................................................................................................93
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Figures
Figure 1. Clock Control States .......................................................................................... 17
Figure 2. PLL RLC Filter ................................................................................................... 25
Figure 3. VTTPWRGD System-Level Connections .......................................................... 26
Figure 4. Illustration of V
CC
Static and Transient Tolerances (VID = 1.40 V) .................. 31
Figure 5. Illustration of Deep Sleep V
CC
Static and Transient Tolerances (VID Setting
=
1.40
V)............................................................................................................ 32
Figure 6. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform ............. 44
Figure 7. Differential BCLK/BCLK# Waveform (Common Mode) ..................................... 44
Figure 8. BCLK/BCLK# Waveform (Differential Mode)..................................................... 45
Figure 9. Valid Delay Timings ........................................................................................... 45
Figure 10.
Setup and Hold Timings .................................................................................. 46
Figure 11. Cold/Warm Reset and Configuration Timings ................................................. 46
Figure 12. Power-on Sequence and Reset Timings ......................................................... 47
Figure 13. Power Down Sequencing and Timings (VCC Leading)................................... 48
Figure 14.
Power Down Sequencing and Timings (V
CCT
Leading).................................... 49
Figure 15.
Test Timings (Boundary Scan) ......................................................................... 50
Figure 16. Test Reset Timings.......................................................................................... 50
Figure 17.
Quick Start/Deep Sleep Timing (BCLK Stopping Method).............................. 51
Figure 18. Quick Start/Deep Sleep Timing (DPSLP# Assertion Method)......................... 51
Figure 19. Enhanced Intel SpeedStep Technology/Deep Sleep Timing .......................... 52
Figure 20. BCLK (Single Ended)/PICCLK Generic Clock Waveform ............................... 54
Figure 21. Maximum Acceptable Overshoot/Undershoot Waveform ............................... 55
Figure 22. VTTPWRGD Noise Specification .................................................................... 59
Figure 23. Socketable Micro-FCPGA Package Top and Bottom Isometric Views ........ 61
Figure 24. Socketable Micro-FCPGA Package Top and Side View .............................. 62
Figure 25. Socketable Micro-FCPGA Package Bottom View ........................................ 63
Figure 26. Micro-FCBGA Package Top and Bottom Isometric Views ........................... 65
Figure 27. Micro-FCBGA Package Top and Side Views ............................................... 66
Figure 28. Micro-FCBGA Package Bottom View ........................................................... 67
Figure 29. Pin/Ball Map Top View.................................................................................. 68
Figure 30. PLL Filter Specifications .................................................................................. 92
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