PB LXT16596-97
Intel
Internet Exchange
Architecture
Product Description
The Intel
LXT16596 and Intel
LXT16597
form a high-performance transponder
chipset for use in SDH STM-16/4/1, SONET
OC-48/12/3 telecommunications systems,
and Optical Transport Network (OTN) sys-
tems with digital wrapping.
The LXT16596 receiver is an on-the-fly
programmable multi-bitrate Clock and Data
Recovery (CDR) device with a 1:4
Demultiplexer (DeMUX), integrated Clock
Multiplication Unit (CMU), and a Limiting
Amplifier (LIA).
The LXT16597 transmitter is an on-the-fly
programmable multi-bitrate 4:1 multiplexer
(MUX) with integrated clock generation and
Phase Locked Loop (PLL) circuits. The inte-
grated chipset ensures simple board design.
The fully integrated on-chip PLLs elimi-
nate critical clock and data timing relations
product brief
and feature the unique dynamic phase align-
ment between ASIC and MUX. The continu-
ous handling of "round trip delay variations"
by the source synchronous clocking ensures
easy external optimization of jitter.
The Intel
LXT16596/97 chipset is manu-
factured in a well-proven silicon bipolar tech-
no-logy that offers the performance, stability
and reliability customers require for optical
communication systems.
The devices are operated from a single
+3.3V power supply with a power dissipation
of 1.0W for LXT16597 and 1.25W for
LXT16596.
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Single Power Supply: +3.3V
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Easy board design and integration
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Power dissipation: 1.25W
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High integration
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Interfaces to Intel
IXF32003 and
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Advanced system solution integrating odd
Intel
IXF6192
ratio digital wrapping
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OIF compliant interface
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Complete CDR secures interoperability
between Demultiplexer and Framer
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100-lead plastic package
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Small physical form factor (14x14mm).
Reduces board space
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Integrated limiting amplifier
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Avoid external limiting amplifier. Cost and
space savings
LXT16596 Receiver
Features
Benefits
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Single Power Supply: +3.3V
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Easy board design and integration
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Power dissipation: 1.0W
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High integration
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Interfaces to Intel
IXF32003 and
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Advanced system solution integrating odd
Intel
IXF6192
ratio digital wrapping
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Dynamic Phase Alignment based on PLL
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Infinite phase margin tolerance
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100-lead plastic package
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Small physical form factor (14x14mm).
Reduces board space
LXT16597 Transmitter
Features
Benefits
Intel
LXT16596/LXT16597
Transmitter/Receiver Chipset
Key Features
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The Intel
LXT16596/97 multi-bitrate chipset is distin-
guished by a low power dissipation and is compatible
with the following line rates:
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2.488Gbit/s
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1.250Gbit/s
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622.08Mbit/s
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155.52Mbit/s
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It offers the possibility of transmitting and receiving
data at increased rates if overhead is needed.
Fractions available are 32/31, 16/15 and 15/14, which
is needed for Forward Error Correction (FEC) applica-
tions.
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The LXT16596 receiver features an integrated limiting
amplifier with an input sensitivity better than 10mV.
Key Applications
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SDH STM-16/4/1
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SONET OC-48/12/3
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OTN
Application Overview
The Intel family of receiver and transmitter line cards are
high performance MUX and DeMUX functions in a variety
of system configurations.
Receiver line card
An optical reception system receives an optical signal
and converts it into an electrical signal. The optical
receiver, which can be a PIN diode or an Avalanche
Photo Detector (APD), converts the optical input to a
small electrical current. A Transimpedance Amplifier (TIA)
also known as a pre-amplifier, then converts the current
to an electrical voltage. The TIA signal, which varies from
a few mV up to 50mVpp or more, can be passed to an
Automatic Gain Controlled (AGC) amplifier or a LIA. This
produces a signal of sufficient amplitude/power to drive
the next building block (See figure 1). A CDR device con-
verts the analog input signal to a digital bit stream with an
associated clock, and the serial high-speed data stream
is finally converted to a parallel signal at lower speed.
This signal then interfaces to the digital processing sys-
tem.
The key function block in the CDR is the PLL, which
locks onto the incoming data stream. The phase detector
is equipped with a discriminator that evaluates the
incoming data signal in the middle of the bit period (the
"eye") and determines whether a 1 or a 0 is received.
A separate lock detector determines whether the
incoming data rate deviates too much from a given fre-
quency. If data input is absent or deviates too much, the
external reference clock ensures that the Voltage
Controlled Oscillator (VCO) remains in a selectable +/-500
to +/-2,000 ppm capture range.
Phase noise and amplitude noise, also known as jitter,
can cause incorrect determination of data bits (bit errors)
in the input signal. When a valid input signal is applied
both differential data and clock outputs are provided.
The DeMUX transforms the serial data signal into four
parallel data signals at a corresponding lower data rate.
If, for example, a 2.488Gbit/s signal (OC-48/STM-16) is
fed into a 1:4 DeMUX, it will produce four parallel data
outputs at 622.08Mbit/s.
Clock output from the CDR is used to clock the data
on the parallel interface into the next device. The Intel
LXT16596 has a DeMUX merged with a CDR and is fully
compliant with the Optical Interface Forum's SFI recom-
mendation on common electrical interface between framers
and Serializer/Deserializer (SerDes) for OC-48/STM-16.
Transmitter line card
In the optical transmission system the parallel signal from
the processing system is converted to a serial signal at
the bitrate of the optical link. The serial signal is amplified
before it is fed to the laser, which converts it to an optical
SIC
O/E
TIA
LIA /AGC
DeMUX
Figure 1. Typical receiver line card
signal. The quality of the transmitted optical signal
(i.e., the maximum transmission distance) is highly
dependent on the jitter of the serial bit stream. The jitter is
the phase noise most commonly caused by the uncer-
tainty or variations in the bit periods. To resolve this, Intel
has directed significant effort towards the system and
component design, focused at maintaining precise, con-
stant duration of the bit periods in the outgoing data
stream (see figure 2).
The MUX has the opposite functions of the DeMUX.
For instance, the MUX might convert a 4-bit parallel sig-
nal into one serial bit stream at a corresponding higher
data rate. When four parallel inputs at 622.08Mbit/s are
fed into a 4:1 MUX, the output data rate will be
2.488Gbit/s for OC-48/STM-16.
The clock interconnections between the MUX and the
data source (such as the framer) can be complex in high-
speed applications. In high-speed clock operation for
MUXs, the input sampling clock must be in the phase to
ensure correct loading of the data into the MUXs so that
input data can be sampled correctly. In addition, the
internal high-speed clock used for shifting data to the
laser must be as clean as possible to minimize the jitter in
the output signal. Three PLLs are implemented in each
MUX to accommodate these critical requirements.
System
ASIC
RXCKL_P/N
RXDATA3_P/N
RXDATA0_P/N
.....
C
KREF
/N
F
C
K
/N
DI/N
Hz
40.134MHz
TXCLK_P/N
TXDATA3_P/N
.....
bit/s
X
C
K1
/N
C
KI
/N
RE
CC
K
/N
TXCLK_SRC_P/N
Figure 2. Typical transmitter line card
Figure 3. System Application Layout
Support Collateral/Tools
Item
Description
Order Number
Data Sheets
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LXT16596/97 Data sheet
249700
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LXD90596/97 Evaluation board data sheet
249701
Support Products
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LXD90596/97 Evaluation board and gerber files
Contact local sales rep
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LXT16596/97 Footprint
Contact local sales rep
Application Brief
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Building Blocks for SONET/SDH Network Elements
249508
and Aggregation
Intel Access
Developer's Site
http://developer.intel.com
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Internet Exchange Architecture Home Page
http://www.intel.com/IXA
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http://developer.intel.com/design/network
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2001 Intel Corporation
Order Number: 249654-001 Printed in US/0601/5K/LOFI/LKL
Intel
Internet Exchange Architecture
Intel
Internet Exchange Architecture is an end-to-end
family of high-performance, flexible and scalable hardware
and software development building blocks designed to
meet the growing performance requirements of today's
networks. Based on programmable silicon and software
building blocks, Intel
IXA solutions enable faster devel-
opment, more cost-effective deployment and future
upgradability of network and communications systems.
Additional information can be found at www.intel.com/IXA
Physical Layer Devices
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