December 1997

Order Number: 272771-002

EMBEDDED WRITE-BACK ENHANCED

IntelDX4TM PROCESSOR

Figure 1. Embedded Write-Back Enhanced IntelDX4TM

Processor Block Diagram

Up to 100 MHz Operation

Integrated Floating-Point Unit

Speed-Multiplying Technology

32-Bit RISC Technology Core

16-Kbyte Write-Back Cache

3.3 V Core Operation with 5 V Tolerant
I/O Buffers

Burst Bus Cycles

Dynamic Bus Sizing for 8- and 16-bit
Data Bus Devices

SL Technology

Data Bus Parity Generation and Checking

Boundary Scan (JTAG)

3.3-Volt Processor, 75 MHz, 25 MHz CLK
-- 208-Lead Shrink Quad Flat Pack (SQFP)

3.3-Volt Processor, 100 MHz, 33 MHz CLK
-- 208-Lead Shrink Quad Flat Pack (SQFP)
-- 168-Pin Pin Grid Array (PGA)

Binary Compatible with Large Software
Base

Paging

Unit

Prefetcher

32-Byte Code

Queue

2 x 16 Bytes

Code

Stream

Floating

Point Unit

Barrel

Shifter

Cache Unit

Burst Bus

Control

Bus Control

Write Buffers

4 x 32

64-Bit Interunit Transfer Bus

File

ALU

Segmentation

Unit

Descriptor

Registers

Limit and

Attribute PLA

Base/

Index

Bus

Translation

Lookaside

Buffer

16 Kbyte

Cache

Clock

Multiplier

Floating

Point

Control &

Protection

Test Unit

Control

ROM

Address

Drivers

CLK

Core
Clock

Data Bus

Transceivers

Request

Sequencer

Bus Size

Control

Cache

Control

Parity

Generation

and Control

Boundary

Scan

Control

Bus Interface

D31-D0

A31-A2 BE3#- BE0#

ADS# W/R# D/C# M/IO# PCD
PWT RDY# LOCK# PLOCK#
BOFF# A20M# BREQ HOLD
HLDA RESET SRESET INTR
NMI SMI# SMIACT# FERR#
IGNNE# STPCLK#

BRDY# BLAST#

BS16# BS8#

KEN# FLUSH# AHOLD EADS#

CACHE# HITM# INV WB/WT#

TCK TMS TDI TDO

128

Instruction

Decode

Decoded
Instruction
Path

PCD

PWT

Physical
Address

32-Bit Data Bus

Linear Address

Micro-

Instruction

Displacement Bus

PCHK# DP3-DP0

A3232-01

CLKMUL

Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.

The Embedded Write-Back Enhanced IntelDX4TM processor may contain design defects or errors known as
errata which may cause the product to deviate from published specifications. Current characterized errata are
available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your
product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

Contents

iii

EMBEDDED WRITE-BACK ENHANCED

IntelDX4TM PROCESSOR

1.0 INTRODUCTION ............................................................................................................. ........................... 1

1.1 Features ............................................................................................................................................. 1

1.2 Family Members ........................................................................................................... ...................... 2

2.0 HOW TO USE THIS DOCUMENT ................................................................................................. ............ 3

3.0 PIN DESCRIPTIONS ......................................................................................................... ........................ 3

3.1 Pin Assignments .......................................................................................................... ....................... 3

3.2 Pin Quick Reference ......................................................................................................................... 16

4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW ............................................................................. 26

4.1 CPUID Instruction ............................................................................................................................. 26

4.1.1 Operation of the CPUID Instruction ....................................................................................... 26

4.2 Identification After Reset .................................................................................................................. 28

4.3 Boundary Scan (JTAG) .................................................................................................................... 28

4.3.1 Device Identification ............................................................................................................... 28

4.3.2 Boundary Scan Register Bits and Bit Order ........................................................................... 29

5.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 30

5.1 Maximum Ratings ............................................................................................................................. 30

5.2 DC Specifications ............................................................................................................................. 30

5.3 AC Specifications ............................................................................................................................. 33

5.4 Capacitive Derating Curves .............................................................................................................. 40

6.0 MECHANICAL DATA .............................................................................................................................. 42

6.1 Package Dimensions ........................................................................................................................ 42

6.2 Package Thermal Specifications ...................................................................................................... 44

FIGURES

Figure 1.

Embedded Write-Back Enhanced IntelDX4TM

Processor Block Diagram ................................... i

Figure 2.

Package Diagram for 208-Lead SQFP Embedded Write-Back Enhanced
IntelDX4TM Processor ................................................................................................................ 4

Figure 3.

Package Diagram for 168-Pin PGA Embedded Write-Back Enhanced
IntelDX4TM Processor .............................................................................................................. 10

Figure 4.

CLK Waveform ........................................................................................................................ 36

Figure 5.

Input Setup and Hold Timing ................................................................................................... 36

Figure 6.

Input Setup and Hold Timing ................................................................................................... 37

Figure 7.

PCHK# Valid Delay Timing ...................................................................................................... 37

Figure 8.

Output Valid Delay Timing ....................................................................................................... 38

Figure 9.

Maximum Float Delay Timing .................................................................................................. 38

Figure 10.

TCK Waveform ........................................................................................................................ 39

Figure 11.

Test Signal Timing Diagram .................................................................................................... 39

Contents

Figure 12.

Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a Low-to-High Transition ..................................................................................................... 40

Figure 13.

Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a High-to-Low Transition ..................................................................................................... 40

Figure 14.

Typical Loading Delay versus Load Capacitance in Mixed Voltage System ........................... 41

Figure 15.

208-Lead SQFP Package Dimensions .................................................................................... 42

Figure 16.

Principal Dimensions and Data for 168-Pin Grid Array Package ............................................. 43

TABLES

Table 1.

The Embedded Write-Back Enhanced IntelDX4TM Processor Family ....................................... 2

Table 2.

Pinout Differences for 208-Lead SQFP Package ...................................................................... 5

Table 3.

Pin Assignment for 208-Lead SQFP Package ........................................................................... 6

Table 4.

Pin Cross Reference for 208-Lead SQFP Package ................................................................... 8

Table 5.

Pinout Differences for 168-Pin PGA Package ......................................................................... 11

Table 6.

Pin Assignment for 168-Pin PGA Package .............................................................................. 12

Table 7.

Pin Cross Reference for 168-Pin PGA Package ...................................................................... 14

Table 8.

Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions ............................. 16

Table 9.

Output Pins .............................................................................................................................. 24

Table 10.

Input/Output Pins ..................................................................................................................... 24

Table 11.

Test Pins .................................................................................................................................. 25

Table 12.

Input Pins ................................................................................................................................. 25

Table 13.

CPUID Instruction Description ................................................................................................. 26

Table 14.

Boundary Scan Component Identification Code (Write-Through/Standard Bus Mode) ........... 28

Table 15.

Boundary Scan Component Identification Code (Write-Back/Enhanced Bus Mode) ............... 29

Table 16.

Absolute Maximum Ratings ..................................................................................................... 30

Table 17.

Operating Supply Voltages ...................................................................................................... 30

Table 18.

DC Specifications ..................................................................................................................... 31

Table 19.

Values ................................................................................................................................ 32

Table 20.

AC Characteristics ................................................................................................................... 33

Table 21.

AC Specifications for the Test Access Port ............................................................................. 35

Table 22.

168-Pin Ceramic PGA Package Dimensions ........................................................................... 43

Table 23.

Ceramic PGA Package Dimension Symbols ........................................................................... 44

Table 24.

Thermal Resistance,

(

C/W) ............................................................................................. 45

Table 25.

Thermal Resistance,

(

C/W) ............................................................................................. 45

Table 26.

Maximum T

ambient

, T

max (

C) ............................................................................................... 45

Embedded Write-Back Enhanced IntelDX4TM Processor

1.0

INTRODUCTION

The embedded Write-Back Enhanced IntelDX4TM
processor provides high performance to 32-bit,
embedded applications. Designed for applications
that need a floating-point unit, the processor is ideal
for embedded designs running DOS*, Microsoft
Windows*, OS/2*, or UNIX* applications written for
the Intel architecture. Projects can be completed
quickly using the wide range of software tools,
utilities, assemblers and compilers that are available
for desktop computer systems. Also, developers can
find advantages in using existing chipsets and
peripheral components in their embedded designs.

The Embedded Write-Back Enhanced IntelDX4
processor is binary compatible with the Intel386TM
and earlier Intel processors. Compared with the
Intel386 processor, it provides faster execution of
many commonly-used instructions. It also provides
the benefits of an integrated, 16-Kbyte, write-back
cache for code and data. Its data bus can operate in
burst mode which provides up to 106-Mbyte-per-
second transfers for cache-line fills and instruction
prefetches.

Intel's SL technology is incorporated in the
Embedded Write-Back Enhanced IntelDX4
processor. Utilizing Intel's System Management
Mode (SMM) enables designers to develop energy-
efficient systems.

Two component packages are available:

· 168-pin Pin Grid Array (PGA)

· 208-lead Shrink Quad Flat Pack (SQFP)

The processor operates at either two or three times
the external bus frequency. At two times the external
bus frequency the processor operates up to 66 MHz,
(33-MHz CLK). At three times the external bus
frequency the processor operates up to 100 MHz
(33-MHz CLK).

1.1

Features

The Embedded Write-Back Enhanced IntelDX4
processor offers these features:

· 32-bit RISC-Technology Core -- The Embedded

Write-Back Enhanced IntelDX4 processor
performs a complete set of arithmetic and logical
operations on 8-, 16-, and 32-bit data types using
a full-width ALU and eight general purpose
registers.

· Single Cycle Execution -- Many instructions

execute in a single clock cycle.

· Instruction Pipelining -- Overlapped instruction

fetching, decoding, address translation and
execution.

· On-Chip Floating-Point Unit -- Intel486TM

processors support the 32-, 64-, and 80-bit formats
specified in IEEE standard 754. The unit is binary
compatible with the 8087, Intel287TM, Intel387TM
coprocessors, and Intel OverDrive

processor.

· On-Chip Cache with Cache Consistency

Support -- A 16-Kbyte internal cache is used for
both data and instructions. It is configurable to be
write-back or write-through on a line-by-line basis.
The internal cache implements a modified MESI
protocol, which is applicable to uniprocessor
systems. Cache hits provide zero wait-state
access times for data within the cache. Bus activity
is tracked to detect alterations in the memory
represented by the internal cache. The internal
cache can be invalidated or flushed so that an
external cache controller can maintain cache
consistency.

· External Cache Control -- Write-back and flush

controls for an external cache are provided so the
processor can maintain cache consistency.

· On-Chip Memory Management Unit -- Address

management and memory space protection
mechanisms maintain the integrity of memory in a
multitasking and virtual memory environment. Both
memory segmentation and paging are supported.

· Burst Cycles -- Burst transfers allow a new

double-word to be read from memory on each bus
clock cycle. This capability is especially useful for
instruction prefetch and for filling the internal
cache. Data written from the processor to memory
can also be burst transfers.

· Write Buffers -- The processor contains four

write buffers to enhance the performance of
consecutive writes to memory. The processor can
continue internal operations after a write to these
buffers, without waiting for the write to be
completed on the external bus.

Embedded Write-Back Enhanced IntelDX4TM Processor

· Bus Backoff -- When another bus master needs

control of the bus during a processor initiated bus
cycle, the Embedded Write-Back Enhanced
IntelDX4 processor floats its bus signals, then
restarts the cycle when the bus becomes available
again.

· Instruction Restart -- Programs can continue

execution following an exception generated by an
unsuccessful attempt to access memory. This
feature is important for supporting demand-paged
virtual memory applications.

· Dynamic Bus Sizing -- External controllers can

dynamically alter the effective width of the data
bus. Bus widths of 8, 16, or 32 bits can be used.

· Boundary Scan (JTAG) -- Boundary Scan

provides in-circuit testing of components on
printed circuit boards. The Intel Boundary Scan
implementation conforms with the IEEE Standard
Test Access Port and Boundary Scan Architecture.

· Enhanced Bus Mode -- The definitions of some

signals have been changed to support write-back
cache mode.

Intel's SL technology provides these features:

· Intel System Management Mode (SMM) -- A

unique Intel architecture operating mode provides
a dedicated special purpose interrupt and address
space that can be used to implement intelligent
power management and other enhanced functions
in a manner that is completely transparent to the
operating system and applications software.

· I/O Restart -- An I/O instruction interrupted by a

System Management Interrupt (SMI#) can
automatically be restarted following the execution
of the RSM instruction.

· Stop Clock -- The Embedded Write-Back

Enhanced IntelDX4 processor has a stop clock
control mechanism that provides two low-power
states: a Stop Grant state (2050 mA typical,
depending on input clock frequency) and a Stop
Clock state (~600

A typical, with input clock

frequency of 0 MHz).

· Auto HALT Power Down -- After the execution of

a HALT instruction, the Embedded Write-Back
Enhanced IntelDX4 processor issues a normal
Halt bus cycle and the clock input to the processor
core is automatically stopped, causing the
processor to enter the Auto HALT Power Down
state (2050 mA typical, depending on input clock
frequency).

· Auto Idle Power Down -- This function allows the

processor to reduce the core frequency to the bus
frequency when both the core and bus are idle.
Auto Idle Power Down is software transparent and
does not affect processor performance. Auto Idle
Power Down provides an average power savings
of 10% and is only applicable to clock multiplied
processors.

1.2

Family Members

Table 1 shows the Embedded Write-Back Enhanced
IntelDX4 processors and briefly describes their
characteristics.

Table 1. The Embedded Write-Back Enhanced IntelDX4TM Processor Family

Product

Supply Voltage

Maximum
Processor

Frequency

Maximum

External Bus

Frequency

Package

FC80486DX4WB75

3.3 V

MHz

208-Lead SQFP

FC80486DX4WB100

3.3 V

100

MHz

208-Lead SQFP

A80486DX4WB100

3.3 V

100

MHz

168-Pin PGA

Embedded Write-Back Enhanced IntelDX4TM Processor

2.0

HOW TO USE THIS DOCUMENT

For a complete set of documentation related to the
Embedded Write-Back Enhanced IntelDX4
processor, use this document in conjunction with the
following reference documents:

Embedded Intel486TM Processor Family
Developer's Manual

-- Order No. 273021

Embedded Intel486TM Processor Hardware
Reference Manual

-- Order No. 273025

Intel486 Microprocessor Family Programmer's
Reference Manual

-- Order No. 240486

· Intel Application Note AP-485 --

Intel Processor

Identification with the CPUID Instruction

Order No. 241618

The information in the reference documents for the
IntelDX4 processor applies to the Embedded Write-
Back Enhanced IntelDX4 processor. Some of the
IntelDX4 processor information is duplicated in this
document to minimize the dependence on the
reference documents.

3.0

PIN DESCRIPTIONS

3.1

Pin Assignments

The following figures and tables show the pin assign-
ments of each package type for the Embedded
Write-Back Enhanced IntelDX4 processor. Tables
are provided showing the pin differences between
the Embedded Write-Back Enhanced IntelDX4
processor and other embedded Intel486 processor
products.

208-Lead SQFP - Quad Flat Pack

· Figure 2, Package Diagram for 208-Lead SQFP

Embedded Write-Back Enhanced IntelDX4TM
Processor (pg. 4)

· Table 2, Pinout Differences for 208-Lead SQFP

Package (pg. 5)

· Table 3, Pin Assignment for 208-Lead SQFP

Package (pg. 6)

· Table 4, Pin Cross Reference for 208-Lead SQFP

Package (pg. 8)

168-Pin PGA - Pin Grid Array

· Figure 3, Package Diagram for 168-Pin PGA

Embedded Write-Back Enhanced IntelDX4TM
Processor (pg. 10)

· Table 5, Pinout Differences for 168-Pin PGA

Package (pg. 11)

· Table 6, Pin Assignment for 168-Pin PGA

Package (pg. 12)

· Table 7, Pin Cross Reference for 168-Pin PGA

Package (pg. 14)

Embedded Write-Back Enhanced IntelDX4TM Processor

Figure 2. Package Diagram for 208-Lead SQFP Embedded Write-Back Enhanced IntelDX4TM Processor

156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105

208-Lead SQFP

Embedded Write-Back Enhanced

IntelDX4TM Processor

Top View

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

100

101

102

103

104

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

LOCK#

PLOCK# V

BLAST#

ADS# A2 V

RESERVED#

A7 V

A8 V

A9 A10

A11

A12

A13 A14

A15 A16

A17 V

TDI

TMS

A18

A19

A20 V

A21

A22

A23

A24

CC5

PCHK#
BRDY#

BOFF#

BS16#

BS8#

CLKMUL

RDY#

KEN#

HOLD

AHOLD

TCK

CLK

HLDA

W/R#

BREQ

BE0#
BE1#
BE2#
BE3#

M/IO#

D/C#
PWT

PCD

EADS#

A20M#

RESET

FLUSH#

INTR

NMI

A25
A26
A27
A28

A29
A30
A31

DP0
D0
D1
D2
D3
D4

D5
D6

NC
D7
DP1
D8
D9

D10
D11
D12
D13

D14
D15

DP2
D16

SRESET

SMIACT#

HITM#

WB/WT#

SMI#

FERR#

TDO

CACHE#

INV

IGNNE#

STPCLK#

D31

D30

D29

D28

D27

D26

D25

D24

DP3

D23

D22

D21

D20

D19

D18

D17

A3230-01

Embedded Write-Back Enhanced IntelDX4TM Processor

Table 2. Pinout Differences for 208-Lead SQFP Package

Pin #

Embedded

Intel486TM SX

Processor

Embedded
IntelDX2TM

Processor

Embedded Write-Back

Enhanced IntelDX4TM

Processor

CC5

INC

CLKMUL

INC

HITM#

INC

WB/WT#

INC

FERR#

INC

CACHE#

INC

INV

INC

IGNNE#

NOTES:

1. This pin location is for the V

CC5

pin on the embedded IntelDX4 processor. For compatibility with 3.3V processors that

have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin should be connected to a V

trace, not to

the V

plane.

2. INC. Internal No Connect. These pins are not connected to any internal pad. However, signals are defined for the loca-

tion of the INC pins in the embedded IntelDX4 processor. One system design can accommodate any one of these pro-
cessors provided the purpose of each INC pin is understood before it is used.

Embedded Write-Back Enhanced IntelDX4TM Processor

Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 1 of 2)

Pin#

Description

Pin#

Description

Pin#

Description

Pin#

Description

105

157

106

158

A24

107

159

A23

PCHK#

108

D16

160

A22

BRDY#

109

DP2

161

A21

BOFF#

SRESET

110

162

BS16#

SMIACT#

111

163

BS8#

112

D15

164

A20

113

D14

165

A19

114

166

A18

CLKMUL

HITM#

115

167

TMS

RDY#

WB/WT#

116

D13

168

TDI

KEN#

SMI#

117

D12

169

FERR#

118

D11

170

119

D10

171

A17

HOLD

TDO

120

172

AHOLD

121

173

A16

TCK

CACHE#

122

174

A15

INV

123

175

IGNNE#

124

176

STPCLK#

125

DP1

177

A14

D31

126

178

A13

D30

127

179

CLK

128

180

A12

129

181

HLDA

D29

130

182

A11

W/R#

D28

131

183

132

184

133

185

BREQ

134

186

A10

BE0#

D27

135

187

BE1#

D26

136

188

BE2#

D25

137

189

BE3#

138

190

D24

139

191

Embedded Write-Back Enhanced IntelDX4TM Processor

140

192

M/IO#

141

193

DP3

142

194

RESERVED#

D/C#

D23

143

195

PWT

D22

144

196

PCD

D21

145

DP0

197

146

198

147

A31

199

148

A30

200

149

A29

201

EADS#

150

202

A20M#

D20

151

A28

203

ADS#

RESET

100

D19

152

A27

204

BLAST#

FLUSH#

101

D18

153

A26

205

INTR

102

154

A25

206

PLOCK#

NMI

103

D17

155

207

LOCK#

104

156

208

NOTE:

1. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to V

, or V

or to any other

signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors.

Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 2 of 2)

Pin#

Description

Pin#

Description

Pin#

Description

Pin#

Description

Embedded Write-Back Enhanced IntelDX4TM Processor

Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 1 of 2)

Address

Pin #

Data

Pin #

Control

Pin #

CC5

202

144

A20M#

197

143

ADS#

203

196

142

AHOLD

127

195

141

BE0#

193

140

BE1#

192

130

BE2#

190

129

BE3#

187

126

BLAST#

204

A10

186

124

BOFF#

A11

182

123

BRDY#

A12

180

D10

119

BREQ

A13

178

D11

118

BS16#

A14

177

D12

117

BS8#

A15

174

D13

116

CACHE#

A16

173

D14

113

CLK

A17

171

D15

112

CLKMUL

A18

166

D16

108

D/C#

A19

165

D17

103

DP0

145

104

A20

164

D18

101

DP1

125

105

A21

161

D19

100

DP2

109

107

A22

160

D20

DP3

110

A23

159

D21

EADS#

115

A24

158

D22

FERR#

120

A25

154

D23

FLUSH#

122

A26

153

D24

HITM#

132

A27

152

D25

HLDA

135

A28

151

D26

HOLD

102

138

A29

149

D27

IGNNE#

106

146

A30

148

D28

INTR

111

156

A31

147

D29

INV

114

157

D30

KEN#

121

170

D31

LOCK#

207

128

175

M/IO#

131

181

Embedded Write-Back Enhanced IntelDX4TM Processor

Figure 3. Package Diagram for 168-Pin PGA Embedded Write-Back Enhanced IntelDX4TM Processor

A3231-01

D20

D19

D11

D22

D21

D18

D13

DP1

CC5

A31

A29

A28

A27

A25

A26

TCK

CLK

D17

D10

D15

D12

DP2

D16

D14

DP0

A30

A17

A23

D23

A19

VOLDET

DP3

D24

D25

D27

D26

A21

A18

A14

A24

A22

A15

A12

A20

A16

A13

A11

A10

D29

D31

D28

D30

INV

SMI#

SRESET

RESERVED#

HITM# CACHE# SMIACT#

INC

WB/WT#

TDI

TMS

FERR#

IGNNE#

NMI

FLUSH# A20M# HOLD KEN# STPCLK# BRDY#

BE2#

BE0#

PWT

D/C#

LOCK#

HLDA

BREQ

INTR

TDO

RESET

BS8#

RDY#

BE1#

M/IO#

PLOCK# BLAST#

AHOLD EADS# BS16# BOFF#

BE3#

PCD

W/R#

PCHK# CLKMUL ADS#

168-Pin PGA

Embedded Write-Back Enhanced

IntelDX4TM Processor

Pin Side View

Embedded Write-Back Enhanced IntelDX4TM Processor

Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 1 of 2)

Pin #

Description

Pin #

Description

Pin #

Description

D20

D17

BOFF#

A29

D22

A30

TCK

P15

HLDA

D23

D10

P16

DP3

E15

HOLD

P17

D24

E16

A31

E17

D29

DP1

A17

A19

A10

INV

D15

A21

A11

F15

KEN#

A24

A12

HITM#

F16

RDY#

A22

A13

INC

F17

BE3#

A20

A14

TDI

A16

A15

IGNNE#

Q10

A13

A16

INTR

D12

Q11

A17

AHOLD

G15

STPCLK#

Q12

D19

G16

Q13

D21

G17

Q14

Q15

BREQ

Q16

PLOCK#

DP2

Q17

PCHK#

D25

H15

BRDY#

A28

H16

A25

D31

H17

CC5

B10

SMI#

A18

B11

D16

B12

CACHE#

J15

BE2#

A15

B13

WB/WT#

J16

BE1#

B14

TMS

J17

PCD

B15

NMI

R10

B16

TDO

R11

B17

EADS#

D14

R12

A11

D11

K15

BE0#

R13

D18

K16

R14

CLK

K17

R15

R16

BLAST#

R17

CLKMUL

Embedded Write-Back Enhanced IntelDX4TM Processor

Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 1 of 2)

Addres

Pin #

Data

Pin #

Control

Pin #

INC

Vcc5

Vcc

Vss

Q14

A20M#

D15

C13

A13

R15

ADS#

S17

S16

AHOLD

A17

B11

A11

Q12

BE0#

K15

S15

BE1#

J16

Q13

BE2#

J15

R13

BE3#

F17

E16

Q11

BLAST#

R16

E17

A10

S13

BOFF#

D17

G16

A11

R12

BRDY#

H15

H16

G17

A12

D10

BREQ

Q15

A13

Q10

D11

BS16#

C17

K16

H17

A14

D12

BS8#

D16

L16

A15

D13

CLK

K17

A16

D14

CLKMUL

R17

M16

A17

D15

CACHE#

B12

P16

L17

A18

D16

D/C#

M15

A19

D17

DP0

M17

A20

D18

DP1

P17

A21

D19

DP2

A22

D20

DP3

R10

A23

D21

EADS#

B17

R11

A24

D22

FERR#

C14

R14

A25

D23

FLUSH#

C15

A26

D24

HITM#

A12

S10

A27

D25

HLDA

P15

S11

A28

D26

HOLD

E15

S12

A29

D27

IGNNE#

A15

S14

A30

D28

INTR

A16

A31

D29

INV

A10

D30

KEN#

F15

D31

LOCK#

N15

M/IO#

N16

Embedded Write-Back Enhanced IntelDX4TM Processor

3.2

Pin Quick Reference

The following is a brief pin description. For detailed signal descriptions refer to Appendix A, "Signal Descrip-
tions," in the

Embedded Intel486TM Processor Family Developer's Manual,

order No. 273021.

Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 1 of 8)

Symbol

Type

Name and Function

CLK

Clock

provides the fundamental timing and internal operating frequency for the

Embedded Write-Back Enhanced IntelDX4 processor. All external timing
parameters are specified with respect to the rising edge of CLK.

ADDRESS BUS

A31-A4

A3A2

I/O

Address Lines A31A2, together with the byte enable signals, BE3#BE0#,
define the physical area of memory or input/output space accessed. Address lines
A31A4 are used to drive addresses into the Embedded Write-Back Enhanced
IntelDX4 processor to perform cache line invalidation. Input signals must meet
setup and hold times t

and t

. A31A2 are not driven during bus or address

hold.

BE3#

BE2#

BE1#

BE0#

Byte Enable

signals indicate active bytes during read and write cycles. During the

first cycle of a cache fill, the external system should assume that all byte enables
are active. BE3#BE0# are active LOW and are not driven during bus hold.

BE3# applies to D31D24

BE2# applies to D23D16

BE1# applies to D15D8

BE0# applies to D7D0

DATA BUS

D31D0

I/O

Data Lines. D7D0 define the least significant byte of the data bus; D31D24
define the most significant byte of the data bus. These signals must meet setup
and hold times t

and t

for proper operation on reads. These pins are driven

during the second and subsequent clocks of write cycles.

DATA PARITY

DP3DP0

I/O

There is one Data Parity pin for each byte of the data bus. Data parity is generated
on all write data cycles with the same timing as the data driven by the Embedded
Write-Back Enhanced IntelDX4 processor. Even parity information must be driven
back into the processor on the data parity pins with the same timing as read
information to ensure that the correct parity check status is indicated by the
Embedded Write-Back Enhanced IntelDX4 processor. The signals read on these
pins do not affect program execution.

Input signals must meet setup and hold times t

and t

. DP3DP0 must be

connected to V

through a pull-up resistor in systems that do not use parity.

DP3DP0 are active HIGH and are driven during the second and subsequent
clocks of write cycles.

PCHK#

Parity Status is driven on the PCHK# pin the clock after ready for read operations.
The parity status is for data sampled at the end of the previous clock. A parity error
is indicated by PCHK# being LOW. Parity status is only checked for enabled bytes
as indicated by the byte enable and bus size signals. PCHK# is valid only in the
clock immediately after read data is returned to the processor. At all other times
PCHK# is inactive (HIGH). PCHK# is never floated.

Embedded Write-Back Enhanced IntelDX4TM Processor

BUS CYCLE DEFINITION

M/IO#

D/C#

W/R#

Memory/Input-Output

Data/Control

and Write/Read

lines are the primary bus

definition signals. These signals are driven valid as the ADS# signal is asserted.

M/IO#

D/C#

W/R#

Bus Cycle Initiated

Interrupt Acknowledge

HALT/Special Cycle (see details below)

I/O Read

I/O Write

Code Read

Reserved

Memory Read

Memory Write

HALT/Special Cycle

Cycle Name

BE3# - BE0#

A4-A2

Shutdown 1110

000

HALT 1011 000

Stop Grant bus cycle

1011

100

LOCK#

Bus Lock

indicates that the current bus cycle is locked. The Embedded Write-

Back Enhanced IntelDX4 processor does not allow a bus hold when LOCK# is
asserted (address holds are allowed). LOCK# goes active in the first clock of the
first locked bus cycle and goes inactive after the last clock of the last locked bus
cycle. The last locked cycle ends when Ready is returned. LOCK# is active LOW
and not driven during bus hold. Locked read cycles are not transformed into cache
fill cycles when KEN# is returned active.

PLOCK#

Pseudo-Lock indicates that the current bus transaction requires more than one
bus cycle to complete. For the Embedded Write-Back Enhanced IntelDX4
processor, examples of such operations are segment table descriptor reads (64
bits) and cache line fills (128 bits). For Intel486 processors with on-chip Floating-
Point Unit, floating-point long reads and writes (64 bits) also require more than one
bus cycle to complete.

The Embedded Write-Back Enhanced IntelDX4 processor drives PLOCK# active
until the addresses for the last bus cycle of the transaction are driven, regardless of
whether RDY# or BRDY# have been returned.

Normally PLOCK# and BLAST# are inverse of each other. However, during the
first bus cycle of a 64-bit floating-point write (for Intel486 processors with on-chip
Floating-Point Unit) both PLOCK# and BLAST# are asserted.

PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be
sampled only in the clock in which Ready is returned. PLOCK# is active LOW and
is not driven during bus hold.

BUS CONTROL

ADS#

Address Status

output indicates that a valid bus cycle definition and address are

available on the cycle definition lines and address bus. ADS# is driven active in the
same clock in which the addresses are driven. ADS# is active LOW and not driven
during bus hold.

Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 2 of 8)

Symbol

Type

Name and Function

Embedded Write-Back Enhanced IntelDX4TM Processor

RDY#

Non-burst Ready

input indicates that the current bus cycle is complete. RDY#

indicates that the external system has presented valid data on the data pins in
response to a read or that the external system has accepted data from the
Embedded Write-Back Enhanced IntelDX4 processor in response to a write. RDY#
is ignored when the bus is idle and at the end of the first clock of the bus cycle.

RDY# is active during address hold. Data can be returned to the Embedded Write-
Back Enhanced IntelDX4 processor while AHOLD is active.

RDY# is active LOW and is not provided with an internal pull-up resistor. RDY#
must satisfy setup and hold times t

and t

for proper chip operation.

BURST CONTROL

BRDY#

Burst Ready

input performs the same function during a burst cycle that RDY#

performs during a non-burst cycle. BRDY# indicates that the external system has
presented valid data in response to a read or that the external system has
accepted data in response to a write. BRDY# is ignored when the bus is idle and at
the end of the first clock in a bus cycle.

BRDY# is sampled in the second and subsequent clocks of a burst cycle. Data
presented on the data bus is strobed into the Embedded Write-Back Enhanced
IntelDX4 processor when BRDY# is sampled active. If RDY# is returned simulta-
neously with BRDY#, BRDY# is ignored and the burst cycle is prematurely
aborted.

BRDY# is active LOW and is provided with a small pull-up resistor. BRDY# must
satisfy the setup and hold times t

and t

BLAST#

Burst Last

signal indicates that the next time BRDY# is returned, the burst bus

cycle is complete. BLAST# is active for both burst and non-burst bus cycles.
BLAST# is active LOW and is not driven during bus hold.

INTERRUPTS

RESET

Reset input forces the Embedded Write-Back Enhanced IntelDX4 processorto
begin execution at a known state. The processor cannot begin executing instruc-
tions until at least 1 ms after V

, and CLK have reached their proper DC and AC

specifications. The RESET pin must remain active during this time to ensure
proper processor operation. However, for warm resets, RESET should remain
active for at least 15 CLK periods. RESET is active HIGH. RESET is asynchronous
but must meet setup and hold times t

and t

for recognition in any specific clock.

INTR

Maskable Interrupt

indicates that an external interrupt has been generated. When

the internal interrupt flag is set in EFLAGS, active interrupt processing is initiated.
The Embedded Write-Back Enhanced IntelDX4 processorgenerates two locked
interrupt acknowledge bus cycles in response to the INTR pin going active. INTR
must remain active until the interrupt acknowledges have been performed to
ensure processor recognition of the interrupt.

INTR is active HIGH and is not provided with an internal pull-down resistor. INTR is
asynchronous, but must meet setup and hold times t

and t

for recognition in

any specific clock.

NMI

Non-Maskable Interrupt

request signal indicates that an external non-maskable

interrupt has been generated. NMI is rising-edge sensitive and must be held LOW
for at least four CLK periods before this rising edge. NMI is not provided with an
internal pull-down resistor. NMI is asynchronous, but must meet setup and hold
times t

and t

for recognition in any specific clock.

Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 3 of 8)

Symbol

Type

Name and Function

Embedded Write-Back Enhanced IntelDX4TM Processor

SRESET

Soft Reset pin duplicates all functionality of the RESET pin except that the
SMBASE register retains its previous value. For soft resets, SRESET must remain
active for at least 15 CLK periods. SRESET is active HIGH. SRESET is
asynchronous but must meet setup and hold times t

and t

for recognition in any

specific clock.

SMI#

System Management Interrupt input invokes System Management Mode (SMM).
SMI# is a falling-edge triggered signal which forces the Embedded Write-Back
Enhanced IntelDX4 processorinto SMM at the completion of the current instruction.
SMI# is recognized on an instruction boundary and at each iteration for repeat
string instructions. SMI# does not break LOCKed bus cycles and cannot interrupt a
currently executing SMM. The Embedded Write-Back Enhanced IntelDX4 proces-
sorlatches the falling edge of one pending SMI# signal while it is executing an
existing SMI#. The nested SMI# is not recognized until after the execution of a
Resume (RSM) instruction.

SMIACT#

System Management Interrupt Active, an active LOW output, indicates that the
Embedded Write-Back Enhanced IntelDX4 processoris operating in SMM. It is
asserted when the processor begins to execute the SMI# state save sequence and
remains active LOW until the processor executes the last state restore cycle out of
SMRAM.

STPCLK#

Stop Clock Request input signal indicates a request was made to turn off or
change the CLK input frequency. When the Embedded Write-Back Enhanced
IntelDX4 processorrecognizes a STPCLK#, it stops execution on the next
instruction boundary (unless superseded by a higher priority interrupt), empties all
internal pipelines and write buffers, and generates a Stop Grant bus cycle.
STPCLK# is active LOW. STPCLK# must be pulled high via a 10-KW pullup
resistor. STPCLK# is an asynchronous signal, but must remain active until
the Embedded Write-Back Enhanced IntelDX4 processor issues the Stop
Grant bus cycle. STPCLK# may be de-asserted at any time after the
processor has issued the Stop Grant bus cycle.

BUS ARBITRATION

BREQ

Bus Request

signal indicates that the Embedded Write-Back Enhanced IntelDX4

processorhas internally generated a bus request. BREQ is generated whether or
not the processor is driving the bus. BREQ is active HIGH and is never floated.

HOLD

Bus Hold Request allows another bus master complete control of the Embedded
Write-Back Enhanced IntelDX4 processorbus. In response to HOLD going active,
the processor floats most of its output and input/output pins. HLDA is asserted after
completing the current bus cycle, burst cycle or sequence of locked cycles. The
Embedded Write-Back Enhanced IntelDX4 processorremains in this state until
HOLD is de-asserted. HOLD is active HIGH and is not provided with an internal
pull-down resistor. HOLD must satisfy setup and hold times t

and t

for proper

operation.

HLDA

Hold Acknowledge

goes active in response to a hold request presented on the

HOLD pin. HLDA indicates that the Embedded Write-Back Enhanced IntelDX4
processor has given the bus to another local bus master. HLDA is driven active in
the same clock that the processor floats its bus. HLDA is driven inactive when
leaving bus hold. HLDA is active HIGH and remains driven during bus hold.

Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 4 of 8)

Symbol

Type

Name and Function

Embedded Write-Back Enhanced IntelDX4TM Processor

BOFF#

Backoff

input forces the Embedded Write-Back Enhanced IntelDX4 processor to

float its bus in the next clock. The processor floats all pins normally floated during
bus hold but HLDA is not asserted in response to BOFF#. BOFF# has higher
priority than RDY# or BRDY#; if both are returned in the same clock, BOFF# takes
effect. The Embedded Write-Back Enhanced IntelDX4 processor remains in bus
hold until BOFF# is negated. If a bus cycle is in progress when BOFF# is asserted
the cycle is restarted. BOFF# is active LOW and must meet setup and hold times
t

and t

for proper operation.

CACHE INVALIDATION

AHOLD

Address Hold

request allows another bus master access to the Embedded Write-

Back Enhanced IntelDX4 processor's address bus for a cache invalidation cycle.
The processor stops driving its address bus in the clock following AHOLD going
active. Only the address bus is floated during address hold, the remainder of the
bus remains active. AHOLD is active HIGH and is provided with a small internal
pull-down resistor. For proper operation, AHOLD must meet setup and hold times
t

and t

EADS#

External Address - This signal indicates that a

valid

external address has been

driven onto the Embedded Write-Back Enhanced IntelDX4 processor address pins.
This address is used to perform an internal cache invalidation cycle. EADS# is
active LOW and is provided with an internal pull-up resistor. EADS# must satisfy
setup and hold times t

and t

for proper operation.

CACHE CONTROL

KEN#

Cache Enable

pin is used to determine whether the current cycle is cacheable.

When the Embedded Write-Back Enhanced IntelDX4 processorgenerates a cycle
that can be cached and KEN# is active one clock before RDY# or BRDY# during
the first transfer of the cycle, the cycle becomes a cache line fill cycle. Returning
KEN# active one clock before RDY# during the last read in the cache line fill
causes the line to be placed in the on-chip cache. KEN# is active LOW and is
provided with a small internal pull-up resistor. KEN# must satisfy setup and hold
times t

and t

for proper operation.

FLUSH#

Cache Flush

input forces the Embedded Write-Back Enhanced IntelDX4

processorto flush its entire internal cache. FLUSH# is active LOW and need only
be asserted for one clock. FLUSH# is asynchronous but setup and hold times t

and t

must be met for recognition in any specific clock.

PAGE CACHEABILITY

PWT

PCD

O
O

Page Write-Through

and Page Cache Disable pins reflect the state of the page

attribute bits, PWT and PCD, in the page table entry, page directory entry or
control register 3 (CR3) when paging is enabled. When paging is disabled, the
Embedded Write-Back Enhanced IntelDX4 processorignores the PCD and PWT
bits and assumes they are zero for the purpose of caching and driving PCD and
PWT pins. PWT and PCD have the same timing as the cycle definition pins (M/IO#,
D/C#, and W/R#). PWT and PCD are active HIGH and are not driven during bus
hold. PCD is masked by the cache disable bit (CD) in Control Register 0.

Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 5 of 8)

Symbol

Type

Name and Function

Embedded Write-Back Enhanced IntelDX4TM Processor

BUS SIZE CONTROL

BS16#

BS8#

I
I

Bus Size 16

and Bus Size 8

pins (bus sizing pins) cause the Embedded Write-

Back Enhanced IntelDX4 processor to run multiple bus cycles to complete a
request from devices that cannot provide or accept 32 bits of data in a single cycle.
The bus sizing pins are sampled every clock. The processor uses the state of
these pins in the clock before Ready to determine bus size. These signals are
active LOW and are provided with internal pull-up resistors. These inputs must
satisfy setup and hold times t

and t

for proper operation.

ADDRESS MASK

A20M#

Address Bit 20 Mask pin, when asserted, causes the Embedded Write-Back
Enhanced IntelDX4 processorto mask physical address bit 20 (A20) before
performing a lookup to the internal cache or driving a memory cycle on the bus.
A20M# emulates the address wraparound at 1 Mbyte, which occurs on the 8086
processor. A20M# is active LOW and should be asserted only when the
Embedded Write-Back Enhanced IntelDX4 processoris in real mode. This pin is
asynchronous but should meet setup and hold times t

and t

for recognition in

any specific clock. For proper operation, A20M# should be sampled HIGH at the
falling edge of RESET.

TEST ACCESS PORT

TCK

Test Clock, an input to the Embedded Write-Back Enhanced IntelDX4 processor,
provides the clocking function required by the JTAG Boundary scan feature. TCK
is used to clock state information (via TMS) and data (via TDI) into the component
on the rising edge of TCK. Data is clocked out of the component (via TDO) on the
falling edge of TCK. TCK is provided with an internal pull-up resistor.

TDI

Test Data Input is the serial input used to shift JTAG instructions and data into the
processor. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and
SHIFT-DR Test Access Port (TAP) controller states. During all other TAP controller
states, TDI is a "don't care." TDI is provided with an internal pull-up resistor.

TDO

Test Data Output is the serial output used to shift JTAG instructions and data out
of the component. TDO is driven on the falling edge of TCK during the SHIFT-IR
and SHIFT-DR TAP controller states. At all other times TDO is driven to the high
impedance state.

TMS

Test Mode Select is decoded by the JTAG TAP to select test logic operation. TMS
is sampled on the rising edge of TCK. To guarantee deterministic behavior of the
TAP controller, TMS is provided with an internal pull-up resistor.

NUMERIC ERROR REPORTING

FERR#

The Floating Point Error pin is driven active when a floating point error occurs.
FERR# is similar to the ERROR# pin on the Intel387TM Math CoProcessor. FERR#
is included for compatibility with systems using DOS type floating point error
reporting. FERR# will not go active if FP errors are masked in FPU register.
FERR# is active LOW, and is not floated during bus hold.

Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 6 of 8)

Symbol

Type

Name and Function

Embedded Write-Back Enhanced IntelDX4TM Processor

IGNNE#

When the Ignore Numeric Error pin is asserted the processor will ignore a
numeric error and continue executing non-control floating point instructions, but
FERR# will still be activated by the processor. When IGNNE# is de-asserted the
processor will freeze on a non-control floating point instruction, if a previous
floating point instruction caused an error. IGNNE# has no effect when the NE bit in
control register 0 is set. IGNNE# is active LOW and is provided with a small
internal pull-up resistor. IGNNE# is asynchronous but setup and hold times t

and

must be met to ensure recognition on any specific clock.

WRITE-BACK ENHANCED MODE

CACHE#

The CACHE# output indicates internal cacheability on read cycles and burst write-
back on write cycles. CACHE# is asserted for cacheable reads, cacheable code
fetches and write-backs. It is driven inactive for non-cacheable reads, I/O cycles,
special cycles, and write-through cycles.

FLUSH#

Cache FLUSH# is an existing pin that operates differently if the processor is
configured as Enhanced Bus mode (write-back). FLUSH# causes the processor to
write back all modified lines and flush (invalidate) the cache. FLUSH# is
asynchronous, but must meet setup and hold times t

and t

for recognition in any

specific clock.

HITM#

The Hit/Miss to a Modified Line pin is a cache coherency protocol pin that is
driven only in Enhanced Bus mode. When a snoop cycle is run, HITM# indicates
that the processor contains the snooped line and that the line has been modified.
Assertion of HITM# implies that the line will be written back in its entirety, unless
the processor is already in the process of doing a replacement write-back of the
same line.

INV

The Invalidation Request pin is a cache coherency protocol pin that is used only
in the Enhanced Bus mode. It is sampled by the processor on EADS#-driven
snoop cycles. It is necessary to assert this pin to get the effect of the processor
invalidate cycle on write-through-only lines. INV also invalidates the write-back
lines. However, if the snooped line is modified, the line will be written back and
then invalidated. INV must satisfy setup and hold times t

and t

for proper

operation.

PLOCK#

In the Enhanced bus mode, Pseudo-Lock Output is always driven inactive. In this
mode, a 64-bit data read (caused by an FP operand access or a segment
descriptor read) is treated as a multiple cycle read request, which may be a burst
or a non-burst access based on whether BRDY# or RDY# is returned by the
system. Because only write-back cycles (caused by snoop write-back or
replacement write-back) are write burstable, a 64-bit write will be driven out as two
non-burst bus cycles. BLAST# is asserted during both writes.

SRESET

For the Embedded Write-Back Enhanced IntelDX4 processor, Soft RESET
operates similar to other the Intel486 processors. On SRESET, the internal
SMRAM base register retains its previous value, does not flush, write-back or
disable the internal cache. Because SRESET is treated as an interrupt, it is
possible to have a bus cycle while SRESET is asserted. SRESET is serviced only
on an instruction boundary. SRESET is asynchronous but must meet setup and
hold times t

and t

for recognition in any specific clock.

Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 7 of 8)

Symbol

Type

Name and Function

Embedded Write-Back Enhanced IntelDX4TM Processor

WB/WT#

The Write-Back/Write-Through pin enables Enhanced Bus mode (write-back
cache). It also defines a cached line as write-through or write-back. For cache
configuration, WB/WT# must be valid during RESET and be active for at least two
clocks before and two clocks after RESET is de-asserted. To define write-back or
write-through configuration of a line, WB/WT# is sampled in the same clock as the
first RDY# or BRDY# is returned during a line fill (allocation) cycle.

CLKMUL, VCC5, AND VOLDET

CLKMUL

The Clock Multiplier input, defined during device RESET, defines the ratio of
internal core frequency to external bus frequency. If sampled low, the core
frequency operates at twice the external bus frequency (speed doubled mode). If
driven high, speed triple mode is selected. CLKMUL has an internal pull-up speed
to V

. A 10-K

pullup resistor is recommended when the pin is tied high.

CC5

The 5V reference voltage

input is the reference voltage for the 5V-tolerant I/O

buffers. This signal should be connected to +5V ±5% for use with 5V logic. If all
inputs are from 3V logic, this pin should be connected to 3.3V.

VOLDET

A Voltage Detect signal allows external system logic to distinguish between a 5V
Intel486 processor and the 3.3V IntelDX4 processor. This signal is active LOW for
a 3.3V IntelDX4 processor. This pin is available only on the PGA version of the
Embedded Write-Back Enhanced IntelDX4 processor.

RESERVED PINS

RESERVED#

Reserved is reserved for future use. This pin MUST be connected to an external
pull-up resistor circuit. The recommended resistor value is 10 kOhms. The pull-up
resistor must be connected only to the RESERVED# pin. Do not share this
resistor with other pins requiring pull-ups.

Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 8 of 8)

Symbol

Type

Name and Function

Embedded Write-Back Enhanced IntelDX4TM Processor

Table 9. Output Pins

Name

Active Level

Output Signal

Floated During

Address Hold

Floated During

Bus Hold

During Stop Grant and

Stop Clock States

BREQ

HIGH

Previous State

HLDA

HIGH

As per HOLD

BE3#-BE0#

LOW

Previous State

PWT, PCD

HIGH

Previous State

W/R#, M/IO#, D/C#

HIGH/LOW

Previous State

LOCK#

LOW

HIGH (inactive)

PLOCK#

LOW

HIGH (inactive)

ADS#

LOW

HIGH (inactive)

BLAST#

LOW

Previous State

PCHK#

LOW

Previous State

FERR#

LOW

Previous State

A3-A2

HIGH

Previous State

SMIACT#

LOW

Previous State

CACHE#

LOW

HIGH

HITM#

LOW

HIGH

VOLDET

LOW

NOTES:

1. The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the pro-

cessor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.

2. For the case of snoop cycles (via EADS#) during Stop Grant state, CACHE# and HITM# can go active depending on the

snoop hit in the internal cache.

Table 10. Input/Output Pins

Name

Active Level

Output Signal

Floated During

Address Hold

Floated During

Bus Hold

During Stop Grant and

Stop Clock States

D31-D0

HIGH

Floated

DP3DP0

HIGH

Floated

A31-A4

HIGH

Previous State

NOTE:

The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the

processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.

Embedded Write-Back Enhanced IntelDX4TM Processor

Table 11. Test Pins

Name

Input or Output

Sampled/ Driven On

TCK

Input

N/A

TDI

Input

Rising Edge of TCK

TDO

Output

Failing Edge of TCK

TMS

Input

Rising Edge of TCK

Table 12. Input Pins (Sheet 1 of 2)

Name

Active Level

Synchronous/

Asynchronous

Internal Pull-Up/

Pull-Down

CLK

RESET

HIGH

Asynchronous

SRESET

HIGH

Asynchronous

Pull-Down

HOLD

HIGH

Synchronous

AHOLD

HIGH

Synchronous

Pull-Down

EADS#

LOW

Synchronous

Pull-Up

BOFF#

LOW

Synchronous

Pull-Up

FLUSH#

LOW

Asynchronous

Pull-Up

A20M#

LOW

Asynchronous

Pull-Up

BS16#, BS8#

LOW

Synchronous

Pull-Up

KEN#

LOW

Synchronous

Pull-Up

RDY#

LOW

Synchronous

BRDY#

LOW

Synchronous

Pull-Up

INTR

HIGH

Asynchronous

NMI

HIGH

Asynchronous

IGNNE#

LOW

Asynchronous

Pull-Up

RESERVED#

LOW

Asynchronous

Pull-Up

SMI#

LOW

Asynchronous

Pull-Up

STPCLK#

LOW

Asynchronous

Pull-Up

INV

HIGH

Synchronous

Pull-Up

NOTE:

1. Even though STPCLK# and CLKMUL have internal pull-up resistors, they cannot be left floating. An external 10-K

pull-

up resistor is needed if the STPCLK# pin is unused. CLKMUL must be driven to a valid logic level. If tied HIGH, an external
10-K

pull-up resistor is recommended.

Embedded Write-Back Enhanced IntelDX4TM Processor

WB/WT#

HIGH/LOW

Synchronous

Pull-Down

CLKMUL

HIGH

Pull-Up

TCK

HIGH

Pull-Up

TDI

HIGH

Pull-Up

TMS

HIGH

Pull-Up

Table 12. Input Pins (Sheet 2 of 2)

Name

Active Level

Synchronous/

Asynchronous

Internal Pull-Up/

Pull-Down

NOTE:

1. Even though STPCLK# and CLKMUL have internal pull-up resistors, they cannot be left floating. An external 10-K

pull-

up resistor is needed if the STPCLK# pin is unused. CLKMUL must be driven to a valid logic level. If tied HIGH, an external
10-K

pull-up resistor is recommended.

4.0

ARCHITECTURAL AND
FUNCTIONAL OVERVIEW

The Embedded Write-Back Enhanced IntelDX4
processor architecture is essentially the same as the
IntelDX4 processor. Refer to the

Embedded

Intel486TM Processor Family Developer's Manual

(273021)

The Embedded Write-Back Enhanced IntelDX4
processor has one pin reserved for possible future
use. This pin, an input signal, is called RESERVED#
and must be connected to a 10-K

pull-up resistor.

The pull-up resistor must be connected only to the
RESERVED# pin. Do not share this resistor with
other pins requiring pull-ups.

4.1

CPUID Instruction

The Embedded Write-Back Enhanced IntelDX4
processor supports the CPUID instruction (see Table
13). Because not all Intel processors support the
CPUID instruction, a simple test can determine if the
instruction is supported. The test involves the

processor's ID Flag, which is bit 21 of the EFLAGS
register. If software can change the value of this flag,
the CPUID instruction is available. The actual state
of the ID Flag bit is irrelevant and provides no signifi-
cance to the hardware. This bit is cleared (reset to
zero) upon device reset (RESET or SRESET) for
compatibility with Intel486 processor designs that do
not support the CPUID instruction.

CPUID-instruction details are provided here for the
Embedded Write-Back Enhanced IntelDX4
processor. Refer to Intel Application Note AP-485

Intel Processor Identification with the CPUID
Instruction

(Order No. 241618) for a description that

covers all aspects of the CPUID instruction and how
it pertains to other Intel processors.

4.1.1

Operation of the CPUID Instruction

The CPUID instruction requires the software
developer to pass an input parameter to the
processor in the EAX register. The processor
response is returned in registers EAX, EBX, EDX,
and ECX.

Table 13. CPUID Instruction Description

OP CODE

Instruction

Processor

Core Clocks

Parameter passed in

EAX

(Input Value)

Description

0F A2

CPUID

Vendor (Intel) ID String

Processor Identification

> 1

Undefined (Do Not Use)

Embedded Write-Back Enhanced IntelDX4TM Processor

Vendor ID String - When the parameter passed in EAX is 0 (zero), the register values returned upon
instruction execution are shown in the following table.

The values in EBX, EDX and ECX indicate an Intel processor. When taken in the proper order, they decode to
the string "

GenuineIntel

The state of the WB/WT# input pin is sampled by the processor on the falling edge of the RESET signal. If
WB/WT# is LOW, the processor is configured to operate in Write-Through/Standard Bus mode. If HIGH, it is
configured to operate in Write-Back/Enhanced Bus mode. The value of the "Model" field of the processor
signature register depends on the bus mode for which the processor is configured.

Processor Identification - When the parameter passed to EAX is 1 (one), the register values returned upon
instruction execution are:

31-------------24

23-----------16

15--------------8

7--------------0

High Value (= 1)

EAX

0 0 0 0

0 0 0 1

Vendor ID String

EBX

(75)

(6E)

(65)

(47)

(ASCII

EDX

(49)

(65)

(6E)

(69)

Characters)

ECX

(6C)

(65)

(74)

(6E)

31---------------------------14

13,12

11----8

7----4

3----0

Processor

Signature for

Write-Through/Stan-

dard Bus mode

EAX

(Do Not Use)

Intel Reserved

0 0

Processor

Type

0 1 0 0

Family

1 0 0 0

Model

XXXX

Stepping

Processor

Signature for

Write-

Back/Enhanced Bus

mode

(Do Not Use)

Intel Reserved

0 0

Processor

Type

0 1 0 0

Family

1 0 0 1

Model

XXXX

Stepping

(Intel releases information about stepping numbers as needed)

31--------------------------------------------------------------------------------------------------0

Intel Reserved

EBX

Intel Reserved

(Do Not Use)

ECX

Intel Reserved

31----------------------------------------------------------------------------2

Feature Flags

EDX

0------------------------------------------------------------------------------0

VME

FPU

Embedded Write-Back Enhanced IntelDX4TM Processor

4.2

Identification After Reset

Processor Identification - Upon reset, the EDX register contains the processor signature:

4.3

Boundary Scan (JTAG)

4.3.1

Device Identification

Tables 14 and 15 show the 32-bit code for the Embedded Write-Back Enhanced IntelDX4 processor. This code
is loaded into the Device Identification Register.

31---------------------------14

13,12

11----8

7----4

3----0

Processor

Signature for

Write-Through/Stan-

dard Bus mode

EDX

(Do Not Use)

Intel Reserved

0 0

Processor

Type

0 1 0 0

Family

1 0 0 0

Model

XXXX

Stepping

Processor

Signature for

Write-

Back/Enhanced Bus

mode

(Do Not Use)

Intel Reserved

0 0

Processor

Type

0 1 0 0

Family

1 0 0 1

Model

XXXX

Stepping

(Intel releases information about stepping numbers as needed)

Table 14. Boundary Scan Component Identification Code (Write-Through/Standard Bus Mode)

Version

Part Number

Mfg ID

009H = Intel

1=3.3 V

Intel

Architecture

Type

Family

0100 = Intel486

CPU Family

Model

01000 =

Embedded Write-

Back Enhanced

IntelDX4 processor

31----28

26-----------21

20----17

16--------12

11------------1

XXXX

000001

0100

01000

00000001001

(Intel releases information about version numbers as needed)
Boundary Scan Component Identification Code = x828 8013 (Hex)

Embedded Write-Back Enhanced IntelDX4TM Processor

4.3.2

Boundary Scan Register Bits and Bit
Order

The boundary scan register contains a cell for each
pin as well as cells for control of bidirectional and
three-state pins. There are "Reserved" bits which
correspond to no-connect (N/C) signals of the
Embedded Write-Back Enhanced IntelDX4
processor. Control registers WRCTL, ABUSCTL,
BUSCTL, and MISCCTL are used to select the
direction of bidirectional or three-state output signal
pins. A "1" in these cells designates that the
associated bus or bits are floated if the pins are
three-state, or selected as input if they are bidirec-
tional.

· WRCTL controls D31-D0 and DP3DP0

· ABUSCTL controls A31-A2

· BUSCTL controls ADS#, BLAST#, PLOCK#,

LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#, M/IO#,
D/C#, PWT, PCD, and CACHE#

· MISCCTL controls PCHK#, HLDA, BREQ, and

HITM#

The following is the bit order of the Embedded Write-
Back Enhanced IntelDX4 processor boundary scan
register:

Table 15. Boundary Scan Component Identification Code (Write-Back/Enhanced Bus Mode)

Version

Part Number

Mfg ID

009H = Intel

1=3.3 V

Intel

Architecture

Type

Family

0100 = Intel486

CPU Family

Model

01001 =

Embedded Write-

Back Enhanced

IntelDX4 processor

31----28

26-----------21

20----17

16--------12

11------------1

XXXX

000001

0100

01001

00000001001

(Intel releases information about version numbers as needed)

Boundary Scan Component Identification Code = x828 9013 (Hex)

TDO

A2, A3, A4, A5, RESERVED#, A6,
A7, A8, A9, A10, A11, A12, A13,
A14, A15, A16, A17, A18, A19,
A20, A21, A22, A23, A24, A25,
A26, A27, A28, A29, A30, A31,
DP0, D0, D1, D2, D3, D4, D5, D6,
D7, DP1, D8, D9, D10, D11, D12,
D13, D14, D15, DP2, D16, D17,
D18, D19, D20, D21, D22, D23,
DP3, D24, D25, D26, D27, D28,
D29, D30, D31, STPCLK#,
IGNNE#, INV, CACHE#, FERR#,
SMI#, WB/WT#, HITM#,
SMIACT#, SRESET, NMI, INTR,
FLUSH#, RESET, A20M#,
EADS#, PCD, PWT, D/C#, M/IO#,
BE3#, BE2#, BE1#, BE0#, BREQ,
W/R#, HLDA, CLK, AHOLD,
HOLD, KEN#, RDY#, CLKMUL,
BS8#, BS16#, BOFF#, BRDY#,
PCHK#, LOCK#, PLOCK#,
BLAST#, ADS#, MISCCTL,
BUSCTL, ABUSCTL, WRCTL

TDI

Embedded Write-Back Enhanced IntelDX4TM Processor

5.0

ELECTRICAL SPECIFICATIONS

5.1

Maximum Ratings

Table 16 is a stress rating only. Extended exposure
to the Maximum Ratings may affect device reliability.

Furthermore, although the Embedded Write-Back
Enhanced IntelDX4 processorcontains protective
circuitry to resist damage from electrostatic
discharge, always take precautions to avoid high
static voltages or electric fields.

Functional operating conditions are given in Section
5.2, DC Specifications and Section 5.3, AC Speci-
fications.

5.2

DC Specifications

The following tables show the operating supply
voltages, DC I/O specifications, and component
power consumption for the Embedded Write-Back
Enhanced IntelDX4 processor.

Table 16. Absolute Maximum Ratings

Case Temperature under
Bias

-65 °C to +110 °C

Storage Temperature

-65 °C to +150 °C

DC Voltage on Any Pin with
Respect to Ground

-0.5 V to V

CC5

+ 0.5 V

Supply Voltage V

with

Respect to V

-0.5 V to +4.6 V

Reference Voltage V

CC5

with

Respect to V

-0.5 V to +6.5 V

Transient Voltage on any
Input

The lesser of:

CC5

+ 1.6 V

6.5 V

Current Sink on V

CC5

55 mA

Table 17. Operating Supply Voltages

Product

FC80486DX4WB75

3.3 V

3 V

FC80486DX4WB100

3.3 V

3 V

A80486DX4WB100

3.3 V

3 V

Embedded Write-Back Enhanced IntelDX4TM Processor

Table 18. DC Specifications

Functional Operating Range: V

= 3.3 V

0.3 V; V

CC5

= 5 V

0.25 V (Note 1); T

CASE

=0 °C to +85 °C

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

Input LOW Voltage

-0.3

+0.8

Input HIGH Voltage

2.0

CC5

+0.3

Note 2

IHC

Input HIGH Voltage of CLK

CC5

-0.6

CC5

+0.3

Output LOW Voltage

= 4.0 mA (Address, Data, BE

)

= 5.0 mA (Definition, Control)

= 2.0 mA

= 100 µA

0.45

0.40

0.20

Output HIGH Voltage

= -2.0 mA

2.4

CC5

Leakage Current

300

µA

Note 3

Input Leakage Current

Note 4

Input Leakage Current

SRESET

200
300

Note 5
Note 5

Input Leakage Current

400

Note 6

Output Leakage Current

Input Capacitance

Note 7

OUT

I/O or Output Capacitance

Note 7

CLK

CLK Capacitance

Note 7

NOTES:

1. V

CC5

should be connected to 3.3 V

0.3 V in 3.3 V-only systems.

2. All inputs except CLK.

3. This parameter is for inputs without pull-up or pull-down resistors and 0V

4. This parameter is for V

CC5

2.25 V. Typical value is not 100% tested.

5. This parameter is for inputs with pull-down resistors and V

= 2.4V.

6. This parameter is for inputs with pull-up resistors and V

= 0.4V.

7. F

=1 MHz. Not 100% tested.

Embedded Write-Back Enhanced IntelDX4TM Processor

Table 19. I

Values

Functional Operating Range: V

= 3.3 V ±0.3 V; V

CC5

= 5 V

0.25 V (Note 1); T

CASE

= 0

C to +85

Parameter

Operating

Frequency

Typ.

Maximum

Notes

Active

(Power Supply)

75 MHz

100 MHz

1100 mA
1450 mA

Note 2

Active

(Thermal Design)

75 MHz

100 MHz

825 mA

1075 mA

975 mA

1300 mA

Notes 3, 4, 5

Stop Grant

75 MHz

100 MHz

20 mA
50 mA

75 mA

100 mA

Note 6

Stop Clock

0 MHz

600 µA

2 mA

Note 7

NOTES:

1. V

CC5

should be connected to 3.3 V

0.3 V in 3.3 V-only systems.

2. This parameter is for proper power supply selection. It is measured using the worst case instruction mix at V

= 3.6V.

3. The maximum current column is for thermal design power dissipation. It is measured using the worst case instruction mix

at V

= 3.3V.

4. The typical current column is the typical operating current in a system. This value is measured in a system using a typical

device at V

= 3.3V, running Microsoft Windows 3.1 at an idle condition. This typical value is dependent upon the specific

system configuration.

5. Typical values are not 100% tested.

6. The I

Stop Grant specification refers to the I

value once the Embedded Write-Back Enhanced IntelDX4 processor

enters the Stop Grant or Auto HALT Power Down state.

7. The I

Stop Clock specification refers to the I

value once the Embedded Write-Back Enhanced IntelDX4 processor

enters the Stop Clock state. The V

and V

levels must be equal to V

and 0 V, respectively, in order to meet the I

Stop Clock specifications.

Embedded Write-Back Enhanced IntelDX4TM Processor

5.3

AC Specifications

The AC specifications for the Embedded Write-Back Enhanced IntelDX4 processor are given in this section.

Table 20. AC Characteristics

= 3.3 V ± 0.3 V; V

CC5

= 5 V

0.25 V (Note 1)

CASE

= 0

C to +85

C; C

= 50pF, unless otherwise specified. (Sheet 1 of 2)

Symbol

Parameter

Product

WB75

WB100

Min

Max

Min

Max

Unit

Figure

Notes

CLK Frequency

MHz

Note 2

CLK Period

125

CLK Period Stability

250

Adjacent

clocks

Note 3

CLK High Time

at 2V

CLK Low Time

at 0.8V

CLK Fall Time

2V to 0.8V

CLK Rise Time

0.8V to 2V

A31A2, PWT, PCD, BE3BE0#,
M/IO#, D/C#, W/R#, ADS#, LOCK#,
FERR#, CACHE#, HITM#, BREQ,
HLDA Valid Delay

A31A2, PWT, PCD, BE3BE0#,
M/IO#, D/C#, W/R#, ADS#, LOCK#,
CACHE# Float Delay

Note 3

PCHK# Valid Delay

BLAST#, PLOCK#, SMIACT# Valid
Delay

BLAST#, PLOCK# Float Delay

Note 3

D31D0, DP3DP0 Write Data Valid
Delay

D31D0, DP3DP0 Write Data Float
Delay

Note 3

EADS#, INV Setup Time

EADS#, INV Hold Time

KEN#, BS16#, BS8#, WB/WT# Setup
Time

KEN#, BS16#, BS8#, WB/WT# Hold
Time

RDY#, BRDY# Setup Time

RDY#, BRDY# Hold Time

Embedded Write-Back Enhanced IntelDX4TM Processor

HOLD, AHOLD Setup Time

18a

BOFF# Setup Time

HOLD, AHOLD, BOFF# Hold Time

FLUSH#, A20M#, NMI, INTR, SMI#,
STPCLK#, SRESET, RESET,
IGNNE# Setup Time

Note 4

FLUSH#, A20M#, NMI, INTR, SMI#,
STPCLK#, SRESET, RESET,
IGNNE# Hold Time

Note 4

D31D0, DP3DP0,
A31A4 Read Setup Time

6
5

D31D0, DP3DP0,
A31A4 Read Hold Time

6
5

NOTES:

1. V

CC5

should be connected to 3.3 V

0.3 V in 3.3 V-only systems.

2. 0-MHz operation is guaranteed when the STPCLK# and Stop Grant bus cycle protocol is used.

3. Not 100% tested, guaranteed by design characterization.

4. A reset pulse width of 15 CLK cycles is required for warm resets (RESET or SRESET). Power-up resets (cold resets)

require RESET to be asserted for at least 1 ms after V

and CLK are stable.

Table 20. AC Characteristics

= 3.3 V ± 0.3 V; V

CC5

= 5 V

0.25 V (Note 1)

CASE

= 0

C to +85

C; C

= 50pF, unless otherwise specified. (Sheet 2 of 2)

Symbol

Parameter

Product

WB75

WB100

Min

Max

Min

Max

Unit

Figure

Notes

Embedded Write-Back Enhanced IntelDX4TM Processor

Table 21. AC Specifications for the Test Access Port

= 3.3 V ±0.3 V; V

CC5

= 5 V

0.25 V (Note 1)

CASE

= 0

C to +85

C; C

= 50 pF

Symbol

Parameter

Min

Max

Unit

Figure

Notes

TCK Frequency

MHz

Note 2

TCK Period

TCK High Time

@ 2.0V

TCK Low Time

@ 0.8V

TCK Rise Time

Note 3

TCK Fall Time

Note 3

TDI, TMS Setup Time

Note 4

TDI, TMS Hold Time

Note 4

TDO Valid Delay

Note 4

TDO Float Delay

Note 4

All Outputs (except TDO) Valid Delay

Note 4

All Outputs (except TDO) Float Delay

Note 4

All Inputs (except TDI, TMS, TCK) Setup Time

Note 4

All Inputs (except TDI, TMS, TCK) Hold Time

Note 4

NOTES:

1. V

CC5

should be connected to 3.3 V

0.3 V in 3.3 V-only systems. All inputs and outputs are TTL level.

2. TCK period

CLK period.

3. Rise/Fall times are measured between 0.8V and 2.0V. Rise/Fall times can be relaxed by 1 ns per 10-ns increase in TCK

period.

4. Parameters t

are measured from TCK.

Embedded Write-Back Enhanced IntelDX4TM Processor

Table 23. Ceramic PGA Package Dimension Symbols

Letter or Symbol

Description of Dimensions

Distance from seating plane to highest point of body

Distance between seating plane and base plane (lid)

Distance from base plane to highest point of body

Distance from seating plane to bottom of body

Diameter of terminal lead pin

Largest overall package dimension of length

A body length dimension, outer lead center to outer lead center

Linear spacing between true lead position centerlines

Distance from seating plane to end of lead

Other body dimension, outer lead center to edge of body

NOTES:

1. Controlling dimension: millimeter.

2. Dimension "e

" ("e") is non-cumulative.

3. Seating plane (standoff) is defined by P.C. board hole size: 0.04150.0430 inch.

4. Dimensions "B", "B

" and "C" are nominal.

5. Details of Pin 1 identifier are optional.

6.2

Package Thermal Specifications

The Embedded Write-Back Enhanced IntelDX4
processoris specified for operation when the case
temperature (T

) is within the range of 0°C to 85°C.

may be measured in any environment to

determine whether the processor is within the
specified operating range.

The ambient temperature (T

) can be calculated

from

and

from the following equations:

= T

+ P *

= T

- P *

= T

+ P * [

]

= T

- P * [

]

Where T

, T

equals Junction, Ambient and

Case Temperature respectively.

equals

Junction-to-Case and Junction-to-Ambient thermal
Resistance, respectively. P is defined as Maximum
Power Consumption.

Values for

and

are given in the following

tables for each product at its maximum operating
frequencies. Maximum T

is shown for each product

operating at its maximum processor frequency (three
times the CLK frequency). Refer to the

Embedded

Intel486TM Processor Family Developer's Manual

(273021) for a description of the methods used to
measure these characteristics.

Embedded Write-Back Enhanced IntelDX4TM Processor

Table 24. Thermal Resistance,

(

C/W)

vs. Airflow -- ft/min. (m/sec)

Package

Heat
Sink

(0)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

1000

(5.07)

168-Pin PGA

17.5

15.0

13.0

11.5

10.0

9.5

168-Pin PGA

Yes

13.5

8.5

6.5

5.5

4.5

4.25

208-Lead SQFP

12.5

10.0

9.0

8.5

208-Lead SQFP

Yes

10.5

6.5

5.0

4.0

Table 25. Thermal Resistance,

(

C/W)

Package

Heat Sink

168-Pin PGA

2.0

168-Pin PGA

Yes

2.0

208-Lead SQFP

1.2

208-Lead SQFP

Yes

0.8

Table 26. Maximum T

ambient,

max (

Airflow -- ft/min. (m/sec)

Package

Heat Sink

Freq.

(MHz)

(0)

200

(1.01)

400

(2.03)

600

(3.04)

168-Pin PGA

100

18.5

29.0

37.5

44.0

168-Pin PGA

Yes

100

35.5

57.0

65.5

70.0

208-Lead SQFP

100

36.5

46.0

50.0

52.5

208-Lead SQFP

Yes

100

43.5

60.5

67.0

71.0

208-Lead SQFP

Yes

Document Outline

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Document Outline

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