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December 1990
COPYRIGHT
INTEL CORPORATION 1995
Order Number 240182-004
376
TM
HIGH PERFORMANCE
32-BIT EMBEDDED PROCESSOR
Y
Full 32-Bit Internal Architecture
8- 16- 32-Bit Data Types
8 General Purpose 32-Bit Registers
Extensive 32-Bit Instruction Set
Y
High Performance 16-Bit Data Bus
16 or 20 MHz CPU Clock
Two-Clock Bus Cycles
16 Mbytes Sec Bus Bandwidth
Y
16 Mbyte Physical Memory Size
Y
High Speed Numerics Support with the
80387SX
Y
Low System Cost with the 82370
Integrated System Peripheral
Y
On-Chip Debugging Support Including
Break Point Registers
Y
Complete Intel Development Support
C PL M Assembler
ICE
TM
-376 In-Circuit Emulator
iRMK Real Time Kernel
iSDM Debug Monitor
DOS Based Debug
Y
Extensive Third-Party Support
Languages C Pascal FORTRAN
BASIC and ADA
Hosts VMS
UNIX
MS-DOS
and
Others
Real-Time Kernels
Y
High Speed CHMOS IV Technology
Y
Available in 100 Pin Plastic Quad Flat-
Pack Package and 88-Pin Pin Grid Array
(See Packaging Outlines and Dimensions
231369)
INTRODUCTION
The 376 32-bit embedded processor is designed for high performance embedded systems It provides the
performance benefits of a highly pipelined 32-bit internal architecture with the low system cost associated with
16-bit hardware systems The 80376 processor is based on the 80386 and offers a high degree of compatibil-
ity with the 80386 All 80386 32-bit programs not dependent on paging can be executed on the 80376 and all
80376 programs can be executed on the 80386 All 32-bit 80386 language translators can be used for
software development With proper support software any 80386-based computer can be used to develop and
test 80376 programs In addition any 80386-based PC-AT compatible computer can be used for hardware
prototyping for designs based on the 80376 and its companion product the 82370
240182 48
80376 Microarchitecture
Intel iRMK ICE 376 386 Intel386 iSDM Intel1376 are trademarks of Intel Corp
UNIX is a registered trademark of AT T
ADA is a registered trademark of the U S Government Ada Joint Program Office
PC-AT is a registered trademark of IBM Corporation
VMS is a trademark of Digital Equipment Corporation
MS-DOS is a trademark of MicroSoft Corporation
376 EMBEDDED PROCESSOR
The following table lists a brief description of each pin on the 80376 The following definitions are used in
these descriptions
The named signal is active LOW
I
Input signal
O
Output signal
I O
Input and Output signal
No electrical connection
Symbol
Type
Name and Function
CLK2
I
CLK2
provides the fundamental timing for the 80376 For additional
information see Clock in Section 4 1
RESET
I
RESET
suspends any operation in progress and places the 80376 in a
known reset state See Interrupt Signals in Section 4 1 for additional
information
D
15
D
0
I O
DATA BUS
inputs data during memory I O and interrupt acknowledge
read cycles and outputs data during memory and I O write cycles See
Data Bus
in Section 4 1 for additional information
A
23
A
1
O
ADDRESS BUS
outputs physical memory or port I O addresses See
Address Bus
in Section 4 1 for additional information
W R
O
WRITE READ
is a bus cycle definition pin that distinguishes write
cycles from read cycles See Bus Cycle Definition Signals in Section
4 1 for additional information
D C
O
DATA CONTROL
is a bus cycle definition pin that distinguishes data
cycles either memory or I O from control cycles which are interrupt
acknowledge halt and instruction fetching See Bus Cycle Definition
Signals
in Section 4 1 for additional information
M IO
O
MEMORY I O
is a bus cycle definition pin that distinguishes memory
cycles from input output cycles See Bus Cycle Definition Signals in
Section 4 1 for additional information
LOCK
O
BUS LOCK
is a bus cycle definition pin that indicates that other
system bus masters are denied access to the system bus while it is
active See Bus Cycle Definition Signals in Section 4 1 for additional
information
ADS
O
ADDRESS STATUS
indicates that a valid bus cycle definition and
address (W R D C M IO BHE BLE and A
23
A
1
) are being driven at
the 80376 pins See Bus Control Signals in Section 4 1 for additional
information
NA
I
NEXT ADDRESS
is used to request address pipelining See Bus
Control Signals
in Section 4 1 for additional information
READY
I
BUS READY
terminates the bus cycle See Bus Control Signals in
Section 4 1 for additional information
BHE BLE
O
BYTE ENABLES
indicate which data bytes of the data bus take part in
a bus cycle
See Address Bus in Section 4 1 for additional
information
HOLD
I
BUS HOLD REQUEST
input allows another bus master to request
control of the local bus See Bus Arbitration Signals in Section 4 1
for additional information
5
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