Key Features
N Auto-selectable LVD or single-ended termination
N 3.0pF maximum disabled output capacitance
N Fast response, no external capacitors required
N Compatible with active negation drivers
N 15A supply current in disconnect mode
N Logic command disconnects all termination lines
N DIFFSENSE line driver
N Ground driver integrated for single-ended
operation
N Current limit and thermal protection
N Hot-swap compatible (single-ended)
N Compatible with SCSI 1, 2, 3, FAST-20, and the
pending SPI-2 LVD
N Pin compatible with DS2118, UCC5630 and
LX5241/42/43
Block Diagram
9-Line Multimode L
9-Line Multimode L
VD/SE
VD/SE
SCSI T
SCSI T
er
er
minat
minat
or
or
The IMP5241/42/43 is a multimode SCSI terminator that conforms to the
SCSI Parallel Interconnect-2 (SPI-2) specification developed by the T10
standards committee for low voltage differential (LVD) termination,
while providing backwards compatibility to the SCSI, SCSI-2, and SPI
single-ended specifications. Multimode compatibility permits the use of
legacy devices on the bus without hardware alterations. Automatic mode
selection is achieved through voltage detection on the diffsense line.
The IMP5241/42/43 delivers the ultimate in SCSI bus performance while
saving component cost and board area. Elimination of the external capac-
itors also mitigates the need for a lengthy capacitor selection process. The
individual high bandwidth drivers also maximize channel separation
and reduce channel to channel noise and cross talk. The high bandwidth
architecture insures ULTRA2 performance while providing a clear migra-
tion path to ULTRA3 and beyond.
When the IMP5241/42/43 is enabled, the differential sense (DIFFSENSE)
pin supplies a voltage between 1.2V and 1.4V. In application, this pin is
tied to the DIFFSENSE input of the corresponding LVD transceivers. This
action enables the LVD transceiver function. DIFFSENSE is capable of
supplying a maximum of 15mA. Tying the DIFFSENSE pin HIGH places
the IMP5241/42/43 in a high impedance state indicating the presence of
an HVD device. Tying the pin LOW places the part in a single-ended
mode while also signaling the multimode transceiver to operate in a sin-
gle-ended mode.
Recognizing the needs of portable and configurable peripherals, the
IMP5241/42/43 have a TTL compatible sleep/disable mode. During this
sleep/disable mode, power dissipation is reduced to a
meager 15
A while also placing all outputs in a high
impedance state. Also during sleep/disable mode, the
DIFFSENSE function is disabled and is placed in a high
impedance state.
Another key feature of the IMP5241/42/43 is the mas-
ter/slave function. Driving this pin HIGH or floating the
pin enables the 1.3V DIFFSENSE reference. Driving the pin
LOW disables the on board DIFFSENSE reference and
enables use of an external master reference device.
Power ON & MODE Delay
Internal V
REF
1.30V
LVD
1.25V
200
52.5
1.07mA
1.07mA
20
52.5
SE
2.2V
Power ON
Power ON
SE 2.85V, 22.5mA
Latch
SE
DISC/HVD
LVD
SE
LVD(-) / SE
1 of 9
LVD(+) / SE
(Pseudo-GND)
SE
HVD
LVD
HVD
DIFF B
DIFFSENSE
M/S
DISCONNECT
(IMP5241)
DISCONNECT
(IMP5242)
V
TERM
LVD
Window
Comp.
LVD
SE
10mA
HVD
20k
MODE Control & Delay
5241/42_01.eps
1
IMP52
IMP52
4
4
1/42/43
1/42/43
2001 IMP, Inc.
Data Communications 1
D
ATA
C
OMMUNICATIONS
2
408-432-9100/www.impweb.com
2001 IMP, Inc.
r
Ordering Information
Absolute Maximum Ratings
1
Thermal Data
Pin Configuration
1
2
3
4
36
35
34
33
5
6
7
8
32
31
30
29
9
10
11
12
NC
NC
NC
1+
1
2+
2
HEATSINK
HEATSINK
HEATSINK
3+
3
V
TERM
HVD
LVD
SE
9
9+
8
8+
HEATSINK
HEATSINK
HEATSINK
7
28
27
26
25
13
14
24
23
15
16
17
18
4+
4
5+
5
DISCONNECT
GND
6
7+
6+
DIFF B
DIFFSENSE
MASTER/SLAVE
22
21
20
19
5241/42_02.eps
IMP5241/42
DB Package
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . +7V
Operating Junction Temperature
Plastic (DB, PW Packages) . . . . . . . . . . . . . 150
C
Storage Temperature Range . . . . . . . . . . . . . . 65
C to 150C
Note:
1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to Ground. Currents are positive
into, negative out of the specified terminal.
Lead Temperature (Soldering, 10 sec.) . . . . . . 300
C
DB Package:
Thermal Resistance Junction-to-Ambient,
JA
. . . . . . 50
C/W
PW Package:
Thermal Resistance Junction-to-Ambient,
JA
. . . . . . 100
C/W
1
2
3
4
24
23
22
21
5
6
7
8
20
19
18
17
9
10
11
12
1+
1
2+
2
3+
3
4+
4
5+
5
DISCONNECT
GND
V
TERM
NC
9
9+
8
8+
7
7+
6
6+
DIFFSENSE
MASTER/SLAVE
16
15
14
13
5241/42_03.eps
IMP5241/42
DW Package
SSOP-36
TSSOP-24
1
2
3
4
28
27
26
25
5
6
7
8
NC
1+
1
2+
2
NC
3+
3
V
TERM
NC
9
9+
8
8+
NC
7
24
23
22
21
9
10
20
19
11
12
13
14
4+
4
5+
5
DISCONNECT
GND
6
7+
6+
DIFF B
DIFFSENSE
MASTER/SLAVE
18
17
16
15
5243_02.eps
IMP5243
TSSOP-28
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x
JA
).
The
JA
numbers are guidelines for the thermal performance of
the device/pc-board system. No ambient airflow is assumed.
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IMP52
IMP52
4
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1/42/43
1/42/43
Pin Description
2001 IMP, Inc.
Data Communications
3
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1
IMP52
IMP52
4
4
1/42/43
1/42/43
4
408-432-9100/www.impweb.com
2001 IMP, Inc.
r
Unless otherwise specified, these specifications apply over the operating ambient temperature range of 0
C T
A
70C. TermPwr = 4.75V.
DISCONNECT: IMP5241 = LOW, DISCONNECT: IMP5242 = HIGH. Low duty cycle pulse testing techniques are used which maintain
junction and case temperatures equal to the ambient temperature.
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Recommended Operating Conditions
2
Electrical Characteristics
1
IMP52
IMP52
4
4
1/42/43
1/42/43
2001 IMP, Inc.
Data Communications
5
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5
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5
Electrical Characteristics
1
IMP52
IMP52
4
4
1/42/43
1/42/43
6
408-432-9100/www.impweb.com
2001 IMP, Inc.
r
IMP5241
IMP5241
5241/42_06.eps
+
+
Figure 1. Bus Voltage
Figure 2. V
OD
V
(+)
V
()
V
CM
5241/42_04.eps
V
OD
= V
()
V
(+)
, Logic = 0
NEGATED
100mV
100mV
0V
5241/42_05.eps
Figure 3.
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Table 1. MASTER/SLAVE Function Table
Table 2. DIFFSENSE/Power Up/Power Down Function Table
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Application Information
1
IMP52
IMP52
4
4
1/42/43
1/42/43
2001 IMP, Inc.
Data Communications
7
r
+
+
1
V
TERM
DISCONNECT
TERMPOWER
DISCONNECT
M/S
GND
1+
9
Data Lines (9)
Data Lines (9)
Data Lines (9)
9+
DIFFSENSE
DIFF B*
IMP5241/43
IMP5242
1
V
TERM
4.7
F
DISCONNECT
M/S
GND
1+
9
9+
DIFFSENSE
DIFF B*
IMP5241/43
IMP5242
1
V
TERM
DISCONNECT
M/S
GND
1+
9
9+
DIFFSENSE
DIFF B*
IMP5241/43
IMP5242
1
V
TERM
DISCONNECT
TERMPOWER
DISCONNECT
M/S
GND
1+
9
9+
DIFFSENSE
DIFF B*
IMP5241/43
IMP5242
HOST
PERIPHERAL
1
V
TERM
4.7
F
DISCONNECT
M/S
GND
1+
9
9+
DIFFSENSE
DIFF B*
IMP5241/43
IMP5242
1
V
TERM
DISCONNECT
M/S
GND
1+
9
9+
DIFFSENSE
DIFF B*
* The DIFF B pin is not present on the IMP5241/5242 24-pin PW package.
The DIFFSENS signal must be connected to the DIFFSENSE pin on the PW package.
IMP5241/43
IMP5242
5241/42_07.eps
Figure 4. IMP Terminator Application Schematic
Application Information
1
IMP52
IMP52
4
4
1/42/43
1/42/43
8
408-432-9100/www.impweb.com
2001 IMP, Inc.
r
Application Information
1
V
TERM
DISCONNECT
TERMPOWER
DISCONNECT
M/S
GND
NC*
NC*
Pin 1
1+
9
Data Lines (9)
Data Lines (9)
Data Lines (9)
9+
DIFFSENSE
DIFF B*
20k
IMP5241/43
IMP5242
1
V
TERM
4.7
F
DISCONNECT
M/S
GND
1+
9
9+
DIFFSENSE
DIFF B*
IMP5241/43
IMP5242
1
V
TERM
DISCONNECT
M/S
GND
1+
9
9+
DIFFSENSE
DIFF B*
IMP5241/43
IMP5242
1
V
TERM
DISCONNECT
TERMPOWER
DISCONNECT
M/S
GND
1+
9
9+
DIFFSENSE
DIFF B*
IMP5241/43
IMP5242
HOST
PERIPHERAL
1
V
TERM
4.7
F
DISCONNECT
M/S
GND
1+
9
9+
DIFFSENSE
DIFF B*
IMP5241/43
IMP5242
1
V
TERM
DISCONNECT
M/S
GND
1+
9
9+
DIFFSENSE
DIFF B*
* The capacitor on pin 1 can be placed on the IMP5241CDB, IMP5242CDB or the IMP5243CPW to be pin compatible with other devices.
This V
REG
/REF capacitor is not required with IMP devices.
IMP5241/43
IMP5242
5241/42_08.eps
+
+
4.7
F*
+
Pin 1
4.7
F*
+
0.1
F
+
0.1
F
+
NC*
Pin 1
4.7
F*
+
NC*
Pin 1
4.7
F*
+
NC*
Pin 1
4.7
F*
+
NC*
Pin 1
4.7
F*
+
20k
Figure 5. Suggested IMP5241/5242/5243 Universal Application Schematic
(Please reference manufacture's current data sheet to ensure compatibility)
1
IMP52
IMP52
4
4
1/42/43
1/42/43
Plastic (SSOP) Widebody SOIC (36-Pin)
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t
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C
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L
s
p
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.
1
0
t
_
2
4
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1
4
2
5
D
E
P
F
36
19
18
1
B
H
G
E
M
A
L
C
36-Pin (SSOP).eps
SEATING PLANE
3
2
1
E
P
D
SEATING PLANE B
G
A H
F
E
L
24-Pin (TSSOP).eps
C
M
Thin Small Shrink Outline (TSSOP) (24-Pin)
PW
3
2
1
E
P
D
SEATING PLANE B
G
A H
F
E
L
28-Pin (TSSOP).eps
C
M
Thin Small Shrink Outline (TSSOP) (28-Pin)
PW
DB
2001 IMP, Inc.
Data Communications
9
r
Package Dimensions
1
IMP52
IMP52
4
4
1/42/43
1/42/43
IMP, Inc.
Corporate Headquarters
2830 N. First Street
San Jose, CA 95134-2071
Tel: 408-432-9100
Fax: 408-434-5904
e-mail: info@impinc.com
http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc.
All other company and product names are trademarks of their respective owners.
2001 IMP, Inc.
Printed in USA
Publication #: 7001
Revision:
C
Issue Date:
11/01/01
Type:
Product
1
IMP52
IMP52
4
4
1/42/43
1/42/43
PDF 
ZIP