INDUSTRIAL TEMPERATURE RANGE
IDT74LVC374A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
1
APRIL 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4618/2
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
Rail-to-rail output swing for increased noise margin
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SOIC, SSOP, QSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
DRIVE FEATURES:
High Output Drivers: 24mA
Reduced system switching noise
IDT74LVC374A
DESCRIPTION:
The LVC374A octal edge triggered D-type flip-flop is built using advanced
dual metal CMOS technology. This device features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads.
The LVC374A device is particularly suitable for implementing buffer regis-
ters, input-output (I/O) ports, bidirectional bus drivers, and working regis-
ters.
On the positive transition of the clock (CLK) input, the Q outputs are set
to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without interface or pullup components. OE
does not affect internal operations of the latch. Old data can be retained or
new data can be entered while the outputs are in the high-impedance state.
The LVC374A has been designed with a 24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
3.3V CMOS OCTAL
EDGE-TRIGGERED D-TYPE FLIP-
FLOP WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
OE
C
1
CLK
1
D
TO SEVEN OTHER CHANNELS
1
11
3
2
1
D
1
Q
INDUSTRIAL TEMPERATURE RANGE
2
IDT74LVC374A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
4.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5.5
8
pF
C
I/O
I/O Port Capacitance
V
IN
= 0V
6.5
8
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
Symbol
Description
Max
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to +6.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
50 to +50
mA
I
IK
Continuous Clamp Current,
50
mA
I
OK
V
I
< 0 or V
O
< 0
I
CC
Continuous Current through each
100
mA
I
SS
V
CC
or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN CONFIGURATION
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
2
3
1
1
Q
V
CC
16
15
14
6
Q
7
Q
6
D
8
D
8
Q
7
D
11
5
Q
5
D
CLK
19
18
20
17
13
12
OE
5
6
3
D
7
2
Q
3
Q
4
1
D
2
D
8
9
GND
10
4
D
4
Q
NOTES:
1. H = HIGH Voltage Level
X = Don't Care
L = LOW Voltage Level
Z = High-Impedance
= LOW-to-HIGH Transition
2. Output level before the indicated steady-state input conditions were established.
Inputs
Outputs
xD
CLK
OE
xQ
H
L
H
L
L
L
X
H or L
L
Q
(2)
X
X
H
Z
FUNCTION TABLE
(EACH FLIP-FLOP)
(1)
Pin Names
Description
OE
Output Enable Input (Active LOW)
CLK
Clock Input
xD
Data Inputs
xQ
Data Outputs
PIN DESCRIPTION
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC374A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
3
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
1.7
--
--
V
V
CC
= 2.7V to 3.6V
2
--
--
V
IL
Input LOW Voltage Level
V
CC
= 2.3V to 2.7V
--
--
0.7
V
V
CC
= 2.7V to 3.6V
--
--
0.8
I
IH
Input Leakage Current
V
CC
= 3.6V
V
I
= 0 to 5.5V
--
--
5
A
I
IL
I
OZH
High Impedance Output Current
V
CC
= 3.6V
V
O
= 0 to 5.5V
--
--
10
A
I
OZL
(3-State Output pins)
I
OFF
Input/Output Power Off Leakage
V
CC
= 0V, V
IN
or V
O
5.5V
--
--
50
A
V
IK
Clamp Diode Voltage
V
CC
= 2.3V, I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
V
CC
= 3.3V
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= 3.6V
V
IN
= GND or V
CC
--
--
10
A
I
CCH
I
CCZ
3.6
V
IN
5.5V
(2)
--
--
10
I
CC
Quiescent Power Supply Current
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
--
--
500
A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 40C to +85C
NOTES:
1. Typical values are at V
CC
= 3.3V, +25C ambient.
2. This applies in the disabled state only.
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 6mA
2
--
V
CC
= 2.3V
I
OH
= 12mA
1.7
--
V
CC
= 2.7V
2.2
--
V
CC
= 3V
2.4
--
V
CC
= 3V
I
OH
= 24mA
2.2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 6mA
--
0.4
I
OL
= 12mA
--
0.7
V
CC
= 2.7V
I
OL
= 12mA
--
0.4
V
CC
= 3V
I
OL
= 24mA
--
0.55
INDUSTRIAL TEMPERATURE RANGE
4
IDT74LVC374A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
OPERATING CHARACTERISTICS, V
CC
= 3.3V 0.3V, T
A
= 25C
Symbol
Parameter
Test Conditions
Typical
Unit
C
PD
Power Dissipation Capacitance per Flip-Flop Outputs enabled
C
L
= 0pF, f = 10Mhz
54.5
pF
C
PD
Power Dissipation Capacitance per Flip-Flop Outputs disabled
13.5
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
f
MAX
80
--
100
--
MHz
t
PLH
Propagation Delay
--
8.1
1.5
7
ns
t
PHL
CLK to xQ
t
PZH
Output Enable Time
--
8.5
1.5
7.5
ns
t
PZL
OE to xQ
t
PHZ
Output Disable Time
--
7.1
1.5
6.5
ns
t
PLZ
OE to xQ
t
W
Pulse Duration, CLK HIGH or LOW
3.3
--
3.3
--
ns
t
SU
Set-up Time, data before CLK
2
--
2
--
ns
t
H
Hold Time, data after CLK
1.5
--
1.5
--
ns
t
SK
(o)
Output Skew
(2)
--
--
--
1
ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= 40C to + 85C.
2. Skew between any two outputs of the same package and switching in the same direction.
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC374A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
5
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
LVC Link
INPUT
V
IH
0V
V
OH
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
LVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
IH
V
T
V
T
V
IH
V
T
LVC Link
DATA
INPUT
0V
0V
0V
0V
t
REM
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
LVC Link
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
V
T
LVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SWITCH
V
LOAD
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SWITCH
GND
t
PHZ
0V
V
OL+
V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
OH-
V
HZ
LVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
10MHz; t
F
2.5ns; t
R
2.5ns.
2. Pulse Generator for All Pulses: Rate
10MHz; t
F
2ns; t
R
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol V
CC(1)
= 3.3V0.3V V
CC(1)
= 2.7V
V
CC(2)
= 2.5V0.2V
Unit
V
LOAD
6
6
2 x Vcc
V
V
IH
2.7
2.7
Vcc
V
V
T
1.5
1.5
Vcc
/ 2
V
V
LZ
300
300
150
mV
V
HZ
300
300
150
mV
C
L
50
50
30
pF
TEST CONDITIONS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
V
LOAD
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
INDUSTRIAL TEMPERATURE RANGE
6
IDT74LVC374A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
ORDERING INFORMATION
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
IDT
XX
LVC
XXXX
XX
Package
Device Type
Temp. Range
SO
PY
Q
PG
74
Small Outline IC (gull wing)
Shrink Small Outline Package
Quarter Size Small Outline Package
Thin Shrink Small Outline Package
Octal Edge-Triggered D-Type Flip-Flop with
3-State Outputs, 24mA
40C to +85C
X
Bus-Hold
374A
No Bus-hold
Blank
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