1
IDT54/74FCT162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1999
1999 Integrated Device Technology, Inc.
DSC-5434/-
c
IDT54/74FCT162H501AT/CT/ET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS
18-BIT REGISTERED
TRANSCEIVER
DESCRIPTION:
The FCT162H501AT/CT/ET 18-bit registered transceivers are built
using advanced dual metal CMOS technology. These high-speed, low-
power 18-bit registered bus transceivers combine D-type latches and D-
type flip-flops to allow data flow in transparent, latched and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and
OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA)
inputs. For A-to-B data flow, the device operates in transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A bus data is stored in the latch/
flip-flop on the low-to-high transition of CLKAB. OEAB is the output enable
for the B port. Data flow from the B port to the A port is similar but requires
using
OEBA, LEBA and CLKBA. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
The FCT162H501AT/CT/ET has "Bus Hold" which retains the input's
last state whenever the input goes to high impedance. This prevents
"floating" inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
O EB A
CLKBA
LEBA
O EA B
CLKAB
LEAB
B
1
A
1
C
C
D
D
D
C
D
C
TO 17 OTHER CHANNELS
1
30
28
27
55
2
3
54
FEATURES:
-
0.5 MICRON CMOS Technology
-
High-speed, low-power CMOS replacement for ABT functions
-
Typical t
SK
(o) (Output Skew) < 250ps
-
Low input and output leakage
1 A (max.)
-
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
-
25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP
and 25 mil pitch CERPACK packages
-
Extended commercial range of -40C to +85C
-
Bus Hold retains last active bus state during 3-state
-
Eliminates the need for external pull up resistors
2
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
SSOP/ TSSOP/ TVSOP/ CERPACK
TOP VIEW
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
Unit
V
TERM(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
V
TERM(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
5v16-link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. All device
terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
CAPACITANCE (T
A
= +25
O
C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
3.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
3.5
8
pF
5v16-link
NOTE:
1. This parameter is measured at characterization but not tested.
G N D
B
2
B
3
G N D
B
4
B
5
V
C C
B
6
B
7
B
1
B
8
B
9
B
1 0
B
1 1
G N D
B
1 2
B
1 3
V
C C
B
1 4
G N D
C LK A B
B
1 6
B
1 5
B
1 7
G N D
B
1 8
C LK B A
G N D
O E A B
LEA B
A
1
G N D
A
2
A
3
V
C C
A
4
A
5
G N D
A
6
A
7
A
8
A
9
G N D
A
10
A
11
V
C C
A
12
A
18
A
14
A
13
A
16
G N D
A
17
LEB A
A
15
O E B A
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
SO 56-1
SO 56-2
SO 56-3
E56-1
29
30
31
32
25
26
27
28
PIN DESCRIPTION
Pin Names
Description
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
A x
A-to-B Data Inputs or B-to-A 3-State Outputs
(1)
B x
B-to-A Data Inputs or A-to-B 3-State Outputs
(1)
NOTE:
1. These pins have "Bus Hold". All other pins are standard inputs, outputs
or I/Os.
FUNCTION TABLE
(1,4)
Inputs
Outputs
OEAB
LEAB
CLKAB
Ax
Bx
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
L
X
B
(2)
H
L
H
X
B
(3)
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA
, LEBA,
and CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
= LOW-to-HIGH Transition
3
IDT54/74FCT162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
ODL
Output LOW Current
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
60
115
200
mA
I
ODH
Output HIGH Current
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
60
115
200
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 16mA MIL.
2.4
3.3
--
V
V
IN
= V
IH
or V
IL
I
OH
= 24mA COM'L.
V
OL
Output LOW Voltage
V
CC
= Min.
I
OL
= 16mA MIL.
--
0.3
0.55
V
V
IN
= V
IH
or V
IL
I
OL
= 24mA COM'L
5v16-link
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is 5A at T
A
= -55C.
OUTPUT DRIVE CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= -40C to +85C, V
CC
= 5.0V 10%; Military: T
A
= -55C to +125C, V
CC
= 5.0V 10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH
Standard Input
(5)
V
CC
= Max.
V
I
= V
CC
--
--
1
A
Current
(4)
Standard I/O
(5)
--
--
1
Bus-hold Input
--
--
100
Bus-hold I/O
--
--
100
I
IL
Input LOW
Standard Input
(5)
V
I
= GND
--
--
1
Current
(4)
Standard I/O
(5)
--
--
1
Bus-hold Input
--
--
100
Bus-hold I/O
--
--
100
I
BHH
Bus Hold
Bus-hold Input
V
CC
= Min.
V
I
= 2.0V
50
--
--
A
I
BHL
Sustain Current
(4)
V
I
= 0.8V
+50
--
--
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
(5, 6)
V
O
= 0.5V
--
--
1
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
80
140
250
mA
V
H
Input Hysteresis
--
--
100
--
mV
I
CCL
I
CCH
I
CCZ
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
--
5
500
A
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Pins with Bus-hold are identified in the pin description.
5. The test limit for this parameter is 5A at T
A
= -55C.
6. Does not include Bus-hold I/O pins.
4
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply
V
CC
= Max.
--
0.5
1.5
mA
Current TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
75
120
A/
OEAB =
OEBA = V
CC
or GND
V
IN
= GND
MHz
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
0.8
1.7
mA
f
CP
= 10MHz (CLKAB)
V
IN
= GND
50% Duty Cycle
OEAB =
OEBA = V
CC
LEAB = GND
V
IN
= 3.4V
--
1.3
3.2
One Bit Toggling
V
IN
= GND
f
i
=
5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
3.8
6.5
(5)
f
CP
= 10MHz (CLKAB)
V
IN
= GND
50% Duty Cycle
OEAB =
OEBA = V
CC
LEAB = GND
V
IN
= 3.4V
--
8.5
20.8
(5)
Eighteen Bits Toggling
V
IN
= GND
f
i
=
2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
fi = Input Frequency
Ni = Number of Inputs at fi
5
IDT54/74FCT162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162H501AT
FCT162H501CT
FCT162H501ET
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Unit
f
MAX
CLKAB or CLKBA frequency
(4)
C
L
= 50pF
--
150
--
150
--
150
--
150
--
150
--
--
MHz
t
PLH
t
PHL
Propagation Delay
Ax to Bx or Bx to Ax
R
L
= 500
1.5
5.1
1.5
5.6
1.5
4.6
1.5
4.6
1.5
3.8
--
--
ns
t
PLH
t
PHL
Propagation Delay
LEBA to Ax, LEAB to Bx
1.5
5.6
1.5
6
1.5
5.3
1.5
5.6
1.5
4.2
--
--
ns
t
PLH
t
PHL
Propagation Delay
CLKBA to Ax, CLKAB to Bx
1.5
5.6
1.5
6
1.5
5.3
1.5
5.4
1.5
4.2
--
--
ns
t
PZH
t
PZL
Output Enable Time
OEBA to Ax, OEAB to Bx
1.5
6
1.5
6.4
1.5
5.6
1.5
6
1.5
4.8
--
--
ns
t
PHZ
t
PLZ
Output Disable Time
OEBA to Ax, OEAB to Bx
1.5
5.6
1.5
6
1.5
5.2
1.5
5.6
1.5
5.2
--
--
ns
t
SU
Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
3
--
3
--
3
--
3
--
2.4
--
--
--
ns
t
H
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
0
--
0
--
0
--
0
--
0
--
--
--
ns
t
SU
Set-up Time HIGH or LOW Clock LOW
3
--
3
--
3
--
3
--
2
--
--
--
ns
Ax to LEAB, Bx to LEBA
Clock HIGH
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
--
--
ns
t
H
Hold Time, HIGH or LOW
Ax to LEAB, Bx to LEBA
1.5
--
1.5
--
1.5
--
1.5
--
0.5
--
--
--
ns
t
W
LEAB or LEBA Pulse Width HIGH
(4)
3
--
3
--
3
--
3
--
3
--
--
--
ns
t
W
CLKAB or CLKBA Pulse Width HIGH or LOW
(4)
3
--
3
--
3
--
3
--
3
--
--
--
ns
t
SK
(o)
Output Skew
(3)
--
0.5
--
0.5
--
0.5
--
0.5
--
0.5
--
--
ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
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