Integrated
Circuit
Systems, Inc.
ICS9DB106
Preliminary Product Preview
0833A--07/26/04
Pin Configuration
Recommended Application:
1-to-6 Zero-delay or fanout buffer for PCI Express
Output Features:
6 - 0.7V current mode differential output pairs (HSCL)
SMBus for complete device control
Key Specifications:
Cycle-to-cycle jitter < 40ps
Output-to-output skew < 30 ps
Features/Benefits:
CLKREQ# pin for outputs 1 and 4/output enable for
Express Card applications
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible/tracks spreading input
clock for low EMI
SMBus Interface/unused outputs can be disabled
6 Output PCI Express* Buffer with CLKREQ# Function
28-pin SSOP & TSSOP
PLL_BW 1
28 VDDA
CLK_INT 2
27 GNDA
CLK_INC 3
26 IREF
*CLKREQ1# 4
25 **CLKREQ4#
PCIEXT0 5
24 PCIEXT5
PCIEXC0 6
23 PCIEXC5
VDD 7
22 VDD
GND 8
21 GND
PCIEXT1 9
20 PCIEXT4
PCIEXC1 10
19 PCIEXC4
PCIEXT2 11
18 PCIEXT3
PCIEXC2 12
17 PCIEXC3
VDD 13
16 VDD
SMBDAT 14
15 SMBCLK
Note:
Pins preceeded by '**' have internal 120K ohm pull down resistors
I
C
S9
DB1
0
6
*Other names and brands may be claimed as the property of others.
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
change without notice.
2
Integrated
Circuit
Systems, Inc.
ICS9DB106
Preliminary Product Preview
0833A--07/26/04
Pin Description
PIN
#
PIN NAME
PIN TYPE
DESCRIPTION
1
PLL_BW
IN
3.3V input for selecting PLL Band Width
0 = low, 1= high
2
CLK_INT
IN
"True" reference clock input.
3
CLK_INC
IN
"Complimentary" reference clock input.
4
**CLKREQ1#
IN
Output enable for PCI Express output pair '1'
0 = enabled, 1 = tri-stated
5
PCIEXT0
OUT
True clock of differential PCI_Express pair.
6
PCIEXC0
OUT
Complement clock of differential PCI_Express pair.
7
VDD
PWR
Power supply, nominal 3.3V
8
GND
IN
Ground pin.
9
PCIEXT1
OUT
True clock of differential PCI_Express pair.
10
PCIEXC1
OUT
Complement clock of differential PCI_Express pair.
11
PCIEXT2
OUT
True clock of differential PCI_Express pair.
12
PCIEXC2
OUT
Complement clock of differential PCI_Express pair.
13
VDD
PWR
Power supply, nominal 3.3V
14
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
15
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
16
VDD
PWR
Power supply, nominal 3.3V
17
PCIEXC3
OUT
Complement clock of differential PCI_Express pair.
18
PCIEXT3
OUT
True clock of differential PCI_Express pair.
19
PCIEXC4
OUT
Complement clock of differential PCI_Express pair.
20
PCIEXT4
OUT
True clock of differential PCI_Express pair.
21
GND
PWR
Ground pin.
22
VDD
PWR
Power supply, nominal 3.3V
23
PCIEXC5
OUT
Complement clock of differential PCI_Express pair.
24
PCIEXT5
OUT
True clock of differential PCI_Express pair.
25
**CLKREQ4#
IN
Output enable for PCI Express output pair '4'
0 = enabled, 1 = tri-stated
26
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied
to ground in order to establish the appropriate current. 475 ohms is
the standard value.
27
GNDA
PWR
Ground pin for the PLL core.
28
VDDA
PWR
3.3V power for the PLL core.
Note:
Pins preceeded by '**' have internal 120K ohm pull down resistors
3
Integrated
Circuit
Systems, Inc.
ICS9DB106
Preliminary Product Preview
0833A--07/26/04
The ICS9DB106 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB106 is driven by a differential
SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It
attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without
Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock
request (OE#) pins make the ICS9DB106 suitable for Express Card applications.
General Description
Block Diagram
Power Groups
VDD
GND
7, 13, 16, 22
8,21
PCI Express Outputs
TBD
TBD
SMBUS
N/A
27
IREF
28
27
Analog VDD & GND for PLL core
Description
Pin Number
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
SMBDAT
SMBCLK
CLK_INT
C LK_INC
PLL_BW
IREF
PCIEX1
PCIEX4
CLKREQ4#
CLKREQ1#
PCIEX(0,2,3,5)
4
Integrated
Circuit
Systems, Inc.
ICS9DB106
Preliminary Product Preview
0833A--07/26/04
Absolute Max
Symbol
Parameter
Min
Max
Units
VDDA
3.3V Core Supply Voltage
V
DD
+ 0.5V
V
VDD
3.3V Output Supply Voltage
GND - 0.5
V
DD
+ 0.5V
V
Ts
Storage Temperature
-65
150
C
Tambient
Ambient Operating Temp
0
70
C
Tcase Case
Temperature
115
C
ESD prot
Input ESD protection
human body model
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Input High Voltage
V
IH
3.3 V +/-5%
2
V
DD
+ 0.3
V
1
Input Low Voltage
V
IL
3.3 V +/-5%
V
SS
- 0.3
0.8
V
1
Input High Current
I
IH
V
IN
= V
DD
-5
5
uA
1
I
IL1
V
IN
= 0 V; Inputs with no pull-
up resistors
-5
uA
1
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200
uA
1
Full Active, C
L
= Full load;
130
150
mA
1
all differential pairs tri-stated
30
40
mA
1
Input Frequency
F
i
V
DD
= 3.3 V
99
100
101
MHz
Pin Inductance
L
pin
7
nH
1
C
IN
Logic Inputs
5
pF
1
C
OUT
Output pin capacitance
4.5
pF
1
Clk Stabilization
T
STAB
From VDD reaching 3.1V and
input clock stable
1.8
ms
1
Input Spread Spectrum
Modulation Frequency
Triangular Modulation
30
33
kHz
1
SMBus Voltage
V
DD
2.7
5.5
V
1
Low-level Output Voltage
V
OL
@ I
PULLUP
0.4
V
1
Current sinking at
V
OL
= 0.4 V
I
PULLUP
4
mA
1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
1
Guaranteed by design and characterization, not 100% tested in production.
Input Capacitance
I
DD3.3OP
Operating Supply Current
Input Low Current
5
Integrated
Circuit
Systems, Inc.
ICS9DB106
Preliminary Product Preview
0833A--07/26/04
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Outputs
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2
, R
P
=49.9
REF
9,
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Current Source Output
Impedance
Zo
1
V
O
= V
x
3000
1
Voltage High
VHigh
660
850
1,3
Voltage Low
VLow
-150
150
1,3
Max Voltage
Vovs
1150
1,3
Min Voltage
Vuds
-300
1,3
Crossing Voltage (abs)
Vcross(abs)
250
550
mV
1,3
Crossing Voltage (var)
d-Vcross
Variation of crossing over all
edges
140
mV
1,3
Long Accuracy
ppm
see Tperiod min-max values
0
ppm
1,2
100.00MHz nominal
9.9970
10.0030
ns
2
100.00MHz spread
9.9970
10.0533
ns
2
Absolute min period
T
absmin
100.00MHz nominal/spread
9.8720
ns
1,2
Rise Time
t
r
V
OL
= 0.175V, V
OH
= 0.525V
175
700
ps
1
Fall Time
t
f
V
OH
= 0.525V V
OL
= 0.175V
175
700
ps
1
Rise Time Variation
d-t
r
125
ps
1
Fall Time Variation
d-t
f
125
ps
1
t
pd
PLL Mode.
100
150
ps
1
t
pdbyp
Bypass mode
3.2
3.7
ns
1
Duty Cycle
d
t3
Measurement from differential
wavefrom
45
55
%
1
Output-to-Output Skew
t
sk3
V
T
= 50%
30
ps
1
PLL mode,
Measurement from differential
wavefrom
40
ps
1
BYPASS mode as additive jitter
25
ps
1
1
Guaranteed by design and characterization, not 100% tested in production.
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock
complies with CK409/CK410 accuracy requirements
Jitter, Cycle to cycle
t
jcyc-cyc
Average period
T
period
Input to Output Delay
Statistical measurement on
single ended signal using
oscilloscope math function.
mV
Measurement on single ended
signal using absolute value.
mV
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