Integrated
Circuit
Systems, Inc.
ICS94228
0447E--05/07/04
Block Diagram
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA KT266 style chipset
Output Features:
1 - Differential pair open drain CPU clocks @ 2.7V
1 - Differential pair push-pull CPU clocks @ 2.5V
11 - PCI including 1 free running and 1 early @ 3.3V
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz.
Features:
Programmable output frequency.
Programmable output rise/fall time.
Programmable slew and skew control for CPUCLK,
PCICLK, AGP, REF, 48MHz and 24_48MHz.
Real time system reset output.
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread
percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
Skew Specifications:
CPU - CPU: <200ps
PCI - PCI: <500ps
CPU (early - PCI: min=1.0ns, max=2.6ns
CPU cycle to cycle jitter: <250ps
Programmable System Clock Chip for AMD - K7TM processor
* Internal Pull-up Resistor of 120K to VDD
SEL24_48#
PLL2
PLL1
Spread
Spectrum
48MHz (1:0)
24_48MHz
PCICLK (8:0)
AGP (2:0)
PCICLK_F
REF_F
PCICLK9_E
SRESET#
3
9
2
2
X1
X2
XTAL
OSC
CPU
DIVDER
CPU
DIVDER
PCI
DIVDER
AGP
DIVDER
Stop
Stop
Stop
Stop
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
AGP_STOP#
REF_STOP#
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
CPUCLKT0
CPUCLKC0
CPUCLK_CST0
CPUCLK_CSC0
3
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VDDREF
GND
X1
X2
AVDD48
*FS2/48MHz
*FS3/24_48MHz
GND
PCICLK_F
*SEL24_48#/PCICLK0
PCICLK1
GND
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
PCILCK8
PCICLK9_E
VDDPCI
SRESET#
REF0/
REF1/FS1*
REF_F
REF_STOP#*
AGP_STOP#*
GND
CPUCLKT0
CPUCLKC0
VDDL
CPUCLK_CST0
CPUCLK_CSC0
GND
CPU_STOP#*
PCI_STOP#*
PD#*
AVDD
AGND
SDATA
SCLK
GND
AGP2
AGP1
AGP0
VDDAGP
FS0*
ICS9422
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
ICS94228
0447E--05/07/04
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
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3
ICS94228
0447E--05/07/04
General Description
The ICS94228 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all
clocks required for such a system.
The ICS94228 belongs to ICS new generation of programmable system clock generators. It employs serial
programming I
2
C interface as a vehicle for changing output functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable from over clocking.
SRESET# Signal Description
The SRESET# signal from ICS94228 system clock generator is a real time active low pulse that can be used to reset
the system.
The Open-Drain Nch output Reset# pin needs to be tied to the system reset line which has a pull-up resistor. When
activated, the SRESET# output will be driven to a low with a 32ms pulse width.
4
ICS94228
0447E--05/07/04
General I
2
C serial interface information for the ICS94228
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 16
(see Note 2)
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends Byte 0 through byte 6 (default)
ICS clock sends Byte 0 through byte X (if X
(H)
was
written to byte 6).
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
*See notes on the following page
.
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 14
ACK
Byte 15
ACK
Byte 16
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B6
Byte 7
ACK
If 1A
H
has been written to B6
Byte 14
ACK
If 1B
H
has been written to B6
Byte 15
ACK
If 1C
H
has been written to B6
Byte 16
ACK
Stop Bit
How to Read:
5
ICS94228
0447E--05/07/04
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8 bit bytes.
6.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Notes:
Brief I
2
C registers description for ICS94228
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Functionality &
Frequency Select
Register
0
Output frequency, hardware / I
2
C
frequency select, spread spectrum &
output enable control register.
See individual
byte
description
Output Control Registers
1, 2, 3
Active / inactive output control
registers/latch inputs read back.
See individual
byte
description
Vendor ID & Revision ID
Registers
5, 6, 7
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
See individual
byte
description
Byte Count
Read Back Register
8
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00
H
to
this byte.
08
H
Watchdog Enable
Register
4
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
10
H
Watchdog Control
Registers
Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.
000,0000
VCO Control Selection
Bit
4, 5
This bit select whether the output
frequency is control by
hardware/byte 0 configurations or
byte 11&12 programming.
0
VCO Frequency Control
Registers
9, 10
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
Depended on
hardware/byte
0 configuration
Spread Spectrum
Control Registers
11, 12
These registers control the spread
percentage amount.
Depended on
hardware/byte
0 configuration
Group Skews Control
Registers
13, 14
Increment or decrement the group
skew amount as compared to the
initial skew.
See individual
byte
description
Output Rise/Fall Time
Select Registers
15, 16
These registers will control the
output rise and fall time.
See individual
byte
description
6
ICS94228
0447E--05/07/04
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Bit5
Bit4
Bit3 Bit2 Bit1 Bit0
SSB1 SSB0 FS3 FS2 FS1 FS0
0
0
0
0
0
0
233.33
77.78
38.88
+/- 0.25% Center Spread
0
0
0
0
0
1
220.00
73.33
36.67
+/- 0.25% Center Spread
0
0
0
0
1
0
210.00
70.00
35.00
+/- 0.25% Center Spread
0
0
0
0
1
1
200.00
66.67
33.33
+/- 0.25% Center Spread
0
0
0
1
0
0
190.00
76.00
38.00
+/- 0.25% Center Spread
0
0
0
1
0
1
180.00
72.00
36.00
+/- 0.25% Center Spread
0
0
0
1
1
0
170.00
68.00
34.00
+/- 0.25% Center Spread
0
0
0
1
1
1
150.00
75.00
37.50
+/- 0.25% Center Spread
0
0
1
0
0
0
140.00
70.00
35.00
+/- 0.25% Center Spread
0
0
1
0
0
1
120.00
60.00
30.00
+/- 0.25% Center Spread
0
0
1
0
1
0
110.00
66.00
33.00
+/- 0.25% Center Spread
0
0
1
0
1
1
66.67
66.67
33.33
+/- 0.25% Center Spread
0
0
1
1
0
0
200.00
66.67
33.33
+/- 0.25% Center Spread
0
0
1
1
0
1
166.67
66.67
33.33
+/- 0.25% Center Spread
0
0
1
1
1
0
100.00
66.67
33.33
+/- 0.25% Center Spread
0
0
1
1
1
1
133.33
66.67
33.33
+/- 0.25% Center Spread
0
1
0
0
0
0
200.00
66.67
33.33
0 to -0.5% Down Spread
0
1
0
0
0
1
166.67
66.67
33.33
0 to -0.5% Down Spread
0
1
0
0
1
0
100.00
66.67
33.33
0 to -0.5% Down Spread
0
1
0
0
1
1
133.33
66.67
33.33
0 to -0.5% Down Spread
1
0
0
1
0
0
200.00
66.67
33.33
+/- 0.50% Center Spread
1
0
0
1
0
1
166.67
66.67
33.33
+/- 0.50% Center Spread
1
0
0
1
1
0
100.00
66.67
33.33
+/- 0.50% Center Spread
1
0
0
1
1
1
133.33
66.67
33.33
+/- 0.50% Center Spread
1
1
1
0
0
0
200.00
66.67
33.33
+/- 0.75% Center Spread
1
1
1
0
0
1
166.67
66.67
33.33
+/- 0.75% Center Spread
1
1
1
0
1
0
100.00
66.67
33.33
+/- 0.75% Center Spread
1
1
1
0
1
1
133.33
66.67
33.33
+/- 0.75% Center Spread
1
0
1
1
0
0
200.00
66.67
33.33
0 to +0.5% Up Spread
1
0
1
1
0
1
166.67
66.67
33.33
0 to +0.5% Up Spread
1
0
1
1
1
0
100.00
66.67
33.33
0 to +0.5% Up Spread
1
0
1
1
1
1
133.33
66.67
33.33
0 to +0.5% Up Spread
Bit 6: 0 = Hardware select; 1 = I
2
C select. Default is OFF.
Bit 7: 0 = Spread off; 1 = Spread spectrum enable. Default is OFF
CPUCLK AGPCLK
PCICLK
Spread Percentage
7
ICS94228
0447E--05/07/04
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
1
4
,
2
4
1
0
C
K
L
C
U
P
C
,
0
T
K
L
C
U
P
C
6
t
i
B
8
3
,
9
3
1
0
C
S
C
_
K
L
C
U
P
C
,
0
T
S
C
_
K
L
C
U
P
C
5
t
i
B
6
1
z
H
M
8
4
4
t
i
B
7
1
z
H
M
8
4
_
4
2
3
t
i
B
-
1
)
k
c
a
b
d
a
e
r
(
0
S
F
2
t
i
B
8
2
1
2
P
G
A
1
t
i
B
7
2
1
1
P
G
A
0
t
i
B
6
2
1
0
P
G
A
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
0
2
1
7
K
L
C
I
C
P
6
t
i
B
8
1
1
6
K
L
C
I
C
P
5
t
i
B
7
1
1
5
K
L
C
I
C
P
4
t
i
B
6
1
1
4
K
L
C
I
C
P
3
t
i
B
4
1
1
3
K
L
C
I
C
P
2
t
i
B
3
1
1
2
K
L
C
I
C
P
1
t
i
B
1
1
1
1
K
L
C
I
C
P
0
t
i
B
0
1
1
0
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: Watch Dog Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
k
c
a
b
d
a
e
r
(
#
8
4
_
4
2
L
E
S
6
t
i
B
-
0
)
k
c
a
b
d
a
e
r
(
3
S
F
5
t
i
B
-
0
:
s
u
t
a
t
s
g
o
d
h
c
t
a
W
m
r
a
l
A
=
1
l
a
m
r
o
N
=
0
4
t
i
B
-
1
1
B
S
S
3
t
i
B
-
1
3
S
F
2
t
i
B
-
1
2
S
F
1
t
i
B
-
1
1
S
F
0
t
i
B
-
1
0
S
F
Byte 5: Vendor Specific Feature, Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: PCI, REF, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
9
1
F
_
K
L
C
I
C
P
6
t
i
B
2
2
1
E
_
9
K
L
C
I
C
P
5
t
i
B
-
1
)
k
c
a
b
d
a
e
r
(
1
S
F
4
t
i
B
1
2
1
8
K
L
C
I
C
P
3
t
i
B
6
4
1
F
_
F
E
R
2
t
i
B
-
1
)
k
c
a
b
d
a
e
r
(
2
S
F
1
t
i
B
7
4
1
1
F
E
R
0
t
i
B
8
4
1
0
F
E
R
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
D
I
e
c
i
v
e
D
6
t
i
B
-
0
5
t
i
B
-
0
4
t
i
B
-
1
3
t
i
B
-
0
D
I
r
o
d
n
e
V
2
t
i
B
-
0
1
t
i
B
-
0
0
t
i
B
-
1
Byte 6: Vendor ID1 , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don't write into this register, writing into this
register can cause malfunction
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
e
l
b
a
n
e
g
o
d
h
c
t
a
W
p
o
t
s
:
0
t
r
a
t
s
:
1
6
t
i
B
-
0
e
l
b
a
n
e
m
a
r
g
o
r
p
N
/
M
5
t
i
B
-
0
f
o
n
o
i
t
a
t
n
e
s
e
r
p
e
r
l
a
m
i
c
e
d
e
h
T
o
t
d
n
o
p
s
e
r
r
o
c
s
t
i
b
8
e
s
e
h
t
g
o
d
h
c
t
a
w
e
h
t
s
m
1
r
o
s
m
0
9
2
s
e
o
g
t
i
e
r
o
f
e
b
t
i
a
w
l
l
i
w
r
e
m
i
t
e
h
t
t
e
s
e
r
d
n
a
e
d
o
m
m
r
a
l
a
o
t
.
g
n
i
t
t
e
s
e
f
a
s
e
h
t
o
t
y
c
n
e
u
q
e
r
f
X
8
s
i
p
u
r
e
w
o
p
t
a
t
l
u
a
f
e
D
.
s
d
n
o
c
e
s
6
.
4
=
s
m
0
8
5
4
t
i
B
-
0
3
t
i
B
-
1
2
t
i
B
-
0
1
t
i
B
-
0
0
t
i
B
-
0
8
ICS94228
0447E--05/07/04
Byte 7: Vendor ID2, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
D
I
n
o
i
s
i
v
e
R
6
t
i
B
-
0
D
I
n
o
i
s
i
v
e
R
5
t
i
B
-
0
D
I
n
o
i
s
i
v
e
R
4
t
i
B
-
0
D
I
n
o
i
s
i
v
e
R
3
t
i
B
-
1
D
I
n
o
i
s
i
v
e
R
2
t
i
B
-
1
D
I
n
o
i
s
i
v
e
R
1
t
i
B
-
0
D
I
n
o
i
s
i
v
e
R
0
t
i
B
-
0
D
I
n
o
i
s
i
v
e
R
Byte 8: Byte Count Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
d
e
v
r
e
s
e
R
6
t
i
B
-
0
d
e
v
r
e
s
e
R
5
t
i
B
-
0
d
e
v
r
e
s
e
R
4
t
i
B
-
0
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
0
d
e
v
r
e
s
e
R
1
t
i
B
-
0
d
e
v
r
e
s
e
R
0
t
i
B
-
0
d
e
v
r
e
s
e
R
Byte 11: VCO Spread Spectrum Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
7
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
6
t
i
B
-
X
6
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
5
t
i
B
-
X
5
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
4
t
i
B
-
X
4
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
t
i
B
-
X
3
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
t
i
B
-
X
2
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
t
i
B
-
X
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
t
i
B
-
X
0
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
Byte 12: VCO Spread Spectrum Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
d
e
v
r
e
s
e
R
6
t
i
B
-
X
d
e
v
r
e
s
e
R
5
t
i
B
-
X
d
e
v
r
e
s
e
R
4
t
i
B
-
X
2
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
t
i
B
-
X
1
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
t
i
B
-
X
0
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
t
i
B
-
X
9
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
t
i
B
-
X
8
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
Byte 10: VCO Frequency Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
8
t
i
B
r
e
d
i
v
i
D
O
C
V
6
t
i
B
-
X
7
t
i
B
r
e
d
i
v
i
D
O
C
V
5
t
i
B
-
X
6
t
i
B
r
e
d
i
v
i
D
O
C
V
4
t
i
B
-
X
5
t
i
B
r
e
d
i
v
i
D
O
C
V
3
t
i
B
-
X
4
t
i
B
r
e
d
i
v
i
D
O
C
V
2
t
i
B
-
X
3
t
i
B
r
e
d
i
v
i
D
O
C
V
1
t
i
B
-
X
2
t
i
B
r
e
d
i
v
i
D
O
C
V
0
t
i
B
-
X
1
t
i
B
r
e
d
i
v
i
D
O
C
V
Byte 9: VCO Frequency Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
0
t
i
B
r
e
d
v
i
D
O
C
V
6
t
i
B
-
X
6
t
i
B
r
e
d
v
i
D
F
E
R
5
t
i
B
-
X
5
t
i
B
r
e
d
v
i
D
F
E
R
4
t
i
B
-
X
4
t
i
B
r
e
d
v
i
D
F
E
R
3
t
i
B
-
X
3
t
i
B
r
e
d
v
i
D
F
E
R
2
t
i
B
-
X
2
t
i
B
r
e
d
v
i
D
F
E
R
1
t
i
B
-
X
1
t
i
B
r
e
d
v
i
D
F
E
R
0
t
i
B
-
X
0
t
i
B
r
e
d
v
i
D
F
E
R
9
ICS94228
0447E--05/07/04
Byte 13: Output Skew Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
l
o
r
t
n
o
C
w
e
k
S
0
T
/
0
C
K
L
C
U
P
C
6
t
i
B
-
0
5
t
i
B
-
0
4
t
i
B
-
0
3
t
i
B
-
0
l
o
r
t
n
o
C
w
e
k
S
C
/
T
S
C
_
C
K
L
C
U
P
C
2
t
i
B
-
0
1
t
i
B
-
0
0
t
i
B
-
0
Byte 14: Output Skew Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
l
o
r
t
n
o
C
w
e
k
S
)
0
:
8
(
K
L
C
I
C
P
6
t
i
B
-
0
5
t
i
B
-
1
4
t
i
B
-
0
3
t
i
B
-
0
l
o
r
t
n
o
C
w
e
k
S
)
0
:
2
(
P
G
A
2
t
i
B
-
0
1
t
i
B
-
0
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
E
_
9
K
L
C
I
C
P
0
t
i
B
-
0
Byte 15: Output Rise/Fall Time Select Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
0
T
K
L
C
U
P
C
6
t
i
B
-
0
0
C
K
L
C
U
P
C
5
t
i
B
-
0
T
S
C
_
T
K
L
C
U
P
C
4
t
i
B
-
0
C
S
C
_
C
K
L
C
U
P
C
3
t
i
B
-
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
)
0
:
2
(
P
G
A
2
t
i
B
-
0
1
t
i
B
-
0
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
)
0
:
2
(
F
E
R
0
t
i
B
-
0
Byte 16: Output Rise/Fall Time Select Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
)
0
:
3
(
K
L
C
I
C
P
6
t
i
B
-
0
5
t
i
B
-
1
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
)
4
:
8
(
K
L
C
I
C
P
4
t
i
B
-
0
3
t
i
B
-
0
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
z
H
M
8
4
2
t
i
B
-
0
1
t
i
B
-
0
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
z
H
M
8
4
_
4
2
0
t
i
B
-
0
10
ICS94228
0447E--05/07/04
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . 0C to +70C
Storage Temperature . . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+ 0.3
V
Input Low Voltage
V
IL
V
SS
- 0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
5
mA
Input Low Current
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
-5
mA
Input Low Current
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
mA
Operating
I
DD3.3OP66
C
L
= 0 pF; Select @ 66MHz
Supply Current
I
DD3.3OP100
C
L
= 0 pF; Select @ 100MHz
I
DD3.3OP133
C
L
= 0 pF; Select @ 133MHz
Power Down
PD
600
mA
Input frequency
F
i
V
DD
= 3.3 V;
12
14.318
16
MHz
C
IN
Logic Inputs
5
pF
C
INX
X1 & X2 pins
27
45
pF
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target Freq.
3
ms
t
CPU-PCI
2.3
2.6
ns
t
CPU-AGP
300
550
ps
1
Guaranteed by design, not 100% tested in production.
180
mA
Skew Window
Input Capacitance
1
11
ICS94228
0447E--05/07/04
Electrical Characteristics - REF
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output High Voltage
V
OH5
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL5
I
OL
= 9 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-22
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
16
mA
Rise Time
1
t
r5
V
OL
= 0.4 V, V
OH
= 2.4 V
1.3
4
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, V
OL
= 0.4 V
1.4
4
ns
Duty Cycle
1
d
t5
V
T
= 1.5V
45
54
57
%
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; V
DDL
=2.5V+/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
MIN
TYP
UNITS
Output Impedance
Z
O
W
V
V
Output Low Current
I
OL2B
18
mA
Rise Time
1
, CPUCLK
t
r2B
2.2
ns
Fall Time
1
, CPUCLK
t
f2B
1.3
ns
Duty Cycle
1
d
t2B
45
50
%
Skew
1
t
sk2B
140
Jitter, Cycle-to-cycle
1
,
CPUCLK
t
jcyc-cyc2B
150
ps
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "tr
3 - Vpullup(external) = 2.7V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV
Differential Crossover
Voltage
1
CPUCLK(Open Drain)
V
X
Note 3
1.2
0.4
0.2
V
OL
= 0.3V
V
OL
= 20%, V
OH
= 80%
V
OH
= 80%, V
OL
=20%
V
T
= 50%
V
T
= 50%
V
T
= V
X
200
250
55
V
Vpullup(external)
+ 0.6
V
1.7
V
1.4
Vpullup(external)
+ 0.6
2.0
2.5
Output Low Voltage
Differential voltage-DC
1
V
DIF
Note 2
Vpull-up(external)
Differential voltage-AC
1
V
DIF
Note 2
Termination to
MAX
1
V
OL2B
Vpull-up(external)
1.2
0.4
Output High Voltage
V
OH2B
CONDITIONS
V
O
= V
X
Termination to
12
ICS94228
0447E--05/07/04
Electrical Characteristics - PCICLK
T
A
= 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH1
2.6
V
Output Low Voltage
V
OL1
0.4
V
Output High Current
I
OH1
-16
mA
Output Low Current
I
OL1
19
mA
Rise Time
1
t
r1
2.0
2.5
ns
Fall Time
1
t
f1
1.8
2.5
ns
Duty Cycle
1
dt1
45
51
55
%
Jitter Cycle-to-Cycle
1
tj
cyc-cyc1
130
500
ps
Skew1(window)
Tsk1
330
500
ps
1
Guaranteed by design, not 100% tested in production.
CONDITIONS
I
OH
= -11 mA
I
OL
= 9.4 mA
V
OH
= 2.0 V
V
OL
= 0.8 V
V
OL
= 0.4 V, V
OH
= 2.4V
V
OH
= 2.4V, V
OL
= 0.4V
V
T
= 1.5 V
V
T
= 1.5V
V
T
= 1.5V
Electrical Characteristics - PCICLK_E
T
A
= 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH1
2.6
V
Output Low Voltage
V
OL1
0.4
V
Output High Current
I
OH1
-12
mA
Output Low Current
I
OL1
12
mA
Rise Time
1
t
r1
1.7
2.5
ns
Fall Time
1
t
f1
2.0
2.5
ns
Duty Cycle
1
dt1
45
52
55
%
Jitter Cycle-to-Cycle
1
tj
cyc-cyc1
100
500
ps
PCI_E to PCI Skew1
Tsk1
2.3
2.7
ns
1
Guaranteed by design, not 100% tested in production.
CONDITIONS
I
OH
= -11 mA
I
OL
= 9.4 mA
V
OH
= 2.0 V
V
OL
= 0.8 V
V
OL
= 0.4 V, V
OH
= 2.4V
V
T
= 1.5 V
V
T
= 1.5V
V
T
= 1.5V
V
OH
= 2.4V, V
OL
= 0.4V
13
ICS94228
0447E--05/07/04
Electrical Characteristics - 24MHz, 48MHz
T
A
= 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH5
2.4
V
Output Low Voltage
V
OL5
0.4
V
Output High Current
I
OH5
-22
mA
Output Low Current
I
OL5
16
mA
Rise Time
1
tr
5
1.3
4
ns
Fall Time
1
tf
5
1.3
4
ns
Duty Cycle
1
dt
5
45
52
55
%
Jitter, Cycle-to-Cycle
1
tjcyc-cyc1
190
500
ps
Jitter, Absolute
1
tjabs5
-1
1
ns
1
Guaranteed by design, not 100% tested in production.
CONDITIONS
I
OH
= -16 mA
I
OL
= 9 mA
V
OH
= 2.0 V
V
OL
= 0.8 V
V
T
= 1.5 V
V
OL
= 0.4 V, V
OH
= 2.4V
V
OH
= 2.4 V, V
OL
= 0.4V
VT = 1.5 V
V
T
= 1.5 V
14
ICS94228
0447E--05/07/04
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS94228
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of Power-
On reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
W
8.2K
W
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
15
ICS94228
0447E--05/07/04
AGP_STOP# Timing Diagram
Notes:
1. All timing is referenced to the internal CPUCLK.
2. AGP_STOP# is an asynchronous input and metastable conditions
may exist. This signal is synchronized to the CPUCLKs inside the
ICS4228.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
5. Only applies if MODE pin latched 0 at power up.
AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP clocks. for low power
operation. AGP_STOP# is synchronized by the ICS94228. The AGPCLKs will always be stopped in a low state and
start in such a manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK
and AGPCLK off latency is less than 3 AGPCLKs. This function is available only with MODE pin latched low.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power
operation. CPU_STOP# is synchronized by the ICS94228. All other clocks will continue to run while the CPUCLKs
clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees
the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than
4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPUCLKs inside the ICS94228.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCICLK
CPUCLKT
CPUCLKT_CST
CPUCLKC
CPUCLKC_CSC
PD# (High)
CPU_STOP#
INTERNAL
CPUCLK
16
ICS94228
0447E--05/07/04
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping
and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94228 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
PD#
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94228. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS94228 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94228 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94228.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCICLK
PCI_STOP#
17
ICS94228
0447E--05/07/04
Ordering Information
ICS94228yFLF-T
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
h x 45
h x 45
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
0
8
0
8
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y F LF- T
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