Integrated
Circuit
Systems, Inc.
ICS93718
0434D--10/10/03
Block Diagram
DDR and SDRAM Buffer
Pin Configuration
48-Pin SSOP
Recommended Application:
DDR & SDRAM fanout buffer, for VIA Pro 266, KT266 and
P4X266 DDR chipsets
Product Description/Features:
Low skew, fanout buffer
1 to 12 differential clock distribution
I
2
C for functional and output control
Feedback pin for input to output synchronization
Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs +
2 DDR DIMMs
Frequency supports up to 200MHz (DDR400)
Supports Power Down Mode for power
mananagement
CMOS level control signal input
Switching Characteristics:
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time for DDR outputs: 500ps -
700ps
DUTY CYCLE: 47% - 53%
FB_OUT
VDD3.3_2.5
GND
DDRT0_SDRAM0
DDRC0_SDRAM1
DDRT1_SDRAM2
DDRC1_SDRAM3
VDD3.3_2.5
GND
DDRT2_SDRAM4
DDRC2_SDRAM5
VDD3.3_2.5
BUF_IN
GND
DDRT3_SDRAM6
DDRC3_SDRAM7
VDD3.3_2.5
GND
DDRT4_SDRAM8
DDRC4_SDRAM9
DDRT5_SDRAM10
DDRC5_SDRAM11
VDD3.3_2.5
SDATA
SEL_DDR*
VDD2.5
GND
DDRT11
DDRC11
DDRT10
DDRC10
VDD2.5
GND
DDRT9
DDRC9
VDD2.5
PD#*
GND
DDRT8
DDRC8
VDD2.5
GND
DDRT7
DDRC7
DDRT6
DDRC6
GND
SCLK
ICS93718
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
*Internal Pull-up Resistor of 120K to VDD
SCLK
SDATA
SEL_DDR*
PD#
BUF_IN
Control
Logic
FB_OUT
DDRT0_SDRAM0
DDRT1_SDRAM2
DDRT2_SDRAM4
DDRT3_SDRAM6
DDRT4_SDRAM8
DDRT5_SDRAM10
DDRT(11:6)
DDRC0_SDRAM1
DDRC1_SDRAM3
DDRC2_SDRAM5
DDRC3_SDRAM7
DDRC4_SDRAM9
DDRC5_SDRAM11
DDRC (11:6)
Functionality
E
D
O
M
8
4
N
I
P
D
D
V
5
.
2
_
3
.
3
N
I
P
,
5
1
,
1
1
,
0
1
,
7
,
6
,
5
,
4
2
2
,
1
2
,
0
2
,
9
1
,
6
1
R
D
D
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d
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R
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o
2
ICS93718
0434D--10/10/03
Pin Descriptions
R
E
B
M
U
N
N
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P
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M
A
N
N
I
P
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P
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T
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R
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=
1
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d
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D
S
/
R
D
D
=
0
3
ICS93718
0434D--10/10/03
Byte 6: Output Control
(1= enable, 0 = disable)
Byte 7: Output Control
(1= enable, 0 = disable)
T
I
B
#
N
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P
D
W
P
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T
P
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4
1
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R
(
R
D
D
_
L
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S
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
1
)
d
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s
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R
(
3
t
i
B
4
4
,
5
4
1
1
1
C
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D
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1
1
T
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D
D
2
t
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2
4
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3
4
1
0
1
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R
D
D
,
0
1
T
R
D
D
1
t
i
B
8
3
,
9
3
1
9
C
R
D
D
,
9
T
R
D
D
0
t
i
B
3
3
,
4
3
1
8
C
R
D
D
,
8
T
R
D
D
T
I
B
#
N
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P
D
W
P
N
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I
T
P
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R
C
S
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D
7
t
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B
9
2
,
0
3
1
7
C
R
D
D
,
7
T
R
D
D
6
t
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B
7
2
,
8
2
1
6
C
R
D
D
,
6
T
R
D
D
5
t
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B
2
2
,
1
2
1
0
1
M
A
R
D
S
,
5
T
R
D
D
1
1
M
A
R
D
S
_
5
C
R
D
D
4
t
i
B
0
2
,
9
1
1
8
M
A
R
D
S
_
4
T
R
D
D
9
M
A
R
D
S
_
4
C
R
D
D
3
t
i
B
6
1
,
5
1
1
6
M
A
R
D
S
_
3
T
R
D
D
7
M
A
R
D
S
_
3
C
R
D
D
2
t
i
B
1
1
,
0
1
1
4
M
A
R
D
S
_
2
T
R
D
D
5
M
A
R
D
S
_
2
C
R
D
D
1
t
i
B
7
,
6
1
2
M
A
R
D
S
_
1
T
R
D
D
3
M
A
R
D
S
_
1
C
R
D
D
0
t
i
B
5
,
4
1
1
M
A
R
D
S
_
0
T
R
D
D
0
M
A
R
D
S
_
0
C
R
D
D
4
ICS93718
0434D--10/10/03
Recommended Operating Condition
SEL_DDR=0 SDRAM Outputs V
DD
=3.3V, T
A
= 0 - 85C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD3.3_2.5
3.0
3.3
3.6
V
DD2.5
2.3
2.5
2.7
Input High Voltage
V
IH
SEL_DDR, PD# input
2.0
V
Input Low Voltage
V
IL
SEL_DDR, PD# input
0.8
V
Input voltage level
V
IN
V
DD
V
1
Guaranteed by design, not 100% tested in production.
V
Power Supply Voltage
Absolute Maximum Ratings
Supply Voltage (VDD & VDD2.5) . . . . . . . . . -0.5V to 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . 0C to +85C
Case Temperature . . . . . . . . . . . . . . . . . . . . . 115C
Storage Temperature . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR = 0 SDRAM Outputs V
DD
= 3.3V, T
A
= 0 - 85C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Current
I
IH
V
I
= V
DD
or GND
1
10
A
Input Low Current
I
IL
V
I
=
V
DD
or GND
-100
-20
A
I
DD3.3_2.5
C
L
= 0pf, 133MHz
200
250
mA
I
DD2.5
C
L
= 0pf, 133MHz
100
200
mA
I
DDPD
C
L
= 0pf, all frequencies
3
10
mA
Output High Current
I
OH
V
DD
=
3.3V
,
V
OUT
= 1V
-74
-18
mA
Output Low Current
I
OL
V
DD
= 3.3V
,
V
OUT
= 1.2V
26
42
mA
V
DD
= 3.3V,
V
OH
= -12mA
V
DD
= 3.3V
I
OH
= 12mA
Input Capacitance
1
C
IN
V
I
=
GND or V
DD
2
pF
1
Guaranteed by design, not 100% tested in production.
V
Low-level output voltage
V
OL
0.4
0.35
2.95
Operating Supply Current
High-level output voltage V
OH
2
5
ICS93718
0434D--10/10/03
Recommended Operating Condition
SEL_DDR=1 DDR/DDR_SDRAM Outputs = 2.5V, T
A
= 0 - 85C (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD3.3_2.5
2.3
2.5
2.7
V
DD2.5
2.3
2.5
2.7
Input High Voltage
V
IH
SEL_DDR, PD# input
2.0
V
Input Low Voltage
V
IL
SEL_DDR, PD# input
0.8
V
Input voltage level
V
IN
V
DD
V
1
Guaranteed by design, not 100% tested in production.
V
Power Supply Voltage
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR = 1 DDR/DDR_SDRAM Outputs V
DD
=2.5, T
A
= 0 - 85C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Current
I
IH
V
I
= V
DD
or GND
1
10
A
Input Low Current
I
IL
V
I
=
V
DD
or GND
-100
-25
A
I
DD2.5
C
L
= 0pf, 133MHz
76
200
mA
I
DDPD
C
L
= 0pf, all frequencies
3
10
mA
Output High Current
I
OH
V
DD
=
2.5V
,
V
OUT
= 1V
-74.5
-18
mA
Output Low Current
I
OL
V
DD
= 2.5V
,
V
OUT
= 1.2V
26
42.5
mA
V
DD
= 2.5V,
V
OH
= -12mA
V
DD
= 2.5V
I
OH
= 12mA
Output differential-pair crossing
voltage
V
OC
(V
DD/
2) 0.1
1.25
(V
DD/
2) +0.1
V
Input Capacitance
1
C
IN
V
I
= GND or V
DD
2
pF
1
Guaranteed by design, not 100% tested in production.
Operating Supply Current
High-level output voltage
V
OH
1.7
V
Low-level output voltage
V
OL
0.46
2.3
0.35
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