Integrated
Circuit
Systems, Inc.
ICS93701
0417B--10/29/02
Block Diagram
DDR Phase Lock Loop Clock Driver
Pin Configuration
48-Pin TSSOP
Recommended Application:
DDR Clock Driver
Product Description/Features:
Low skew, low jitter PLL clock driver
I
2
C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Switching Characteristics:
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (66MHz):<120ps
CYCLE - CYCLE jitter (>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
DUTY CYCLE: 49.5% - 50.5%
Slew rate: 1V/ns - 2V/ns
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
SCLK
CLK_INT
CLK_INC
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
VDDI C
2
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
SDATA
FB_INC
VDD
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
FB_INT
FB_OUTC
ICS93701
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Functionality
S
T
U
P
N
I
S
T
U
P
T
U
O
e
t
a
t
S
L
L
P
D
D
V
A
T
N
I
_
K
L
C
C
N
I
_
K
L
C
T
K
L
C
C
K
L
C
T
T
U
O
_
B
F
C
T
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_
B
F
V
5
.
2
)
m
o
n
(
L
H
L
H
L
H
n
o
V
5
.
2
)
m
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n
(
H
L
H
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L
n
o
V
5
.
2
)
m
o
n
(
)
z
H
M
0
2
<
)
1
(
Z
Z
Z
Z
f
f
o
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
SCLK
SDATA
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKT6
CLKT7
CLKT8
CLKT9
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
CLKC6
CLKC7
CLKC8
CLKC9
2
ICS93701
0417B--10/29/02
Pin Descriptions
R
E
B
M
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N
N
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C
3
ICS93701
0417B--10/29/02
Byte 0: Output Control
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
0
3
,
9
2
1
8
C
K
L
C
,
8
T
K
L
C
6
t
i
B
6
2
,
7
2
1
9
C
K
L
C
,
9
T
K
L
C
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
Byte 1: Output Control
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
Byte 3: Reserved
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
Byte 4: Reserved
(1= enable, 0 = disable)
Byte 2: Reserved
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 5: Reserved
(1= enable, 0 = disable)
Note: Don't write into this register, writing into this
register can cause malfunction
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
2
,
3
1
0
C
K
L
C
,
0
T
K
L
C
6
t
i
B
6
,
5
1
1
C
K
L
C
,
1
T
K
L
C
5
t
i
B
9
,
0
1
1
2
C
K
L
C
,
2
T
K
L
C
4
t
i
B
9
1
,
0
2
1
3
C
K
L
C
,
3
T
K
L
C
3
t
i
B
3
2
,
2
2
1
4
C
K
L
C
,
4
T
K
L
C
2
t
i
B
7
4
,
6
4
1
5
C
K
L
C
,
5
T
K
L
C
1
t
i
B
3
4
,
4
4
1
6
C
K
L
C
,
6
T
K
L
C
0
t
i
B
0
4
,
9
3
1
7
C
K
L
C
,
7
T
K
L
C
4
ICS93701
0417B--10/29/02
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . . -0.5V to 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+ 0.5 V
Ambient Operating Temperature . . . . . . . . . . 0C to +85C
Storage Temperature . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Common Output Parameters
T
A
= 0 - 85
o
C; Supply Voltage A
VDD
, V
DD
= 2.5V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Current
I
IH
V
IN
= V
DD
or GND
5
A
Input Low Current
I
IL
V
IN
= V
DD
or GND
5
A
I
DD2.5
CL = 0pF @ 100MHz
185
210
mA
I
DDPD
CL = 0pF @ 100MHz
0.15
100
mA
Output High Current
I
OH
V
DD
= 2.3V, V
OUT
= 1V
-18
-32
mA
Output Low Current
I
OL
V
DD
= 2.3V, V
OUT
= 1.2V
26
35
mA
Input Clamp Voltage
V
IK
V
DDQ
= 2.3V I
IN
= -18mA
-1.2
V
V
DD
= min to max,
I
OH
= -1 mA
V
DDQ
= 2.3V,
I
OH
= -12 mA
V
DD
= min to max
I
OL
=1 mA
V
DDQ
= 2.3 V
I
OL
=12 mA
Input Capacitance
1
C
IN
V
IN
= GND or V
DD
3
pF
Output Capacitance
1
C
OUT
V
OUT
= GND or V
DD
3
pF
1
Guaranteed by design, not 100% tested in production.
Operating Supply
Current
High Impedance Output
Current
I
OZ
V
DD
=2.7V, V
OUT
=V
DD
or GND
0.1
10
A
0.6
V
OL
Low-level output voltage
High-level output voltage
V
OH
V
DDQ
- 0.1
1.7
V
V
0.05
2.45
V
V
0.35
0.1
2.10
5
ICS93701
0417B--10/29/02
Recommended Operating Condition (see note1)
T
A
= 0 - 85
o
C; Supply Voltage A
VDD
, V
DD
= 2.5V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DDQ
, A
VDD
2.3
2.5
2.7
V
DDI2C
2.3
3.6
V
V
IL
-0.3
0
V
DD
-0.4
V
V
IH
0.4
0.71
V
DD
+0.3
V
DC - CLKT, FB_INT
0.36
V
DDQ
+0.6
V
AC - CLKT, FB_INT
0.5
V
DDQ
+0.6
V
Output differential crossing
voltage
V
OX
V
DDQ
/2 -0.2
1.25
V
DDQ
/2 +0.2
V
1
Differential input signal voltage specifies the differential voltage [V
TR
- V
CP
] required for switching,
where V
TR
is the true input level and V
CP
is the complementary input level.
Input voltage level
Analog/core Supply
Voltage
Input differential-pair
voltage swing
1
V
ID
V
Input differential crossing
voltage
V
IX
0.45x(V
IH
-V
IL
)
0.55x(V
IH
-V
IL
)
Timing Requirements
T
A
= 0 - 85
o
C; Supply Voltage A
VDD
, V
DD
= 2.5V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freq
op
2.5V+0.2V @ 25
o
C
33
270
MHz
Application Frequency Range
freq
App
2.5V+0.2V @ 25
o
C
60
170
MHz
Input clock duty cycle
d
tin
40
60
%
from V
DD
= 3.3V to 1%
target freq.
100
s
CLK stabilization
T
STAB
6
ICS93701
0417B--10/29/02
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
High-to low level
propagation delay time
Output enable time
t
EN
PD# to any output
3
ns
Output disable time
tdis
PD# to any output
3
ns
Period Jitter
100/133/166MHz
-40
25
40
ps
Half-period jitter
t(jit_hper)
100/133/166MHz
-120
50
100
ps
Cycle to Cycle Jitter1
T
cyc-
T
cyc
100/133/166MHz
30
65
ps
Phase error
t
(phase error)
100/133/166Mhz
-150
-100
150
ps
Output to Output Skew
T
skew
60
100
ps
Pulse skew
T
skewp
60
100
ps
66MHz to 100MHz
49.5
50
50.5
%
101MHz to 133MHz
48.5
49
50
%
135MHz to 167MHz
48.5
49
50
%
Slew Rate
t
SLEW
Load = 120
/14pF
1
1.9
2
ps
Notes:
1. Refers to transition on noninverting outputs in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error increases at
high frequencies. This is due to the formula: duty cycle=t
wH
/t
c
, where the cycle (t
c
)
decreases as the frequency goes up.
Duty cycle
DC
2
3.5
t
PHL
1
CLK_IN to any output
3.5
t
PLH
1
CLK_IN to any output
ns
ns
7
ICS93701
0417B--10/29/02
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
8
ICS93701
0417B--10/29/02
Recommended Layout for the ICS93701
General Layout Precautions:
Use copper flooded ground on the top signal layer under the
clock buffer The area under U1 on the right is an example.
Flood over the ground vias.
1)
Use power vias for power and ground. Vias 20 mil or
larger in diameter have lower high frequency impedance.
Vias for signals may be minimum drill size.
2)
Make all power and ground traces are as wide as the via
pad for lower inductance.
3)
VAA for pin 16 has a low pass RC filter to decouple the
digital and analog supplies. The 4.7uF capacitors may be
replaced with a single low ESR device with the same
total capacitance. VAA is routed on a outside signal
layer. Do not cut a power or ground plane and route in it.
4)
Notice that ground vias are never shared.
5)
When ever possible, VCC (net V2P5 in the schematic)
pins have a decoupling capacitor. Power is always routed
from the plane connection via to the capacitor pad to the
VCC pin on the clock buffer. Moats or plane cuts are not
used to isolate power.
6)
Differential mode clock output traces are routed:
a.
With a ground trace between the pairs. Trace is
grounded on both ends.
b.
Without a ground trace, clock pairs are routed with a
separation of at least 5 times the thickness of the
dielectric. If the dielectric thickness is 4.5 mil, the
trace separation is at least 18 mils.
Component Values:
Ref Desg.
Value
Description
Package
C1,C4,C5,
C7,C11,C12
.01uF
CERAMIC MLC
0603
C2,C3,C8,
C9
4.7uF
CERAMIC MLC
1206
C10
.22uF
CERAMIC MLC
0603
C6
2200pF
CERAMIC MLC
0603
R12
120
0603
R9
4.7
0603
U1
ICS93701AG
TSSOP48
C2
4.7uF
1
2
V2P5
FB_IN#
C3
4.7uF
1
2
V2A5
C9
4.7uF
1
2
C7
.01uF
1
2
V2P5
C16
.01uF
1
2
C10
.22uF
1
2
C1
.01uF
1
2
C5
.01uF
1
2
C11
.01uF
1
2
R12
120
1
2
V2A5
V2A5
CLK_IN#
U1
ICS93701
16
4
11
15
21
28
34
38
45
1
7
8
18
24
25
31
41
42
48
17
35
36
13
14
37
12
3
2
5
6
10
9
20
19
22
23
46
47
44
43
39
40
29
30
27
26
33
32
AVDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AGND
FB_INT
FB_INC
CLK_INT
CLK_INC
SDA
SCL
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
FB_OUTT
FB_OUTC
C12
.01uF
1
2
C6
.0022pF
1
2
SCL
R9
4.7
1
2
C13
.01uF
1
2
SDA
C14
.01uF
1
2
FB_IN
C8
4.7uF
1
2
C15
.01uF
1
2
CLK_IN
C4
.01uF
1
2
9
ICS93701
0417B--10/29/02
Ordering Information
ICS93701yGT
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y G - PPP - T
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
- C -
- C -
b
c
L
aaa
C
MIN
MAX
MIN
MAX
A
--
1.20
--
.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
D
E
E1
6.00
6.20
.236
.244
e
L
0.45
0.75
.018
.030
N
0
8
0
8
aaa
--
0.10
--
.004
VARIATIONS
MIN
MAX
MIN
MAX
48
12.40
12.60
.488
.496
10-0039
6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil) (20 mil)
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS
SEE VARIATIONS
8.10 BASIC
0.319 BASIC
0.50 BASIC
0.020 BASIC
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
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