Integrated
Circuit
Systems, Inc.
ICS9248-128
Third party brands and names are the property of their respective owners.
Block Diagram
9248-128 Rev B 11/16/00
Functionality
Pin Configuration
Recommended Application:
SIS 530/620 style chipset
Output Features:
- 3 CPU @ 2.5V/3.3V up to 133.3 MHz.
- 6 PCI @ 3.3V (including 1 free-running)
- 13 SDRAMs @ 3.3V up to 133.3MHz.
- 3 REF @ 3.3V, 14.318MHz
- 1 clock @ 24/14.3 MHz selectable output for SIO
- 1 Fixed clock at 48MHz (3.3V)
- 1 IOAPIC @ 2.5V / 3.3V
Features:
Up to 133MHz frequency support
Support power management: CPU, PCI, SDRAM stop and
Power down Mode from I
2
C programming.
Spread spectrum for EMI control ( 0.25% center spread
& 0 to -0.5% down spread).
Uses external 14.318MHz crystal
FS pins for frequency select
Key Specifications:
CPU CPU<175ps
SDRAM SDRAM < 350ps
CPUSDRAM < 500ps
CPU(early) PCI : 1-4ns (typ. 2ns)
PCI PCI <500ps
Frequency Generator & Integrated Buffers
VDDR/X
*MODE/REF0
GNDREF
X1
X2
VDDPCI
*FS1/PCICLK_F
*FS2.PCICLK0
GNDPCI
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
SDRAM12
GNDSDR
*CPU_STOP# /SDRAM11
*PCI_STOP# /SDRAM10
VDDSD/C
*SDRAM_STOP# /SDRAM9
*PD# /SDRAM8
GNDFIX
SDATA
SCLK
VDDLAPIC
IOAPIC
REF1/SD_SEL#*
GNDLAPIC
REF2/CPU2.5_3.3#*
CPUCLK1
VDDLCPU
CPUCLK2
CPUCLK3
GNDCPU
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GNDSDR
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GNDSDR
48MHz/FS0*
SIO/SEL24_14#MHz*
ICS9248
-128
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-Pin SSOP
* Internal Pull-up Resistor of
120K to 3.3V on indicated inputs
CPU_STOP#
SDRAM_STOP#
PCI_STOP#
PD#
PLL2
PLL1
Spread
Spectrum
48MHz
SIO
REF(2:0)
IOAPIC
CPUCLK (3:1)
SDRAM (12:0)
PCICLK (4:0)
PCICLK_F
X1
X2
SEL24_14#
XTAL
OSC
PCI
CLOCK
DIVDER
STOP
STOP
SDATA
SCLK
MODE
FS(2:0)
CPU3.3#_2.5
SD_SEL#
Control
Logic
Config.
Reg.
LATCH
POR
PCI_STOP
CPU_STOP
3
3
13
5
5
3
/2
SD_SEL FS2
FS1
FS0
CPU
MHZ
SDRAM
M HZ
PCI
MHZ
0
0
0
0
90.00
90.00
30.00
0
0
0
1
66.70
100.05
33.35
0
0
1
0
95.00
63.33
31.66
0
0
1
1
100.00
66.66
33.33
0
1
0
0
100.00
75.00
30.00
0
1
0
1
112.00
74.66
37.33
0
1
1
0
124.00
82.66
31.00
0
1
1
1
97.00
97.00
32.33
1
0
0
0
66.70
66.70
33.35
1
0
0
1
75.00
75.00
30.00
1
0
1
0
83.30
83.30
33.32
1
0
1
1
95.00
95.00
31.66
1
1
0
0
100.00
100.00
33.33
1
1
0
1
112.00
112.00
37.33
1
1
1
0
124.00
124.00
31.00
1
1
1
1
133.30
133.30
33.33
Note: REF, IOAPIC = 14.318MHz
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9248-128
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
P in num b er
P in nam e
T yp e
D escription
1
V DDR/X
P ower
Is olated 3.3 V power for c ry s tal & referenc e
RE F0
O utput
3.3V , 14.318 M Hz referenc e c loc k output.
M ode
Input
Func tion s elec t pin, 1= des k top m ode, 0= m obile m ode. Latc hed input.
3,9,16,22,
27,33,39
G ND
P ower
3.3 V Ground
4
X 1
Input
14.318 M Hz c ry s tal input
5
X 2
O utput
14.318 M Hz c ry s tal output
6,14
V DDP CI
P ower
3.3 V power for the P CI c loc k outputs
FS 1
Input
Logic input frequenc y s elec t bit. Input latc hed at power-on.
P CICLK _F
O utput
3.3 V free running P CI c loc k output, will not be s topped by the P CI_S TO P #
P CICLK 0
O utput
3.3 V P CI c loc k outputs , generating tim ing requirem ents for P entium II
FS 2
Input
Logic input frequenc y s elec t bit. Input latc hed at power-on.
13, 12, 11, 10
P CICLK (4:1)
O utput
3.3 V P CI c loc k outputs , generating tim ing requirem ents for P entium II
15,28,29,31,32,
34,35,37,38
S DRA M 12,
S DRA M (7:0)
O utput
S DRA M c loc k outputs . Frequenc y is s elec ted by S D-S el latc hed input.
S DRA M 11
O utput
S DRA M c loc k outputs . Frequenc y is s elec ted by S D-S el latc hed input.
CP U_S TOP #
Input
A s y nc hronous ac tiv e low input pin us ed to s top the CP UCLK in low s tate,
all other c loc k s will c ontinue to run. The CP UCLK will hav e a "Turnon" latenc y
of at leas t 3 CP U c loc k s .
S DRA M 10
O utput
S DRA M c loc k outputs . Frequenc y is s elec ted by S D-S E L latc hed input.
P CI-S TO P #
Input
S y nc hronous ac tiv e low input us ed to s top the P CICLK in a low s tate. It will not
effec t P CICLK _F or any other outputs .
19
V DDS D/C
P ower
3.3 V power for S DRA M outputs and c ore
S DRA M 9
O utput
S DRA M c loc k outputs . Frequenc y is s elec ted by S D-S el latc hed input.
S DRA M _S TOP #
Input
A s y nc hronous ac tiv e low input us ed to s top the S DRA M in a low s tate.
It will not effec t any other outputs .
S DRA M 8
O utput
S DRA M c loc k outputs . Frequenc y is s elec ted by S D-S el latc hed input.
P D#
Input
A s y nc hronous ac tiv e low input pin us ed to power down the dev ic e into a low
power s tate. The internal c loc k s are dis abled and the V CO and the c ry s tal are
s topped. The latenc y of the power down will not be greater than 3m s .
23
S DA TA
Input
Data input for I
2
C s erial input.
24
S CLK
Input
Cloc k input of I
2
C input
S E L24_14#
Input
This input pin c ontrols the frequenc y of the S IO . If logic 0 at power on
S IO= 14.318 M Hz . If logic 1 at power-on S IO = 24M Hz .
S IO
O utput
S uper I/O output. 24 or 14.318 M Hz . S elec table at power-up by S E L24_14M Hz
FS 0
Input
Logic input frequenc y s elec t bit. Input latc hed at power-on.
48 M Hz
O utput
3.3 V 48 M Hz c loc k output, fix ed frequenc y c loc k ty pic ally us ed with
US B dev ic es
30,36
V DDS DR
P ower
3.3 V power for S DRA M outputs
40,41,43
CP UCLK (3:1)
0utput
2.5 V CP U and Hos t c loc k outputs
42
V DDLCP U
P ower
2.5 V power for CP U
RE F2
O utput
3.3V , 14.318 M Hz referenc e c loc k output.
CP U3.3#_2.5
Input
This pin s elec ts the operating v oltage for the CP U. If logic 0 at power on
CP U= 3.3 V and if logic 1 at power on CP U= 2.5 V operating v oltage.
45
GNDL
P ower
2.5 V Ground for the IOA P IC or CP U
RE F1
O utput
3.3V , 14.318 M Hz referenc e c loc k output.
S D_S E L#
Input
This input pin c ontrols the frequenc y of the S DRA M .
47
IOA P IC
O utput
2.5V fix ed 14.318 M Hz IO A P IC c loc k outputs
48
V DDLA P IC
P ower
2.5 V power for IOA P IC
2
1, 2
8
1, 2
26
1,2
7
1, 2
46
1,2
44
1,2
17
1
20
1
18
1
21
1
25
1,2
3
ICS9248-128
Third party brands and names are the property of their respective owners.
Power Management Functionality
Mode Pin - Power Management Input Control
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
PD#
CPU_STOP# PCI_STOP# SDRAM_STOP
PCICLK
(0:4)
SDRAM
(0:12)
PCICLK_F
CPUCLK
Crystal
OSC
VCO
0
X
X
X
Stopped
Low
Stopped
Low
Stopped
Low
Stopped
Low
Stopped
Low
Stopped
Low
1
1
1
1
Running
Running
Running
Running
Running
Running
1
1
1
0
Running
Stopped
Low
Running
Running
Running
Running
1
1
0
1
Stopped
Low
Running
Running
Running
Running
Running
1
1
0
0
Stopped
Low
Stopped
Low
Running
Running
Running
Running
1
0
1
1
Running
Running
Running
Stopped
Low
Running
Running
1
0
1
0
Running
Stopped
Low
Running
Stopped
Low
Running
Running
1
0
0
1
Stopped
Low
Running
Running
Stopped
Low
Running
Running
1
0
0
0
Stopped
Low
Stopped
Low
Running
Stopped
Low
Running
Running
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The ICS9248-128 is the single chip clock solution for Desktop/Notebook designs using the SIS style chipset. It provides all
necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-128 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection. The SD_SEL
latched input allows the SDRAM frequency to follow the CPUCLK frequency(SD_SEL=1) or other clock frequencies
(SD_SEL=0)
General Description
4
ICS9248-128
Third party brands and names are the property of their respective owners.
Byte 0: Functionality and frequency select register (Default = 0)
Serial Configuration Command Bitmap
Note 1: Default at power-up will be for latched logic inputs to define frequency.
I
2
C readback of the power up default indicates the revision ID code in bit 2, 6:4 as shown.
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ICS9248-128
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
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