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Электронный компонент: ICS9248yF-126-T

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ICS9248-126
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
Block Diagram
9248-126 Rev C 9/6/00
Recommended Application:
Motherboard Single chip clock solution for Pentium II/III and
K6 processors, using SIS540/SIS630 style chipset.
Output Features:
3- CPUs @ 2.5/3.3V, up to 166MHz.
14 - SDRAM @ 3.3V
7- PCI @3.3V,
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz).
2- REF @3.3V, 14.318MHz.
Features:
Up to 166MHz frequency support
Support FS0-FS3 trapping status bit for I
2
C read back.
Support power management: CPU, PCI, SDRAM stop
and Power down Mode form I
2
C programming.
Spread spectrum for EMI control (0 to -0.5%, 0.25%).
FS0, FS1, FS3 must have a internal 120K pull-Down
to GND.
Uses external 14.318MHz crystal
Skew Specifications:
CPU - CPU: < 175ps
SDRAM - SDRAM < 500ps
PCI - PCI: < 500ps
CPU - SDRAM: < 500ps
CPU - PCI: 1 - 4ns
Functionality
CPU2.5_3.3#
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK (2:0)
SDRAM (13:0)
PCICLK (6:0)
X1
X2
XTAL
OSC
PCI
CLOCK
DIVDER
CPU
CLOCK
DIVDER
SDRAM
CLOCK
DIVDER
SDATA
SCLK
FS(3:0)
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
LATCH
2
3
14
7
4
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
Frequency Generator & Integrated Buffers for Celeron & P
II
/
III
TM & K6
VDDREF
* REF0/FS3
GND
X1
X2
VDDPCI
*PCICLK0/FS1
*PCICLK1/FS2
PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VDDSDR
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDATA
SCLK
1
REF1
VDDLCPU
CPUCLK0
CPUCLK1
GND
CPUCLK2
VDDSDR
SDRAM13
SDRAM12
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GNDSDR
SDRAM7
SDRAM6
VDDSDR
SDRAM5
SDRAM4
VDDSDR
48MHz/FS0*
24_48MHz/CPU2.5_3.3#*
1
ICS9248-126
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3
S
F
2
S
F
1
S
F
0
S
F
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6
6
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0
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1
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3
3
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1
0
.
0
0
1
0
.
0
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3
3
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0
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7
3
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3
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0
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3
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8
.
6
6
6
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3
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4
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3
3
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0
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3
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3
3
1
3
.
3
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7
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3
3
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3
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3
3
1
3
.
3
3
1
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8
.
6
6
8
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6
6
4
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3
3
1
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0
1
0
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7
9
0
.
7
9
3
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2
3
1
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1
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0
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5
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5
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6
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7
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1
3
1
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2
1
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2
1
1
3
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7
3
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7
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3
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2
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2
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2
3
1
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.
6
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6
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2
3
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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2
ICS9248-126
Third party brands and names are the property of their respective owners.
The ICS9248-126 is the single chip clock solution for
Desktop/Notebook designs using the SIS 540/630 style
chipset. It provides all necessary clock signals for such a
system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-126
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection.
General Description
Power Groups
VDDREF = REF, X1, X2
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM, supply for PLL core,
VDD48 = 48MHz, 24MHz
VDDLCPU = CPUCLKs
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 6, 15, 19, 27, 30,
36, 42
VDD
PWR
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48M Hz output
REF0
OUT
14.318 M Hz reference clock.
FS3
IN
Frequency select pin.
3, 10, 16, 22,
33, 39, 44
GND
PWR
Ground pin for 3V outputs.
4
X1
IN
Crystal input,nominally 14.318M Hz.
5
X2
OUT
Crystal output, nominally 14.318M Hz.
FS1
IN
Frequency select pin.
PCICLK0
OUT
PCI clock outputs.
FS2
IN
Frequency select pin.
PCICLK1
OUT
PCI clock outputs.
14, 13, 12, 11, 9
PCICLK (6:2)
OUT
PCI clock outputs.
41, 40, 38, 37, 35,
34, 32, 31, 29, 28,
21, 20, 18, 17
SDRAM (13:0)
OUT
SDRAM clock outputs
23
SDATA
I/O
Data pin for I
2
C circuitry 5V tolerant
24
SCLK
IN
Clock input of I2C input, 5V tolerant input
CPU2.5_3.3#
IN
Voltage select 2.5V when high - 3.3V when low
24_48M Hz
OUT
Clock output for super I/O/USB default is 24M Hz
FS0
IN
Frequency select pin.
48M Hz
OUT
48MHz output clock
43, 45, 46
CPUCLK (2:0)
OUT
CPU clock outputs.
47
VDDLCPU
PWR
Power pin for the CPUCLKs. 2.5V
48
REF1
OUT
14.318 M Hz reference clock.
26
2
7
8
25
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3
ICS9248-126
Third party brands and names are the property of their respective owners.
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Read:
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4
ICS9248-126
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I
2
C readback for Bits 7, 2, 6:4 indicate the revision code.
I
2
C is a trademark of Philips Corporation
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5
ICS9248-126
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
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6
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I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
T
I
B
#
N
I
P
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8
4
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4
2
6
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2
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M
8
4
5
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B
1
4
1
3
1
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A
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4
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0
4
1
2
1
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A
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3
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B
8
3
1
1
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A
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2
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B
7
3
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1
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A
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1
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5
3
1
9
M
A
R
D
S
0
t
i
B
4
3
1
8
M
A
R
D
S
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
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W
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N
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r
e
s
e
R
5
t
i
B
-
1
#
3
S
F
4
t
i
B
-
1
#
2
S
F
3
t
i
B
-
1
#
1
S
F
2
t
i
B
-
1
#
0
S
F
1
t
i
B
8
4
1
)
t
c
a
n
I
/
t
c
A
(
1
F
E
R
0
t
i
B
2
1
)
t
c
a
n
I
/
t
c
A
(
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
2
3
1
)
t
c
a
n
I
/
t
c
A
(
7
M
A
R
D
S
6
t
i
B
1
3
1
)
t
c
a
n
I
/
t
c
A
(
6
M
A
R
D
S
5
t
i
B
9
2
1
)
t
c
a
n
I
/
t
c
A
(
5
M
A
R
D
S
4
t
i
B
8
2
1
)
t
c
a
n
I
/
t
c
A
(
4
M
A
R
D
S
3
t
i
B
1
2
1
)
t
c
a
n
I
/
t
c
A
(
3
M
A
R
D
S
2
t
i
B
0
2
1
)
t
c
a
n
I
/
t
c
A
(
2
M
A
R
D
S
1
t
i
B
8
1
1
)
t
c
a
n
I
/
t
c
A
(
1
M
A
R
D
S
0
t
i
B
7
1
1
)
t
c
a
n
I
/
t
c
A
(
0
M
A
R
D
S
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
#
8
4
_
4
2
L
E
S
)
0
o
t
t
e
s
n
e
h
w
z
H
M
8
4
(
)
1
o
t
t
e
s
n
e
h
w
z
H
M
4
2
(
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
3
4
1
)
t
c
a
n
I
/
t
c
A
(
2
K
L
C
U
P
C
2
t
i
B
5
4
1
)
t
c
a
n
I
/
t
c
A
(
1
K
L
C
U
P
C
1
t
i
B
6
4
1
)
t
c
a
n
I
/
t
c
A
(
0
K
L
C
U
P
C
0
t
i
B
-
1
d
e
v
r
e
s
e
R
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Dont write into this register, writing into this
register can cause malfunction