Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9248-64
Block Diagram
9248-64 Rev C 03/19/01
Pin Configuration
48-Pin SSOP
AMD-K is a trademark of Advanced Micro Devices.
Generates the following system clocks:
- 3 differential pair open drain CPU clocks
(1.5V external
pull-up; up to 133MHz).
- 8 PCI including 1 free running (3.3V) @33.3MHz.
- 2 AGP(3.3V) up to 66.6MHz.
- 2 REF(3.3V)@14.318MHz
- 1 48MHz(3.3V)
- 24 / 48MHz(3.3V)
Skew characteristics:
- CPU -CPU<250ps
- CPUt - CPUc <200ps (differential pair)
- PCI PCI: <500ps
- CPU SDRAM_OUT: < 250ps
- CPU AGP <500ps
Efficient Power Management through PD#, PCI_STOP#
and CPU_STOP#.
Spread Spectrum option for EMI reduction
(-1.0% down spread).
Uses external 14.318 MHz crystal
The ICS9248-64 is a main clock synthesizer chip for AMD-
K7 based systems. This provides all clocks required for such
a system when used with a Zero Delay Buffer Chip such as
the ICS9179-06.
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. The
ICS9248-64 employs a proprietary closed loop design, which
tightly controls the percentage of spreading over process and
temperature variations.
*FS0/REF0
*FS1/REF1
GNDREF
X1
X2
GNDPCI
PCICLK_F
PCICLK0
VDDPCI
PCICLK1
PCICLK2
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
VDDAGP
AGP0
AGP1
GNDAGP
VDD48
48MHz
SEL24_48#/24-48MHz
VDDREF
GNDSD
SDRAM_OUT
VDDSD
RESERVED
CPUCLKC2
CPUCLKT2
GNDCPU
CUCLKC1
CPUCLKT1
GND
CPUCLKC0
CPUCLKT0
RESERVED
VDD
GND
PCI_STOP#
CPU_STOP#
PD#
SPREAD#
TEST#
SDATA
SCLK
GND48
ICS9248-64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
{
I C
2
AMD-K7
TM
System Clock Chip
* Internal 120K pullup resistor on indicated inputs
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
4
ICS9248-64
I
2
C Command Bitmaps
Byte 0: Reserved for Buffer
T
I
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#
N
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Byte 1: Reserved for Buffer
T
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Byte 2: Reserved for Buffer
T
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(
Byte 3: Reserved for Buffer
T
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(
5
ICS9248-64
Byte 4: Clock Control Register
Notes: A value of '1'b is enable, '0'b is disable
Byte 6: SDRAM Clock & Generator Mode Control Register
Notes: A value of '1'b is enable, '0'b is disable
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Byte 5: PCI Clock Control Register
Notes: A value of '1'b is enable, '0'b is disable
T
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N
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