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Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9179-06
Block Diagram
PentiumPro is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
Zero Delay Buffers
9179-06 Rev F 6/22/99
Pin Configuration
The ICS9179-06 generates low skew clock buffers required
for high speed RISC or CISC microprocessor systems such as
Intel PentiumPro. An output enable is provided for testability.
The device is a buffer with low output to output skew. This is
a zero delay buffer device, using an internal PLL. This buffer
can be used for phase synchronization to a master clock. With
the wide PLL loop BW, this buffer is compatible to Spread
Spectrum input clocks from clock generator products such as
the ICS9148-27.
The individual clock outputs are addressable through I
2
C to be
enabled, or stopped in a low state for reduced EMI when the
lines are not needed. The device defaults to zero-delay mode,
but can be programmed with I
2
C for selectable delays -2.7,
+2.0, -0.7 ns (nominal target values).
Zero delay buffer, 16 outputs
Supports up to four SDRAM DIMMS
Wide PLL loop bandwidth makes this part ideal in
Spread Spectrum applications.
Skew Input to FB_IN 250ps default, with selectable
skew -2.7, +2.0, -0.7ns nominal.
Synchronous clocks skew matched to 250ps window on
output.
33 to 133MHz input or output frequency.
I
2
C Serial Configuration interface to allow individual
clocks to be stopped, or selectable delays.
Multiple VDD, VSS pins for noise reduction
Slew rate 1.5V/ns into 30pF.
VDD = 3.3 5%, 0 to 70C
All outputs (0:15) tristate with OE low
(FB_OUT stays running).
48-Pin SSOP package
48-Pin SSOP
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Functionality
#
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ICS9179-06
Pin Descriptions
Power Groups
VDD = Power supply for OUTPUT buffers
VDDS = Power supply for I
2
C circuitry
VDDA = Power supply for Analog PLL circuitry
Notes:
1.
At power up all sixteen outputs are enabled and active.
2.
OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
3.
The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for
complete platform flexibility.
4.
I
2
C Byte0, bits 0 & 1 used to select delay. Default* values at power up is 0
5.
Subject to design engineering verification of target value.
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P
Ground Groups
GND = Ground supply for OUTPUT buffer
GNDS = Ground supply for I
2
C circuitry
GNDA = Ground supply for Analog PLL circuitry
Delay Selection Table
4
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2
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2
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-
3
ICS9179-06
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
4
ICS9179-06
Byte 2: OUTPUT Clock Register (Default = 1)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
T
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Byte 3: OUTPUT Clock Register
Notes: 1 = Enabled; 0 = Disabled, outputs held low
T
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R
ICS9179-06 Power Management
The values below are estimates of target specifications.
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.
3
=
D
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0
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1
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0
8
1
Note: PWD = Power-Up Default
Byte 0: OUTPUT Clock Register (default = 0)
Notes: 2 = Default = 0; 1 = Delay element enabled,
0 = No delay path.
T
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B
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7
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6
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5
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4
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3
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2
3
1
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C
w
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k
S
N
I
B
F
Serial Configuration Command Bitmaps
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 1: OUTPUT Clock Register
T
I
B
#
N
I
P
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N
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D
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7
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6
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1
1
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6
T
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5
t
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6
1
1
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c
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A
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5
T
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4
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5
1
1
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4
T
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3
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0
1
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3
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2
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9
1
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I
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2
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1
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1
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0
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Note: PWD = Power-Up Default
5
ICS9179-06
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input & Supply
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+0.3
V
Input Low Voltage
V
IL
V
SS
-0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
5
uA
Input Low Current
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
-5
uA
Input Low Current
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-60
-33
uA
Operating
I
DD
C
L
= 0 pF; F
IN
@ 66M
115
150
mA
Supply Current
C
L
= 0 pF; F
IN
@ 100M
170
180
mA
Output Disabled
I
DD
C
L
= 0 pF; F
IN
@ 66M
30
mA
Supply Current
C
L
= 0 pF; F
IN
@ 100M
30
mA
Input frequency
F
i
V
DD
= 3.3 V; All Outputs Loaded
33
105
MHz
Input Capacitance
C
IN
Logic Inputs
5
pF
1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - Input & Supply
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+0.3
V
Input Low Voltage
V
IL
V
SS
-0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
5
uA
I
IL
V
IN
= 0 V; Inputs with no pull-up resistors
-5
uA
I
IL
V
IN
= 0 V; Inputs with 100K pull-up resistors
-60
-33
uA
Operating
I
DD1
C
L
= 0 pF; F
IN
@ 66M
115
150
mA
Supply Current
I
DD2
C
L
= 0 pF; F
IN
@ 100M
170
180
mA
Input frequency
F
i
1
V
DD
= 3.3 V; All Outputs Loaded
10
150
MHz
Input Capacitance
C
IN
1
Logic Inputs
5
pF
1
Guarenteed by design, not 100% tested in production.
Input Low Current
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