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Электронный компонент: ICS874003

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Integrated
Circuit
Systems, Inc.
874003AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
1
ICS874003
PCI E
XPRESS
J
ITTER
A
TTENUATOR
F_SELA
0 5
(default)
1 4
F_SELB
0 5
(default)
1 4
VCO
490 - 640MHz
Phase
Detector
M = 5
(fixed)
G
ENERAL
D
ESCRIPTION
The ICS874003 is a high performance Dif-
ferential-to-LVDS Jitter Attenuator designed for
use in PCI Express systems. In some PCI
Express systems, such as those found in
desktop PCs, the PCI Express clocks are
generated from a low bandwidth, high phase noise PLL
frequency synthesizer. In these systems, a jitter attenuator
may be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer
and from the system board. The ICS874003 has 3 PLL
bandwidth modes: 200kHz, 400kHz, and 800kHz. The
200kHz mode will provide maximum jitter attenuation, but
with higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated. The 400kHz provides an intermediate bandwidth
that can easily track triangular spread profiles, while
providing good jitter attenuation. The 800kHz bandwidth
provides the best tracking skew and will pass most spread
profiles, but the jitter attenuation will not be as good as the
lower bandwidth modes. Because some 2.5Gb serdes have
x20 multipliers while others have than x25 multipliers, the
ICS874003 can be set for 1:1 mode or 5/4 multiplication
mode (i.e. 100MHz input/125MHz output) using the FSEL pins.
The ICS874003 uses ICS 3
rd
Generation FemtoClock
TM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package,
making it ideal for use in space constrained applications
such as PCI Express add-in cards.
F
EATURES
Three Differential LVDS output pairs
One Differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 160MHz
Input frequency range: 98MHz - 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 35ps (maximum)
3.3V operating supply
Three bandwidth modes allow the system designer to
make jitter attenuation/tracking skew design trade-offs
0C to 70C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
HiPerClockSTM
ICS
QA0
nQA0
B
LOCK
D
IAGRAM
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~400kHz (default)
1 = PLL Bandwidth: ~800kHz
PLL B
ANDWIDTH
Pulldown
OEA
F_SELA
BW_SEL
CLK
nCLK
F_SELB
MR
OEB
QA1
nQA1
QB0
nQB0
Pulldown
Pulldown
Pullup
Pullup
Pullup
Float
P
IN
A
SSIGNMENT
ICS874003
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
QA1
V
DDO
QA0
nQA0
MR
BW_SEL
nc
V
DDA
F_SELA
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nQA1
V
DDO
QB1
nQB1
F_SELB
OEB
GND
nCLK
CLK
OEA
Pulldown
0 = ~200kHz
Float = ~400kHz
1 = ~800kHz
background image
Integrated
Circuit
Systems, Inc.
874003AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
2
ICS874003
PCI E
XPRESS
J
ITTER
A
TTENUATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
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IN
C
HARACTERISTICS
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ABLE
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background image
Integrated
Circuit
Systems, Inc.
874003AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
3
ICS874003
PCI E
XPRESS
J
ITTER
A
TTENUATOR
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
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background image
Integrated
Circuit
Systems, Inc.
874003AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
4
ICS874003
PCI E
XPRESS
J
ITTER
A
TTENUATOR
T
ABLE
4D. LVDS DC C
HARACTERISTICS
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background image
Integrated
Circuit
Systems, Inc.
874003AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
5
ICS874003
PCI E
XPRESS
J
ITTER
A
TTENUATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
C
YCLE
-
TO
-C
YCLE
J
ITTER
D
IFFERENTIAL
I
NPUT
L
EVEL
3.3V LVDS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
V
DD
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
D
IFFERENTIAL
O
UTPUT
V
OLTAGE
S
ETUP
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
QAx,
QB0
nQAx,
nQB0
QAx,
QB0
nQAx,
nQB0
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
SCOPE
Qx
nQx
LVDS
3.3V5%
POWER SUPPLY
+
Float GND
V
DD,
V
DDO
V
DDA
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
O
FFSET
V
OLTAGE
S
ETUP
t
sk(o)
nQy
Qy
nQx
Qx

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