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Электронный компонент: ICS8735-01

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8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS8735-01 is a highly versatile 1:5 Differ-
ential-to-3.3V LVPECL clock generator and a
member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
ICS8735-01 has a fully integrated PLL and can
be configured as zero delay buffer, multiplier or divider, and
has an output frequency range of 31.25MHz to 700MHz. The
reference divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-
input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The
external feedback allows the device to achieve "zero delay"
between the input clock and the output clocks. The PLL_SEL
pin can be used to bypass the PLL for system test and debug
purposes. In bypass mode, the reference clock is routed
around the PLL and into the internal output dividers.
F
EATURES
5 differential 3.3V LVPECL outputs
Selectable differential clock inputs
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
External feedback for "zero delay" clock regeneration
with configurable frequencies
Cycle-to-cycle jitter: 25ps (maximum)
Output skew: 25ps (maximum)
Static phase offset: 50ps 100ps
3.3V supply voltage
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32-Lead VFQFN
5mm x 5mm x 0.95 package body
K Package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
CCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
CCO
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
V
CCO
Q0
nQ0
V
EE
SEL2
FB_IN
nFB_IN
V
CC
V
CCO
nQ4
Q4
V
EE
SEL3
V
CCA
PLL_SEL
V
CC
ICS8735-01
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
1
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
0
1
1, 2, 4, 8,
16, 32, 64
8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
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8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
3
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
3A. C
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a
r
y
c
n
e
u
q
e
r
f
O
C
V
:
E
T
O
N
*
T
ABLE
3B. PLL B
YPASS
F
UNCTION
T
ABLE
s
t
u
p
n
I
s
t
u
p
t
u
O
0
=
L
E
S
_
L
L
P
e
d
o
M
s
s
a
p
y
B
L
L
P
3
L
E
S
2
L
E
S
1
L
E
S
0
L
E
S
4
Q
n
:
0
Q
n
,
4
Q
:
0
Q
0
0
0
0
4
0
0
0
1
4
0
0
1
0
4
0
0
1
1
8
0
1
0
0
8
0
1
0
1
8
0
1
1
0
6
1
0
1
1
1
6
1
1
0
0
0
2
3
1
0
0
1
4
6
1
0
1
0
2
1
0
1
1
2
1
1
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4
1
1
0
1
1
1
1
1
0
2
1
1
1
1
1
8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
4
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
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l
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p
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m
u
m
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M
s
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n
U
V
C
C
e
g
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y
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p
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C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
C
C
e
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a
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l
a
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A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
O
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C
e
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a
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l
o
V
y
l
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S
t
u
p
t
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O
5
3
1
.
3
3
.
3
5
6
4
.
3
V
I
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E
t
n
e
r
r
u
C
y
l
p
p
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S
r
e
w
o
P
0
5
1
A
m
I
A
C
C
t
n
e
r
r
u
C
y
l
p
p
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S
g
o
l
a
n
A
5
1
A
m
l
o
b
m
y
S
r
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t
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m
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d
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T
m
u
m
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l
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m
u
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I
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p
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t
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h
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i
H
N
I
_
B
F
,
1
K
L
C
,
0
K
L
C
V
N
I
V
=
C
C
V
5
6
4
.
3
=
0
5
1
A
N
I
_
B
F
n
,
1
K
L
C
n
,
0
K
L
C
n
V
N
I
V
=
C
C
V
5
6
4
.
3
=
5
A
I
L
I
t
u
p
n
I
t
n
e
r
r
u
C
w
o
L
N
I
_
B
F
,
1
K
L
C
,
0
K
L
C
V
N
I
V
,
V
0
=
C
C
V
5
6
4
.
3
=
5
-
A
N
I
_
B
F
n
,
1
K
L
C
n
,
0
K
L
C
n
V
N
I
V
,
V
0
=
C
C
V
5
6
4
.
3
=
0
5
1
-
A
V
P
P
e
g
a
t
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e
P
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1
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0
3
.
1
V
V
R
M
C
2
,
1
E
T
O
N
;
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g
a
t
l
o
V
t
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p
n
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M
n
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m
m
o
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V
E
E
5
.
0
+
V
C
C
5
8
.
0
-
V
V
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i
K
L
C
n
,
K
L
C
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t
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o
F
:
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T
O
N
C
C
.
V
3
.
0
+
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s
a
d
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n
i
f
e
d
s
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a
t
l
o
v
e
d
o
m
n
o
m
m
o
C
:
2
E
T
O
N
H
I
.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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t
e
m
a
r
a
P
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V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
2
V
C
C
3
.
0
+
V
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
3
.
0
-
8
.
0
V
I
H
I
t
n
e
r
r
u
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t
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p
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,
0
L
E
S
,
R
M
,
L
E
S
_
K
L
C
3
L
E
S
,
2
L
E
S
,
1
L
E
S
V
N
I
V
=
C
C
=
V
5
6
4
.
3
0
5
1
A
L
E
S
_
L
L
P
V
N
I
V
=
C
C
=
V
5
6
4
.
3
5
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
,
0
L
E
S
,
R
M
,
L
E
S
_
K
L
C
3
L
E
S
,
2
L
E
S
,
1
L
E
S
V
N
I
V
,
V
0
=
C
C
V
5
6
4
.
3
=
5
-
A
L
E
S
_
L
L
P
V
N
I
V
,
V
0
=
C
C
V
5
6
4
.
3
=
0
5
1
-
A
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, V
O
-0.5V to V
CCO
+ 0.5V
Package Thermal Impedance,
JA
32 Lead LQFP
47.9C/W (0 lfpm)
32 Lead VFQFN
34.8C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
5
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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t
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m
a
r
a
P
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t
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m
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T
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V
H
O
1
E
T
O
N
;
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t
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p
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C
4
.
1
-
V
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C
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1
-
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T
O
N
;
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g
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C
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.
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T
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5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
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0
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L
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0
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L
C
1
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L
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n
,
1
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L
C
1
=
L
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S
_
L
L
P
5
2
.
1
3
0
0
7
z
H
M
0
=
L
E
S
_
L
L
P
0
0
7
z
H
M
8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
6
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
D
IFFERENTIAL
I
NPUT
L
EVEL
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
C
YCLE
-
TO
-C
YCLE
J
ITTER
-1.3V 0.165V
tsk(o)
nQx
Qx
nQy
Qy
V
CMR
Cross Points
V
PP
V
CC
V
EE
CLK0,
CLK1
nCLK0,
nCLK1
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
P
ROPAGATION
D
ELAY
P
HASE
J
ITTER
& S
TATIC
P
HASE
O
FFSET
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0:Q4
nQ0:nQ4
t
PD
CLK0,
CLK1
nCLK0,
nCLK1
Q0:Q4
nQ0:nQ4
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
Q0:Q4
nQ0:nQ4
(where
t
() is any random sample, and
t
()
mean
is the average
of the sampled cycles measured on controlled edges)
t
()
mean
= Static Phase Offset
t()
V
OH
V
OL
V
OH
V
OL
nCLK0,
nCLK1
nFB_IN
FB_IN
t
jit() =
t
() --
t
()
mean
= Phase Jitter
CLK0,
CLK1
V
CC
,
V
CCA
,
V
CCO
V
EE
8735AY-01
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REV. F NOVEMBER 12, 2004
7
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
A
PPLICATION
I
NFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VCC
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 1A and 1B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
F
IGURE
1B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
1A. LVPECL O
UTPUT
T
ERMINATION
T
ERMINATION
FOR
LVPECL O
UTPUTS
8735AY-01
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REV. F NOVEMBER 12, 2004
8
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 3A to 3D show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
3A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
8735AY-01
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REV. F NOVEMBER 12, 2004
9
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
The schematic of the ICS8735-01 layout example is shown in
Figure 5A. The ICS8735-01 recommended PCB board layout
for this example is shown in
Figure 5B. This layout example is
used as a general guideline. The layout in the actual system will
depend on the selected component types, the density of the
components, the density of the traces, and the stack up of the
P.C. board.
F
IGURE
5A. ICS8735-01 LVPECL Z
ERO
D
ELAY
B
UFFER
S
CHEMATIC
E
XAMPLE
L
AYOUT
G
UIDELINE
VCCO=3.3V
Bypass capacitor located near the power pins
R9
50
SEL0
VCC
RU6
1K
VCCO
CLK_SEL
C5
0.1uF
RD4
SP
3.3V
PL
L
_
SEL
RD6
SP
(155.52 MHz)
Zo = 50 Ohm
R6
50
3.3V PECL Driver
LVPECL_input
+
-
R2
50
Zo = 50 Ohm
VCC=3.3V
R7
10
C7
0.1uF
SEL0
C2
0.1uF
C11
0.01u
Zo = 50 Ohm
SEL
3
(U1-9)
(U1-32)
VCC
RD2
1K
(U1-16)
C6
0.1uF
RD5
1K
R3
50
SEL1
RU5
SP
(77.76 MHz)
SEL[3:0] = 0101,
Divide by 2
RU4
1K
Output
Termination
Example
C16
10u
CLK_SEL
RD3
SP
RD7
1K
SP = Space (i.e. not intstalled)
VCC
U1
8735-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
VC
C
nF
B
_
IN
FB
_
I
N
SEL
2
VEE
nQ0
Q0
V
CCO
VCCO
nQ1
Q1
nQ2
Q2
nQ3
Q3
VCCO
VC
C
PL
L
_
SEL
V
CCA
SEL
3
VEE
Q4
nQ4
V
CCO
VCCO
RU7
SP
(U1-24)
VCCA
RU3
1K
R10
50
(U1-17)
RU2
SP
PLL_SEL
R5
50
C1
0.1uF
(U1-25)
SEL2
SEL3
C4
0.1uF
VCC
R1
50
SEL2
R8
50
SEL1
R4
50
Zo = 50 Ohm
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8735-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 4 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
4. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
10
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C1, C6, C2, C4, C5, and C7,
as close as possible to the power pins. If space allows, place-
ment of the decoupling capacitor on the component side is
preferred. This can reduce unwanted inductance between the
decoupling capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital sys-
tems, the clock signal is less tolerant to poor signal integrity
than other signals. Any ringing on the rising or falling edge
or excessive ring back can cause system failure. The shape
of the trace and the trace delay might be restricted by the
available space on the board and the component location.
While routing the traces, the clock signal traces should be routed
first and should be locked prior to routing other signal traces.
The differential 50
output traces should have same
length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
F
IGURE
5B. PCB B
OARD
L
AYOUT
F
OR
ICS8735-01
GND
C7
C16
VCCA
VIA
U1
VCC
C4
50 Ohm
Traces
C1
C6
VCCO
R7
C5
C2
Pin 1
C11
8735AY-01
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REV. F NOVEMBER 12, 2004
11
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8735-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8735-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 150mA = 520mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power
_MAX
(3.465V, with all outputs switching) = 520mW + 151mW = 671mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.671W * 42.1C/W = 98C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7A. T
HERMAL
R
ESISTANCE


JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
T
ABLE
7B.


JA
VS
. A
IR
F
LOW
T
ABLE
F
OR
32 L
EAD
VFQFN P
ACKAGE


JA
0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8C/W
8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
12
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
1.0V
(V
CCO_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
13
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8735-01 is: 2969
T
ABLE
8A.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP P
ACKAGE


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
8B.
JA
VS
. A
IR
F
LOW
T
ABLE
F
OR
32 L
EAD
VFQFN P
ACKAGE


JA
0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8C/W
8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
14
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
9A. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0




0
-
-
7
c
c
c
-
-
-
-
0
1
.
0
8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
15
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
P
ACKAGE
O
UTLINE
- K S
UFFIX
FOR
32 L
EAD
VFQFN
T
ABLE
9B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-220
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
M
U
M
I
N
I
M
M
U
M
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8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
16
Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 D
IFFERENTIAL
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TO
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10. O
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While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
17
Integrated
Circuit
Systems, Inc.
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1:5 D
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