8725AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 20, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS8725-01 is a highly versatile 1:5 Differ-
ential-to-LVHSTL clock generator and a member
of the HiPerClockSTM family of High Performance
Clock Solutions from ICS. The ICS8725-01 has
a fully integrated PLL and can be configured as
zero delay buffer, multiplier or divider, and has an output fre-
quency range of 31.25MHz to 700MHz. The reference divider,
feedback divider and output divider are each programmable,
thereby allowing for the following output-to-input frequency
ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback
allows the device to achieve "zero delay" between the input
clock and the output clocks. The PLL_SEL pin can be used
to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
5 differential LVHSTL outputs
Selectable differential CLKx, nCLKx input pairs
CLKx, nCLKx pairs can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Output frequency range: 31.25MHz - 700MHz
Input frequency range: 31.25MHz - 700MHz
VCO range: 250MHz - 700MHz
External feedback for "zero delay" clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Static phase offset: 100ps
Cycle-to-cycle jitter: 25ps
Output skew: 25ps
3.3V core, 1.8V output operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
DDO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
DDO
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
V
DDO
Q0
nQ0
GND
SEL2
FB_IN
nFB_IN
V
DD
V
DDO
nQ4
Q4
GND
SEL3
V
DDA
PLL_SEL
V
DD
ICS8725-01
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
1
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
0
1
1, 2, 4, 8,
16, 32
,
64
8725AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 20, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
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8725AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 20, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
3A. C
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1
1
2
1
1
0
0
4
1
1
0
1
1
1
1
1
0
2
1
1
1
1
1
8725AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 20, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to V
DD
+0.5 V
Outputs, V
O
-0.5V to V
DDO
+0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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D
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T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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x
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5
6
4
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D
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=
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L
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x
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5
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D
D
.
8725AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 20, 2001
5
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
4D. LVHSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
l
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F
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C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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z
H
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T
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6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
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:
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T
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M
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6
f
o
y
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:
6
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T
O
N
8725AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 20, 2001
6
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
F
IGURE
1 - O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
LVHSTL
Qx
nQx
V
DD
, V
DDA
= 3.3V 5%
V
DDO
= 1.8V 0.2V
V
DDO
V
DD
, V
DDA
GND = 0V
F
IGURE
2 - D
IFFERENTIAL
I
NPUT
L
EVEL
V
CMR
Cross Points
V
PP
nCLK0, nCLK1
CLK0, CLK1
GND
V
DD
8725AY-01
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REV. A NOVEMBER 20, 2001
7
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
IGURE
5 - P
HASE
J
ITTER
AND
S
TATIC
P
HASE
O
FFSET
(where
t() is any random sample, and t()
mean
is the average
of the sampled cycles measured on controlled edges)
t()
mean
= Static Phase Offset
tjit() = t() -- t()
mean
= Phase Jitter
t()
V
OH
V
ref
V
OL
V
OH
V
ref
V
OL
CLK0, CLK1
nCLK0, nCLK1
FB_IN
nFB_IN
Q0 - Q4
F
IGURE
4 - Cycle-to-Cycle Jitter
nQ0 - nQ4
t
jit(cc) =
t
cycle n
t
cycle n+1
t
cycle n
t
cycle n+1
F
IGURE
3 - O
UTPUT
S
KEW
tsk(o)
nQx
Qx
nQy
Qy
8725AY-01
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REV. A NOVEMBER 20, 2001
8
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
IGURE
8 - odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
F
IGURE
7 - P
ROPAGATION
D
ELAY
t
PD
F
IGURE
6 - I
NPUT
AND
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Inputs
and Outputs
20%
80%
80%
20%
t
R
t
F
V
S W I N G
nCLK0, nCLK1
CLK0, CLK1
nQ0 - nQ4
Q0 - Q4
nQ0 - nQ4
Q0 - Q4
8725AY-01
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REV. A NOVEMBER 20, 2001
9
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
A
PPLICATION
I
NFORMATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 9 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
F
IGURE
9 - S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R2
1K
V
DD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
8725AY-01
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REV. A NOVEMBER 20, 2001
10
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
IGURE
10 - ICS8725-01 LVHSTL Z
ERO
D
ELAY
B
UFFER
S
CHEMATIC
E
XAMPLE
L
AYOUT
G
UIDELINE
The schematic of the ICS8725-01 layout example is shown in
Figure 10. The ICS8725-01 recommended PCB board layout for this
example is shown in
Figure 11. This layout example is used as a general guideline. The layout in the actual system will depend on the
selected component types, the density of the components, the density of the traces, and the stacking of the P.C. board.
C6
0.1uF
VDDA
SEL0
SEL[3:0] = 0101,
Divide by 2
SEL1
(U1-32)
(U1-25)
VDDO
VDDO
3.3V
3.3V PECL Driver
RD4
SP
RU3
1K
C11
0.01u
C4
0.1uF
VDD
RU7
SP
C2
0.1uF
C7
0.1uF
SP = Space (i.e. not intstalled)
R2A
50
C1
0.1uF
RD5
1K
PL
L
_
SEL
CLK_SEL
C16
10u
R2B
50
VDD=3.3V
VDD
R7
10
PLL_SEL
SEL1
U1
8725_01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
VDD
nFB
_
I
N
FB_I
N
SEL
2
GND
nQ
0
Q0
VDDO
VDDO
nQ1
Q1
nQ2
Q2
nQ3
Q3
VDDO
VDD
PL
L
_
SEL
VDDA
SEL
3
GND
Q4
nQ
4
VDDO
RD7
1K
R4B
50
C5
0.1uF
(U1-17)
R8
50
Zo = 50 Ohm
Zo = 50 Ohm
RU6
1K
(155.5 MHz)
SEL3
RU5
SP
RD2
1K
SEL2
RD6
SP
Zo = 50 Ohm
R4A
50
RU2
SP
SEL
3
VDD
SEL2
SEL0
VDD
Zo = 50 Ohm
(155.5 MHz)
(U1-16)
RU4
1K
VDDO=1.8V
(U1-9)
LVHSTL_input
+
-
R9
50
RD3
SP
Bypass capacitors located near the power pins
R10
50
CLK_SEL
(U1-24)
8725AY-01
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REV. A NOVEMBER 20, 2001
11
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
IGURE
11 - PCB B
OARD
L
AYOUT
F
OR
ICS8725-01
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C1, C6, C2, C4, and C5, as
close as possible to the power pins. If space allows, placement
of the decoupling capacitor on the component side is preferred.
This can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
DDA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have same
length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a spearation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C1
C2
C16
R7
GND
C5
VDD
U1
VDDA
C4
50 Ohm
Traces
C11
VIA
VDDO
Pin 1
C7
C6
8725AY-01
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REV. A NOVEMBER 20, 2001
12
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8725-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8725-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* (I
DD_MAX
+ I
DDA_MAX
) = 3.465V * (120mA + 15mA) = 468mW
Power (outputs)
MAX
= 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 32.8mW = 164mW
Total Power
_MAX
(3.465V, with all outputs switching) = 468mW + 164mW = 632mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.632W * 42.1C/W = 96.6C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 7. Thermal Resistance
q
JA
for 32-pin LQFP, Forced Convection
8725AY-01
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REV. A NOVEMBER 20, 2001
13
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in
Figure 12.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R
L
) * (V
DD_MAX
- V
OH_MIN
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DD_MAX
- V
OL_MAX
)
Pd_H = (1V/50
) * (2V - 1V) = 20mW
Pd_L = (0.4V/50
) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
F
IGURE
12 - LVHSTL D
RIVER
C
IRCUIT
AND
T
ERMINATION
V
DD
V
OUT
RL
50
Q1
8725AY-01
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REV. A NOVEMBER 20, 2001
14
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8725-01 is: 2969
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8725AY-01
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REV. A NOVEMBER 20, 2001
15
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
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8725AY-01
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REV. A NOVEMBER 20, 2001
16
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
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8725AY-01
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REV. A NOVEMBER 20, 2001
17
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 D
IFFERENTIAL
-
TO
-LVHSTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
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