ChipFind - документация

Электронный компонент: ICS87016

Скачать:  PDF   ZIP

Document Outline

Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
1
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87016 is a low skew, 1:16 LVCMOS/
LVTTL Clock Generator and is a member of the
HiPerClockS family of High Performance Clock
Solutions. The device has 4 banks of 4 outputs
and each bank can be independently selected for
1 or
2 frequency operation. Each bank also has its own power
supply pins so that the banks can operate at the following dif-
ferent voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50
series or
parallel terminated transmission lines.
The divide select inputs, DIV_SELA:DIV_SELD, control the
output frequency of each bank. The output banks can be
independently selected for
1 or
2 operation. The bank enable
inputs, CLK_ENA:CLK_END, support enabling and disabling
each bank of outputs individually. The CLK_ENA:CLK_END
circuitry has a synchronizer to prevent runt pulses when
enabling or disabling the clock outputs. The master reset
input, nMR/OE, resets the
1/
2 flip flops and also controls the
active and high impedance states of all outputs. This pin has
an internal pull-up resistor and is normally used only for test
purposes or in systems which use low power modes.
The ICS87016 is characterized to operate with the core at 3.3V
and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output,
and part-to-part skew characteristics make the 87016 ideal for
those clock applications demanding well-defined performance
and repeatability.
F
EATURES
16 LVCMOS/LVTTL outputs (4 banks of 4 outputs)
Selectable differential CLK1, nCLK1 or LVCMOS clock input
CLK1, nCLK1 pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK0 supports the following input types: LVCMOS, LVTTL
Maximum output frequency: 250MHz
Independent bank control for
1 or
2 operation
Independent output bank voltage settings for 3.3V, 2.5V,
or 1.8V operation
Asynchronous clock enable/disable
Output skew: 170ps (maximum)
Bank skew: 30ps (maximum)
Part-to-part skew: 750ps (maximum)
3.3V core, 3.3V, 2.5V, or 1.8V output operating supply
0C to 85C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
,&6
48-Pin LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
GND
QC2
V
DDOC
QC3
GND
QD0
V
DDOD
QD1
GND
QD2
V
DDOD
QD3
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
V
DD
CLK0
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
nMR/OE
GND
GND
QB0
V
DDOB
QB1
GND
QB2
V
DDOB
QB3
GND
QC0
V
DDOC
QC1
QA3
V
DDOA
QA2
GND
QA1
V
DDOA
QA0
GND
CLK_SEL
nCLK1
CLK1
V
DD
ICS87016
nMR/OE
CLK0
CLK1
nCLK1
CLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
QA0:QA3
QB0:QB3
QC0:QC3
QD0:QD3
0
1
1
0
1
0
1
0
1
0
1
2
4
4
4
4
LE
LE
LE
LE
D
D
D
D
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
2
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
r
e
b
m
u
N
e
m
a
N
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
8
4
,
1
V
D
D
r
e
w
o
P
.
s
n
i
p
y
l
p
p
u
s
e
r
o
C
2
0
K
L
C
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
L
T
T
V
L
/
S
O
M
C
V
L
3
A
L
E
S
_
V
I
D
t
u
p
n
I
p
u
ll
u
P
.
s
t
u
p
t
u
o
A
k
n
a
B
r
o
f
n
o
i
s
i
v
i
d
y
c
n
e
u
q
e
r
f
s
l
o
r
t
n
o
C
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
4
B
L
E
S
_
V
I
D
t
u
p
n
I
p
u
ll
u
P
s
t
u
p
t
u
o
B
k
n
a
B
r
o
f
n
o
i
s
i
v
i
d
y
c
n
e
u
q
e
r
f
s
l
o
r
t
n
o
C
.
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
5
C
L
E
S
_
V
I
D
t
u
p
n
I
p
u
ll
u
P
.
s
t
u
p
t
u
o
C
k
n
a
B
r
o
f
n
o
i
s
i
v
i
d
y
c
n
e
u
q
e
r
f
s
l
o
r
t
n
o
C
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
6
D
L
E
S
_
V
I
D
t
u
p
n
I
p
u
ll
u
P
.
s
t
u
p
t
u
o
D
k
n
a
B
r
o
f
n
o
i
s
i
v
i
d
y
c
n
e
u
q
e
r
f
s
l
o
r
t
n
o
C
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
7
A
N
E
_
K
L
C
t
u
p
n
I
p
u
ll
u
P
.
H
G
I
H
e
v
i
t
c
A
.
s
t
u
p
t
u
o
A
k
n
a
B
r
o
f
e
l
b
a
n
e
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
w
o
l
e
v
i
r
d
s
t
u
p
t
u
o
,
W
O
L
s
i
n
i
p
f
I
8
B
N
E
_
K
L
C
t
u
p
n
I
p
u
ll
u
P
.
H
G
I
H
e
v
i
t
c
A
.
s
t
u
p
t
u
o
B
k
n
a
B
r
o
f
e
l
b
a
n
e
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
w
o
l
e
v
i
r
d
s
t
u
p
t
u
o
,
W
O
L
s
i
n
i
p
f
I
9
C
N
E
_
K
L
C
t
u
p
n
I
p
u
ll
u
P
.
H
G
I
H
e
v
i
t
c
A
.
s
t
u
p
t
u
o
C
k
n
a
B
r
o
f
e
l
b
a
n
e
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
w
o
l
e
v
i
r
d
s
t
u
p
t
u
o
,
W
O
L
s
i
n
i
p
f
I
0
1
D
N
E
_
K
L
C
t
u
p
n
I
p
u
ll
u
P
.
H
G
I
H
e
v
i
t
c
A
.
s
t
u
p
t
u
o
D
k
n
a
B
r
o
f
e
l
b
a
n
e
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
w
o
l
e
v
i
r
d
s
t
u
p
t
u
o
,
W
O
L
s
i
n
i
p
f
I
1
1
E
O
/
R
M
n
t
u
p
n
I
p
u
ll
u
P
e
h
t
s
t
e
s
d
n
a
s
p
o
l
f
p
il
f
2
/
1
e
h
t
s
t
e
s
e
r
,
W
O
L
n
e
h
W
.
t
e
s
e
r
r
e
t
s
a
M
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
e
c
n
a
d
e
p
m
i
h
g
i
h
o
t
s
t
u
p
t
u
o
,
4
2
,
0
2
,
6
1
,
2
1
4
4
,
0
4
,
6
3
,
2
3
,
8
2
D
N
G
r
e
w
o
P
.
d
n
u
o
r
g
y
l
p
p
u
S
9
1
,
7
1
,
5
1
,
3
1
,
2
D
Q
,
3
D
Q
0
D
Q
,
1
D
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
s
t
u
p
t
u
o
D
k
n
a
B
8
1
,
4
1
V
D
O
D
D
r
e
w
o
P
.
s
n
i
p
y
l
p
p
u
s
D
k
n
a
B
t
u
p
t
u
O
7
2
,
5
2
,
3
2
,
1
2
,
2
C
Q
,
3
C
Q
0
C
Q
,
1
C
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
s
t
u
p
t
u
o
C
k
n
a
B
6
2
,
2
2
V
C
O
D
D
r
e
w
o
P
.
s
n
i
p
y
l
p
p
u
s
C
k
n
a
B
t
u
p
t
u
O
5
3
,
3
3
,
1
3
,
9
2
,
2
B
Q
,
3
B
Q
0
B
Q
,
1
B
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
s
t
u
p
t
u
o
B
k
n
a
B
4
3
,
0
3
V
B
O
D
D
r
e
w
o
P
.
s
n
i
p
y
l
p
p
u
s
B
k
n
a
B
t
u
p
t
u
O
3
4
,
1
4
,
9
3
,
7
3
,
2
A
Q
,
3
A
Q
0
A
Q
,
1
A
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
s
t
u
p
t
u
o
A
k
n
a
B
2
4
,
8
3
V
A
O
D
D
r
e
w
o
P
.
s
n
i
p
y
l
p
p
u
s
A
k
n
a
B
t
u
p
t
u
O
5
4
L
E
S
_
K
L
C
t
u
p
n
I
n
w
o
d
ll
u
P
.
s
t
u
p
n
i
1
K
L
C
n
,
1
K
L
C
s
t
c
e
l
e
s
,
H
G
I
H
n
e
h
W
.
t
u
p
n
i
t
c
e
l
e
s
k
c
o
l
C
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
t
u
p
n
i
0
K
L
C
s
t
c
e
l
e
s
,
W
O
L
n
e
h
W
6
4
1
K
L
C
n
t
u
p
n
I
p
u
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
l
a
i
t
n
e
r
e
f
f
i
d
g
n
i
t
r
e
v
n
I
7
4
1
K
L
C
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
l
a
i
t
n
e
r
e
f
f
i
d
g
n
i
t
r
e
v
n
i
-
n
o
N
:
E
T
O
N
p
u
ll
u
P
d
n
a
n
w
o
d
ll
u
P
.
s
e
u
l
a
v
l
a
c
i
p
y
t
r
o
f
,
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
n
i
P
,
2
e
l
b
a
T
e
e
S
.
s
r
o
t
s
i
s
e
r
t
u
p
n
i
l
a
n
r
e
t
n
i
o
t
r
e
f
e
r
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
3
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
2. P
IN
C
HARACTERISTICS
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
ti
n
U
C
N
I
e
c
n
a
t
i
c
a
p
a
C
t
u
p
n
I
4
F
p
R
P
U
L
L
U
P
r
o
t
s
i
s
e
R
p
u
ll
u
P
t
u
p
n
I
1
5
K
C
D
P
e
c
n
a
t
i
c
a
p
a
C
n
o
i
t
a
p
i
s
s
i
D
r
e
w
o
P
)
t
u
p
t
u
o
r
e
p
(
V
D
D
V
,
x
O
D
D
1
E
T
O
N
;
V
5
6
4
.
3
=
8
1
F
p
V
D
D
V
,
5
6
4
.
3
=
x
O
D
D
1
E
T
O
N
;
V
5
2
6
.
2
=
0
2
F
p
V
D
D
V
,
5
6
4
.
3
=
x
O
D
D
1
E
T
O
N
;
V
9
8
.
1
=
0
3
F
p
R
T
U
O
e
c
n
a
d
e
p
m
I
t
u
p
t
u
O
7
V
:
1
E
T
O
N
x
O
D
D
V
s
e
t
o
n
e
d
A
O
D
D
V
,
B
O
D
D
V
,
C
O
D
D
V
d
n
a
,
D
O
D
D
.
T
ABLE
3. F
UNCTION
T
ABLE
s
t
u
p
n
I
s
t
u
p
t
u
O
E
O
/
R
M
n
x
N
E
_
K
L
C
x
L
E
S
_
V
I
D
X
k
n
a
B
y
c
n
e
u
q
e
r
F
x
Q
0
X
X
Z
i
H
A
/
N
1
1
0
e
v
i
t
c
A
2
/
N
I
f
1
1
1
e
v
i
t
c
A
N
I
f
1
0
X
w
o
L
A
/
N
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
4
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
x
O
D
D
1
E
T
O
N
;
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
3
1
.
3
3
.
3
5
6
4
.
3
V
5
7
3
.
2
5
.
2
5
2
6
.
2
V
1
7
.
1
8
.
1
9
8
.
1
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
0
0
1
A
m
I
x
O
D
D
2
E
T
O
N
;
t
n
e
r
r
u
C
y
l
p
p
u
S
t
u
p
t
u
O
5
1
A
m
V
:
1
E
T
O
N
x
O
D
D
V
s
e
t
o
n
e
d
A
O
D
D
V
,
B
O
D
D
V
,
C
O
D
D
V
d
n
a
,
D
O
D
D
I
:
2
E
T
O
N
.
x
O
D
D
I
s
e
t
o
n
e
d
A
O
D
D
I
,
B
O
D
D
I
,
C
O
D
D
I
d
n
a
,
D
O
D
D
.
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
t
u
p
n
I
e
g
a
t
l
o
V
h
g
i
H
,
D
L
E
S
_
V
I
D
:
A
L
E
S
_
V
I
D
,
D
N
E
_
K
L
C
:
A
N
E
_
K
L
C
L
E
S
_
K
L
C
,
E
O
/
R
M
n
2
V
D
D
3
.
0
+
V
0
K
L
C
2
V
D
D
3
.
0
+
V
V
L
I
t
u
p
n
I
e
g
a
t
l
o
V
w
o
L
,
D
L
E
S
_
V
I
D
:
A
L
E
S
_
V
I
D
,
D
N
E
_
K
L
C
:
A
N
E
_
K
L
C
L
E
S
_
K
L
C
,
E
O
/
R
M
n
3
.
0
-
8
.
0
V
0
K
L
C
3
.
0
-
3
.
1
V
I
H
I
t
u
p
n
I
t
n
e
r
r
u
C
h
g
i
H
,
D
N
E
_
K
L
C
:
A
N
E
_
K
L
C
,
D
L
E
S
_
V
I
D
:
A
L
E
S
_
V
I
D
E
O
/
R
M
n
V
D
D
V
=
N
I
V
5
6
4
.
3
=
5
A
L
E
S
_
K
L
C
,
0
K
L
C
V
D
D
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
I
L
I
t
u
p
n
I
t
n
e
r
r
u
C
w
o
L
,
D
N
E
_
K
L
C
:
A
N
E
_
K
L
C
,
D
L
E
S
_
V
I
D
:
A
L
E
S
_
V
I
D
E
O
/
R
M
n
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
L
E
S
_
K
L
C
,
0
K
L
C
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
V
H
O
1
E
T
O
N
;
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
V
x
O
D
D
2
E
T
O
N
;
%
5
V
3
.
3
=
6
.
2
V
V
x
O
D
D
2
E
T
O
N
;
%
5
V
5
.
2
=
8
.
1
V
V
x
O
D
D
2
E
T
O
N
;
%
5
V
8
.
1
=
I
H
O
A
m
2
-
=
V
D
D
5
4
.
0
-
V
V
L
O
1
E
T
O
N
;
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
V
x
O
D
D
2
E
T
O
N
;
%
5
V
3
.
3
=
5
.
0
V
V
x
O
D
D
2
E
T
O
N
;
%
5
V
5
.
2
=
5
.
0
V
V
x
O
D
D
2
E
T
O
N
;
%
5
V
8
.
1
=
I
L
O
A
m
2
=
5
4
.
0
V
I
L
Z
O
w
o
L
t
n
e
r
r
u
C
e
t
a
t
s
i
r
T
t
u
p
t
u
O
5
-
A
I
H
Z
O
h
g
i
H
t
n
e
r
r
u
C
e
t
a
t
s
i
r
T
t
u
p
t
u
O
5
A
0
5
h
t
i
w
d
e
t
a
n
i
m
r
e
t
s
t
u
p
t
u
O
:
1
E
T
O
N
V
o
t
X
O
D
D
.
t
i
u
c
r
i
C
t
s
e
T
d
a
o
L
t
u
p
t
u
O
,
n
o
i
t
a
m
r
o
f
n
I
t
n
e
m
e
r
u
s
a
e
M
r
e
t
e
m
a
r
a
P
e
e
S
.
2
/
V
:
2
E
T
O
N
x
O
D
D
V
s
e
t
o
n
e
d
A
O
D
D
V
,
,
B
O
D
D
V
C
O
D
D
V
d
n
a
D
O
D
D
.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
5
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
I
H
I
t
n
e
r
r
u
C
h
g
i
H
t
u
p
n
I
1
K
L
C
n
V
N
I
V
=
D
D
V
5
6
4
.
3
=
5
A
1
K
L
C
V
N
I
V
=
D
D
V
5
6
4
.
3
=
0
5
1
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
1
K
L
C
n
V
N
I
V
,
V
0
=
D
D
V
5
6
4
.
3
=
0
5
1
-
A
1
K
L
C
V
N
I
V
,
V
0
=
D
D
V
5
6
4
.
3
=
5
-
A
V
P
P
e
g
a
t
l
o
V
t
u
p
n
I
k
a
e
P
-
o
t
-
k
a
e
P
5
1
.
0
3
.
1
V
V
R
M
C
;
e
g
a
t
l
o
V
t
u
p
n
I
e
d
o
M
n
o
m
m
o
C
2
,
1
E
T
O
N
5
.
0
+
D
N
G
V
D
D
5
8
.
0
-
V
s
n
o
i
t
a
c
il
p
p
a
d
e
d
n
e
e
l
g
n
i
s
r
o
F
:
1
E
T
O
N
,
V
s
i
1
K
L
C
n
,
1
K
L
C
r
o
f
e
g
a
t
l
o
v
t
u
p
n
i
m
u
m
i
x
a
m
e
h
t
D
D
.
V
3
.
0
+
V
s
a
d
e
n
i
f
e
d
s
i
e
g
a
t
l
o
v
e
d
o
m
n
o
m
m
o
C
:
2
E
T
O
N
H
I
.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
X
= 3.3V5%, T
A
= 0C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
X
A
M
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
0
5
2
z
H
M
p
t
H
L
,
y
a
l
e
D
n
o
i
t
a
g
a
p
o
r
P
h
g
i
H
o
t
w
o
L
A
1
E
T
O
N
;
0
K
L
C
8
.
2
2
.
3
7
.
3
s
n
;
1
K
L
C
n
,
1
K
L
C
B
1
E
T
O
N
9
.
2
4
.
3
9
.
3
s
n
t
)
b
(
k
s
7
,
2
E
T
O
N
;
w
e
k
S
k
n
a
B
e
g
d
E
g
n
i
s
i
R
e
h
t
n
o
d
e
r
u
s
a
e
M
0
3
s
p
t
)
o
(
k
s
7
,
3
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
e
g
d
E
g
n
i
s
i
R
e
h
t
n
o
d
e
r
u
s
a
e
M
0
5
1
s
p
t
)
p
p
(
k
s
7
,
5
E
T
O
N
;
w
e
k
S
t
r
a
P
-
o
t
-
t
r
a
P
0
5
7
s
p
t
R
t
/
F
6
E
T
O
N
;
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
0
2
0
0
7
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
z
H
M
5
7
1
<
f
5
4
5
5
%
f
z
H
M
5
7
1
0
4
0
6
%
t
N
E
6
E
T
O
N
;
e
m
i
T
e
l
b
a
n
E
t
u
p
t
u
O
0
1
s
n
t
S
I
D
6
E
T
O
N
;
e
m
i
T
e
l
b
a
s
i
D
t
u
p
t
u
O
0
1
s
n
.
e
s
i
w
r
e
h
t
o
d
e
t
o
n
s
s
e
l
n
u
z
H
M
0
5
2
t
a
d
e
r
u
s
a
e
m
s
r
e
t
e
m
a
r
a
p
ll
A
V
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
A
1
E
T
O
N
D
D
V
o
t
t
u
p
n
i
e
h
t
f
o
2
/
X
O
D
D
.
t
u
p
t
u
o
e
h
t
f
o
2
/
V
o
t
t
n
i
o
p
g
n
i
s
s
o
r
c
t
u
p
n
i
l
a
i
t
n
e
r
e
f
f
i
d
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
B
1
E
T
O
N
X
O
D
D
.
t
u
p
t
u
o
e
h
t
f
o
2
/
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
k
n
a
b
a
n
i
h
t
i
w
w
e
k
s
s
a
d
e
n
i
f
e
D
:
2
E
T
O
N
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
3
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
X
O
D
D
.
2
/
s
e
i
c
n
e
u
q
e
r
f
t
n
e
r
e
f
f
i
d
t
a
g
n
i
t
a
r
e
p
o
n
o
i
t
c
e
r
i
d
e
m
a
s
e
h
t
n
i
g
n
i
h
c
t
i
w
s
s
t
u
p
t
u
o
f
o
s
k
n
a
b
s
s
o
r
c
a
w
e
k
s
s
a
d
e
n
i
f
e
D
:
4
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
h
t
i
w
X
O
D
D
.
2
/
l
a
u
q
e
h
t
i
w
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
a
g
n
i
t
a
r
e
p
o
s
e
c
i
v
e
d
t
n
e
r
e
f
f
i
d
n
o
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
5
E
T
O
N
V
t
a
d
e
r
u
s
a
e
m
s
i
t
u
p
t
u
o
e
h
t
,
e
c
i
v
e
d
h
c
a
e
n
o
t
u
p
n
i
f
o
e
p
y
t
e
m
a
s
e
h
t
g
n
i
s
U
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
X
O
D
D
.
2
/
.
n
o
i
t
c
u
d
o
r
p
n
i
d
e
t
s
e
t
t
o
N
.
n
o
i
t
a
z
i
r
e
t
c
a
r
a
h
c
y
b
d
e
e
t
n
a
r
a
u
g
e
r
a
s
r
e
t
e
m
a
r
a
p
e
s
e
h
T
:
6
E
T
O
N
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
7
E
T
O
N
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
6
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
X
= 2.5V5%, T
A
= 0C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
X
A
M
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
0
5
2
z
H
M
p
t
H
L
,
y
a
l
e
D
n
o
i
t
a
g
a
p
o
r
P
h
g
i
H
o
t
w
o
L
A
1
E
T
O
N
;
0
K
L
C
9
.
2
3
.
3
8
.
3
s
n
;
1
K
L
C
n
,
1
K
L
C
B
1
E
T
O
N
3
5
.
3
4
s
n
t
)
b
(
k
s
7
,
2
E
T
O
N
;
w
e
k
S
k
n
a
B
e
g
d
E
g
n
i
s
i
R
e
h
t
n
o
d
e
r
u
s
a
e
M
0
3
s
p
t
)
o
(
k
s
7
,
3
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
e
g
d
E
g
n
i
s
i
R
e
h
t
n
o
d
e
r
u
s
a
e
M
0
6
1
s
p
t
)
p
p
(
k
s
7
,
5
E
T
O
N
;
w
e
k
S
t
r
a
P
-
o
t
-
t
r
a
P
0
5
7
s
p
t
R
t
/
F
6
E
T
O
N
;
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
0
2
0
0
7
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
z
H
M
5
7
1
<
f
5
4
5
5
%
f
z
H
M
5
7
1
0
4
0
6
%
t
N
E
6
E
T
O
N
;
e
m
i
T
e
l
b
a
n
E
t
u
p
t
u
O
0
1
s
n
t
S
I
D
6
E
T
O
N
;
e
m
i
T
e
l
b
a
s
i
D
t
u
p
t
u
O
0
1
s
n
.
e
s
i
w
r
e
h
t
o
d
e
t
o
n
s
s
e
l
n
u
z
H
M
0
5
2
t
a
d
e
r
u
s
a
e
m
s
r
e
t
e
m
a
r
a
p
ll
A
V
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
A
1
E
T
O
N
D
D
V
o
t
t
u
p
n
i
e
h
t
f
o
2
/
X
O
D
D
.
t
u
p
t
u
o
e
h
t
f
o
2
/
V
o
t
t
n
i
o
p
g
n
i
s
s
o
r
c
t
u
p
n
i
l
a
i
t
n
e
r
e
f
f
i
d
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
B
1
E
T
O
N
X
O
D
D
.
t
u
p
t
u
o
e
h
t
f
o
2
/
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
k
n
a
b
a
n
i
h
t
i
w
w
e
k
s
s
a
d
e
n
i
f
e
D
:
2
E
T
O
N
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
3
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
X
O
D
D
.
2
/
s
e
i
c
n
e
u
q
e
r
f
t
n
e
r
e
f
f
i
d
t
a
g
n
i
t
a
r
e
p
o
n
o
i
t
c
e
r
i
d
e
m
a
s
e
h
t
n
i
g
n
i
h
c
t
i
w
s
s
t
u
p
t
u
o
f
o
s
k
n
a
b
s
s
o
r
c
a
w
e
k
s
s
a
d
e
n
i
f
e
D
:
4
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
h
t
i
w
X
O
D
D
.
2
/
l
a
u
q
e
h
t
i
w
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
a
g
n
i
t
a
r
e
p
o
s
e
c
i
v
e
d
t
n
e
r
e
f
f
i
d
n
o
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
5
E
T
O
N
V
t
a
d
e
r
u
s
a
e
m
s
i
t
u
p
t
u
o
e
h
t
,
e
c
i
v
e
d
h
c
a
e
n
o
t
u
p
n
i
f
o
e
p
y
t
e
m
a
s
e
h
t
g
n
i
s
U
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
X
O
D
D
.
2
/
.
n
o
i
t
c
u
d
o
r
p
n
i
d
e
t
s
e
t
t
o
N
.
n
o
i
t
a
z
i
r
e
t
c
a
r
a
h
c
y
b
d
e
e
t
n
a
r
a
u
g
e
r
a
s
r
e
t
e
m
a
r
a
p
e
s
e
h
T
:
6
E
T
O
N
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
7
E
T
O
N
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
7
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
X
= 1.8V5%, T
A
= 0C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
X
A
M
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
0
5
2
z
H
M
p
t
H
L
,
y
a
l
e
D
n
o
i
t
a
g
a
p
o
r
P
h
g
i
H
o
t
w
o
L
A
1
E
T
O
N
;
0
K
L
C
1
.
3
8
.
3
5
.
4
s
n
;
1
K
L
C
n
,
1
K
L
C
B
1
E
T
O
N
1
.
3
8
.
3
5
.
4
s
n
t
)
b
(
k
s
7
,
2
E
T
O
N
;
w
e
k
S
k
n
a
B
e
g
d
E
g
n
i
s
i
R
e
h
t
n
o
d
e
r
u
s
a
e
M
0
3
s
p
t
)
o
(
k
s
7
,
3
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
e
g
d
E
g
n
i
s
i
R
e
h
t
n
o
d
e
r
u
s
a
e
M
0
7
1
s
p
t
)
p
p
(
k
s
7
,
5
E
T
O
N
;
w
e
k
S
t
r
a
P
-
o
t
-
t
r
a
P
0
5
7
s
p
t
R
t
/
F
6
E
T
O
N
;
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
0
2
0
0
7
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
z
H
M
5
7
1
<
f
5
4
5
5
%
f
z
H
M
5
7
1
0
4
0
6
%
t
N
E
6
E
T
O
N
;
e
m
i
T
e
l
b
a
n
E
t
u
p
t
u
O
0
1
s
n
t
S
I
D
6
E
T
O
N
;
e
m
i
T
e
l
b
a
s
i
D
t
u
p
t
u
O
0
1
s
n
.
e
s
i
w
r
e
h
t
o
d
e
t
o
n
s
s
e
l
n
u
z
H
M
0
5
2
t
a
d
e
r
u
s
a
e
m
s
r
e
t
e
m
a
r
a
p
ll
A
V
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
A
1
E
T
O
N
D
D
V
o
t
t
u
p
n
i
e
h
t
f
o
2
/
X
O
D
D
.
t
u
p
t
u
o
e
h
t
f
o
2
/
V
o
t
t
n
i
o
p
g
n
i
s
s
o
r
c
t
u
p
n
i
l
a
i
t
n
e
r
e
f
f
i
d
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
B
1
E
T
O
N
X
O
D
D
.
t
u
p
t
u
o
e
h
t
f
o
2
/
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
k
n
a
b
a
n
i
h
t
i
w
w
e
k
s
s
a
d
e
n
i
f
e
D
:
2
E
T
O
N
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
3
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
X
O
D
D
.
2
/
s
e
i
c
n
e
u
q
e
r
f
t
n
e
r
e
f
f
i
d
t
a
g
n
i
t
a
r
e
p
o
n
o
i
t
c
e
r
i
d
e
m
a
s
e
h
t
n
i
g
n
i
h
c
t
i
w
s
s
t
u
p
t
u
o
f
o
s
k
n
a
b
s
s
o
r
c
a
w
e
k
s
s
a
d
e
n
i
f
e
D
:
4
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
h
t
i
w
X
O
D
D
.
2
/
l
a
u
q
e
h
t
i
w
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
a
g
n
i
t
a
r
e
p
o
s
e
c
i
v
e
d
t
n
e
r
e
f
f
i
d
n
o
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
5
E
T
O
N
V
t
a
d
e
r
u
s
a
e
m
s
i
t
u
p
t
u
o
e
h
t
,
e
c
i
v
e
d
h
c
a
e
n
o
t
u
p
n
i
f
o
e
p
y
t
e
m
a
s
e
h
t
g
n
i
s
U
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
X
O
D
D
.
2
/
.
n
o
i
t
c
u
d
o
r
p
n
i
d
e
t
s
e
t
t
o
N
.
n
o
i
t
a
z
i
r
e
t
c
a
r
a
h
c
y
b
d
e
e
t
n
a
r
a
u
g
e
r
a
s
r
e
t
e
m
a
r
a
p
e
s
e
h
T
:
6
E
T
O
N
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
7
E
T
O
N
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
8
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
3.3V/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.40.9V
V
DDOx
GND = -0.9V5%
V
DD
+0.9V5%
SCOPE
Qx
LVCMOS
3.3V/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.05V5%
V
DDOx
GND = -1.25V5%
V
DD
1.25V5%
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
DD
,
V
DDOx
= 1.65V5%
GND = -1.65V5%
D
IFFERENTIAL
I
NPUT
L
EVEL
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
S
KEW
V
CMR
Cross Points
V
PP
GND
CLK1
nCLK1
V
DD
tsk(o)
V
DDOX
2
V
DDOX
2
Qx
Qy
tsk(pp)
V
DDOX
2
V
DDOX
2
Qx
Qy
PART 1
PART 2
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
9
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
t
PD
V
DDOX
2
V
DD
2
P
ROPAGATION
D
ELAY
B
ANK
S
KEW
(
where X denotes outputs in the same bank
)
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
nCLK1
CLK1
QAx,QBx,
QCx, QDx
odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDOX
2
QAx, QBx,
QCx, QDx
CLK0
tsk(o)
V
DDOX
2
V
DDOX
2
O
UTPUT
R
ISE
/F
ALL
T
IME
QX0:QX0
QX0:QX0
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
10
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
A
PPLICATION
I
NFORMATION
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
11
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
F
IGURE
2C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
2B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
2D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 4A to 4E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
2A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 2A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
2E. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
12
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS87016 is: 2034
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
13
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
C
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
8
4
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
7
1
.
0
2
2
.
0
7
2
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
5
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
5
.
5
e
C
I
S
A
B
0
5
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
q
0
-
-
7
c
c
c
-
-
-
-
8
0
.
0
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
14
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
g
n
i
k
r
a
M
e
g
a
k
c
a
P
t
n
u
o
C
e
r
u
t
a
r
e
p
m
e
T
Y
A
6
1
0
7
8
S
C
I
Y
A
6
1
0
7
8
S
C
I
P
F
Q
L
d
a
e
L
8
4
y
a
r
t
r
e
p
0
5
2
C
5
8
o
t
C
0
T
Y
A
6
1
0
7
8
S
C
I
Y
A
6
1
0
7
8
S
C
I
l
e
e
R
d
n
a
e
p
a
T
n
o
P
F
Q
L
d
a
e
L
8
4
0
0
0
1
C
5
8
o
t
C
0
Integrated
Circuit
Systems, Inc.
87016AY
www.icst.com/products/hiperclocks.html
REV. A JUNE 4, 2003
15
ICS87016
L
OW
S
KEW
, 1-
TO
-16
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
E
E
H
S
Y
R
O
T
S
I
H
N
O
I
S
I
V
E
R
v
e
R
e
l
b
a
T
e
g
a
P
e
g
n
a
h
C
f
o
n
o
i
t
p
i
r
c
s
e
D
e
t
a
D
A
,
B
5
T
,
A
5
T
C
5
T
,
7
,
6
8
m
o
r
f
,
n
o
i
t
c
e
s
s
e
t
o
N
e
h
t
n
i
e
n
il
t
s
r
i
f
e
h
t
d
e
t
c
e
r
r
o
c
-
e
l
b
a
T
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
C
A
.
z
H
M
0
5
2
o
t
"
.
.
.
z
H
M
0
5
1
t
a
d
e
r
u
s
a
e
m
s
r
e
t
e
m
a
r
a
p
ll
A
"
2
0
/
1
3
/
7
A
"
r
o
t
a
r
e
n
e
G
k
c
o
l
C
S
O
M
C
V
L
-
o
t
-
l
a
i
t
n
e
r
e
f
f
i
D
"
m
o
r
f
e
l
t
i
t
n
o
i
t
p
i
r
c
s
e
d
t
r
a
p
d
e
s
i
v
e
R
.
"
r
o
t
a
r
e
n
e
G
k
c
o
l
C
S
O
M
C
V
L
"
o
t
2
0
/
9
/
8
A
B
5
T
&
A
5
T
7
&
6
2
1
d
n
a
0
K
L
C
r
o
f
s
e
u
l
a
v
y
a
l
e
d
p
o
r
p
d
e
h
c
t
i
w
s
-
e
l
b
a
T
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
C
A
.
1
K
L
C
n
,
1
K
L
C
.
n
o
i
t
c
e
s
e
c
a
f
r
e
t
n
I
t
u
p
n
I
k
c
o
l
C
l
a
i
t
n
e
r
e
f
f
i
D
d
e
d
d
A
.
t
a
m
r
o
f
d
e
t
a
d
p
U
3
0
/
5
0
/
5
A
1
.
k
c
o
l
b
h
c
t
a
l
d
e
t
c
e
r
r
o
c
,
m
a
r
g
a
i
D
k
c
o
l
B
d
e
i
f
i
d
o
M
3
0
/
4
/
6