Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Input Control Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- LVDS DC Characteristics
- AC Characteristics
- Additive Phase Jitter
- Parameter Measurement Information
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Recommendations for Unused Input and Output Pins
- Clock Input Interface
- Host Bus Adaptor Board Diagram
- Linecard Diagram
- 2.5V LVDS Driver Termination
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
85454AK-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 19, 2006
1
Integrated
Circuit
Systems, Inc.
ICS85454-01
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVDS M
ULTIPLEXER
0
1
0
1
LOOP0
LOOP1
G
ENERAL
D
ESCRIPTION
The ICS85454-01 is a 2:1/1:2 Multiplexer and
a member of the HiPerClockS
TM
family of high
performance clock solutions from ICS. The 2:1
Multiplexer allows one of 2 inputs to be select-
ed onto one output pin and the 1:2 MUX
switches one input to both of two outputs. This device
may be useful for multiplexing multi-rate Ethernet PHYs
which have 100Mbit and 1000Mbit transmit/receive
pairs onto an optical SFP module which has a single
transmit/receive pair. Another mode allows loop back
testing and allows the output of a PHY transmit pair to be
routed to the PHY input pair. For examples, please refer to
the Application Information section of the data sheet.
The ICS85454-01 is optimized for applications requiring
very high performance and has a maximum operating
frequency in 2.5GHz. The device is packaged in a small,
3mm x 3mm VFQFN package, making it ideal for use on
space-constrained boards.
F
EATURES
Dual 2:1/1:2 MUX
Three LVDS outputs
Three differential inputs
Differential inputs can accept the following differential
levels: LVPECL, LVDS, CML
Loopback test mode available
Maximum output frequency: 2.5GHz
Part-to-part skew: 250ps (maximum)
Additive phase jitter, RMS: 0.05ps (typical)
Propagation delay: 550ps (maximum)
2.5V operating supply
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
ICS
ICS85454-01
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
QA0
nQA0
QA1
nQA1
INA0
nINA0
INA1
nINA1
INB
nINB
SELB
GND
QB
nQB
SELA
V
DD
1
2
3
4
12
11
10
9
5 6 7 8
16 15 14 13
INB
nINB
QB
nQB
INA0
nINA0
QA0
nQA0
INA1
nINA1
QA1
nQA1
SELA
SELB
85454AK-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 19, 2006
2
Integrated
Circuit
Systems, Inc.
ICS85454-01
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVDS M
ULTIPLEXER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. I
NPUT
C
ONTROL
F
UNCTION
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85454AK-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 19, 2006
3
Integrated
Circuit
Systems, Inc.
ICS85454-01
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVDS M
ULTIPLEXER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V 5%
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
10mA
Surge Current
15mA
Operating Temperature Range, TA -40C to +85C
Storage Temperature, T
STG
-65C to 150C
Package Thermal Impedance,
JA
51.5C/W (0 lfpm)
(Junction-to-Ambient)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
t o the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
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,
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= 2.5V 5%
T
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DC C
HARACTERISTICS
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+
85454AK-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 19, 2006
4
Integrated
Circuit
Systems, Inc.
ICS85454-01
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVDS M
ULTIPLEXER
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 2.375V
TO
2.625V
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= 2.5V 5%
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85454AK-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 19, 2006
5
Integrated
Circuit
Systems, Inc.
ICS85454-01
D
UAL
2:1/1:2
D
IFFERENTIAL
-
TO
-LVDS M
ULTIPLEXER
A
DDITIVE
P
HASE
J
ITTER
Additive Phase Jitter
at
622.08MHz (12kHz - 20MHz)
= 0.05ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the
dBc Phase Noise.
This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of
the noise power present in a 1Hz band at a specified offset
from the fundamental frequency to the power value of the
fundamental. This ratio is expressed in decibels (dBm) or a
As with most timing specifications, phase noise measure-
ments have issues. The primary issue relates to the limita-
tions of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
ratio of the power in the 1Hz band to the power in the funda-
mental. When the required offset is specified, the phase noise
is called a
dBc
value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the fre-
quency domain, we get a better understanding of its effects
on the desired application over the entire time record of the
signal. It is mathematically possible to calculate an expected
bit error rate given a phase noise plot.
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dB
c/H
Z
PDF 
ZIP