ICS674-01
MDS 674-01 B
1
Revision 062003
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 295-9800
l
www.icst.com
U
SER
C
ONFIGURABLE
D
IVIDER
Description
The ICS674-01 consists of two separate configurable
dividers. The A Divider is a 7-bit divider and can divide
by 3 to 129. The B Divider consists of a 9-bit divider
followed by a post divider. The 9-bit divider can divide
by 12 to 519. The post divider has eight settings of 1, 2,
4, 5, 6, 7, 8, and 10 - giving a maximum total divide of
5190. The A and B Dividers can be cascaded to give a
maximum divide of 669510. The ICS674-01 supports
the ICS673 PLL Building Block and enables the user to
build a full custom PLL synthesizer.
Features
Packaged in 28 pin SSOP (150 mil body)
Supports ICS673 PLL Building Block
User determines the divide by setting input pins
Pull-ups on all select inputs
Includes one 7-bit Divider for OUTA
Includes one 9-bit Divider and one selectable Post
Divider for OUTB
Industrial temperature range available
25mA drive capability at TTL levels
Advanced, low power CMOS process
Operating voltage of 3.3V or 5V
Block Diagram
OUTB
VDD
INA
OUTA
Divider A
(7-Bit)
Divider B
(9-Bit)
INB
Post
Divider
2
7
A6:A0
B8:B0
9
GND
3
S2:S0
3
U
SER
C
ONFIGURABLE
D
IVIDER
MDS 674-01 B
2
Revision 062003
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 295-9800
l
www.icst.com
ICS674-01
Pin Assignment
Post Divider Table
Pin Descriptions
18
7
17
8
16
9
15
INA
10
INB
11
GND
12
OUTB
13
B0
14
B1
GND
GND
B8
B2
B7
B5
B3
B6
22
21
20
19
B4
OUTA
5
6
S2
VDD
VDD
24
23
A0
3
4
S0
S1
A1
26
25
A2
1
2
A5
A6
A3
28
27
A4
28 pin (150 mil) SSOP
S2
Pin 5
S1
Pin 4
S0
Pin 3
Post Divide
0
0
0
10
0
0
1
2
0
1
0
8
0
1
1
4
1
0
0
5
1
0
1
7
1
1
0
1
1
1
1
6
Pin
Number
Pin
Name
Pin Type
Pin Description
1, 2, 24 - 28
A5, A6, A0-A4
Input
Divider A word input pins. Forms a binary number from 3 to 129. Internal
pull-up resistors.
3 - 5
S0, S1, S2
Input
Select pins for Post Divider. See table above. Internal pull-up resistors.
6, 23
VDD
Power
Connect to VDD.
7
INA
Input
Divider A input.
8
INB
Input
Divider B input.
9, 19 - 20
GND
Power
Connect to ground.
10 - 18
B0 - B8
Input
Divider B word input pins. Forms a binary number from 12 to 519. Internal
pull-up resistors.
21
OUTB
Output
Divider B output.
22
OUTA
Output
Divider A output.
U
SER
C
ONFIGURABLE
D
IVIDER
MDS 674-01 B
3
Revision 062003
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 295-9800
l
www.icst.com
ICS674-01
External Components
The ICS674-01 requires a minimum number of external components for proper operation. A 0.01
mF
decoupling capacitors should be connected between VDD and GND as close to the device as possible. A
series termination resistor of 33
W may be used in series with OUTA and OUTB pins.
Determining (setting) the divider
The user has full control in setting the desired divide. The user should connect the appropriate divider select input
pins directly to ground (or VDD, although this is not required because of internal pull-ups) during Printed Circuit
Board layout, ensuring that the ICS674-01 will automatically produce the correct divide when all components are
soldered. It is also possible to connect the inputs to parallel I/O ports in order to change divides. The divides of the
ICS674-01 can be determined by the following simple equations:
Divide A = DAW + 2
Where
Divider A Word (DAW) = 1 to 127 (0 is not permitted)
Divide B = (DBW+8) x PD
Where
Divider B Word (DBW) = 4 to 511 (0, 1, 2, 3 are not permitted)
Post Divider (PD) = values on page 2
For example, suppose Divide A is desired to be 61 and Divide B is desired to be 284, then DAW = 59, DBW = 276,
and PD = 1. This means A6:A0 is 0111011, B8:B0 is 100010100 and S2:S0 is 110. Since all inputs have pull-ups, it
is only necessary to ground the zero pins, namely A6, A2, B7, B6, B5, B1, B0, and S0.
U
SER
C
ONFIGURABLE
D
IVIDER
MDS 674-01 B
4
Revision 062003
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 295-9800
l
www.icst.com
ICS674-01
Using the ICS674-01 with the ICS673-01:
The ICS674-01 may be used with the ICS673-01 to build a frequency synthesizer. The following example shows a
typical application when the reference clock is in the MHz range:
If the reference is in the kHz range, for example 8 kHz, the following configuration may be more typical:
Note that in both examples, Divide B is connected to the output of the ICS673. This is because Divide B has a higher
operating frequency than Divide A.
Reference Clock
Ouput Clock
Divide A
Post
Divide
ICS674-01
Divide B
ICS673-01
REFIN
FBIN
CLK1
CLK2
Reference Clock
Ouput Clock
Post
Divide
ICS674-01
Divide B
ICS673-01
REFIN
FBIN
CLK1
CLK2
Divide A
U
SER
C
ONFIGURABLE
D
IVIDER
MDS 674-01 B
5
Revision 062003
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 295-9800
l
www.icst.com
ICS674-01
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS674-01. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
DC Electrical Characteristics
VDD=5V 10%,
Ambient temperature -40 to +85
C, unless stated otherwise
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5V to VDD+0.5V
CLKIN and FBIN inputs
-0.5V to 5.5V
Electrostatic Discharge
2000 V
Ambient Operating Temperature
0 to +70
C
Ambient Operating Temperature (I version)
-40 to +85
C
Storage Temperature
-65 to +150
C
Junction Temperature
150
C
Soldering Temperature
260
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+3.0
+5.5
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
5.5
V
Input High Voltage
V
IH
All A, B, and S pins
2
V
Input Low Voltage
V
IL
All A, B, and S pins
0.8
V
Input High Voltage
V
IH
INA and INB only
(VDD/2)+1 VDD/2
V
Input Low Voltage
V
IL
INA and INB only
VDD/2
(VDD/2)-1
V
Output High Voltage
V
OH
I
OH
= -25 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 25mA
0.4
V
Operating Supply Current
DivA=DivB=20
IDD
No load, f
in
=100 MHz
3.3 V
3
mA
No load, f
in
=100 MHz
5 V
5
mA
U
SER
C
ONFIGURABLE
D
IVIDER
MDS 674-01 B
6
Revision 062003
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 295-9800
l
www.icst.com
ICS674-01
AC Electrical Characteristics
VDD = 5V, Ambient Temperature -40 to +85
C, C
LOAD
at CLK = 15 pF, unless stated otherwise
1
The duty cycle of OUTA is dependent on the selected divide. This because OUTA goes low for 2 input
clock cycles on INA. For example, if a divide of 20 is selected, the duty cycle will be 90%. Simlarly, if PD=1
is selected for OUTB, the duty cycle will be dependent on the selected divide. In this case, OUTB goes high
for approximately 8 input clock cycles on INB.
Short Circuit Current
I
OS
Each output
70
mA
On-Chip Pull-up Resistor
R
PU
A, B, S select pins
270
k
W
Input Capacitance
C
IN
A, B, S select pins
5
pF
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Input Frequency, Divider A
f
IN
3.3V
0
135
MHz
Input Frequency, Divider B
3.3V
0
180
MHz
Input Frequency, Divider A
5V
0
200
MHz
Input Frequency, Divider B
5V
0
235
MHz
Input Frequency, Divider A
(Industrial temperature)
f
IN
at 3.3V, +85
C
0
125
MHz
Input Frequency, Divider B
(Industrial temperature)
at 3.3V, +85
C
0
170
MHz
Input Frequency, Divider A
(Industrial temperature)
at 5V, +85
C
0
190
MHz
Input Frequency, Divider B
(Industrial temperature)
at 5V, +85
C
0
220
MHz
Output Rise Time
t
OR
0.8 to 2.0V
1
ns
Output Fall Time
t
OF
2.0 to 0.8V
1
ns
OUTB Clock Duty Cycle
1
t
DC
at VDD/2
45
49 to
51
55
%
OUTB Clock Duty Cycle
odd post dividers
at VDD/2, except PD=1
40
60
%
OUTA Clock Duty Cycle
1
at VDD/2
20
98.5
%
Input to Output Skew
rising edges at VDD/2, FBIN
to CLK8
350
ps
Maximum Absolute JItter
15pF
300
ps
Cycle to Cycle Jitter
30pF loads
500
ps
PLL Lock Time
Note 3
1.0
ms
U
SER
C
ONFIGURABLE
D
IVIDER
MDS 674-01 B
7
Revision 062003
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 295-9800
l
www.icst.com
ICS674-01
Package Outline and Package Dimensions
(20 pin SSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as
those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant
any ICS product for use in life support devices or critical medical instruments.
Part / Order Number
Marking
Shipping
packaging
Package
Temperature
ICS674R-01
674R-01
Tubes
28 pin SSOP
0 to +70
C
ICS674R-01T
674R-01
Tape and Reel
28 pin SSOP
0 to +70
C
ICS674R-01I
674R-01I
Tubes
28 pin SSOP
-40 to 85
C
ICS674R-01IT
674R-01I
Tape and Reel
28 pin SSOP
-40 to 85
C
INDEX
AREA
1 2
28
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
.10 (.004)
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
1.35
1.75
.053
.069
A1
0.10
0.25
.0040
.010
A2
--
1.50
--
.059
b
0.20
0.30
0.008
0.012
C
0.18
0.25
.007
.010
D
9.80
10.00
.386
.394
E
5.80
6.20
.228
.244
E1
3.80
4.00
.150
.157
e
0.635 Basic
0.025 Basic
L
0.40
1.27
.016
.050
a
0
8
0
8
PDF 
ZIP