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Электронный компонент: ICS1524

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Integrated
Circuit
Systems, Inc.
General Description
Features
ICS1524
ICS1524 Rev C 01/31/2003
Block Diagram
Dual Output Phase Controlled SSTL_3/PECL Clock Generator
Wide input frequency range
8 kHz to 100 MHz
250 MHz balanced PECL differential outputs
150 MHz single-ended SSTL_3 clock outputs
Dynamic Phase Adjust (DPA) for DPACLK
outputs
Software controlled phase adjustment
360
o
Adjustment down to 1/64 clock
increments
External or internal loop filter selection
Uses 3.3 VDC Inputs are 5 volt tolerant.
I
2
C-bus serial interface runs at either low speed
(100 kHz) or high speed (400 kHz).
Hardware and Software PLL Lock detection
The ICS1524 is a low-cost, very high-performance
frequency generator and phase controlled clock synthe-
sizer. It is perfectly suited to phase controlled clock
synthesis and distribution as well as line-locked and
genlocked applications.
The ICS1524 offers two channels of clock phase con-
trolled outputs; CLK and DPACLK. These two output
channels have both 250 MHz PECL differential and 150
MHz SSTL_3 single-ended output pins. The CLK output
channel has a fixed phase relationship to the PLL's input
and the DPACLK uses the Dynamic Phase Adjust cir-
cuitry to allow control of the clock phase relative to input
signal.
Optionally, the CLK outputs can operate at half the clock
rate and phase aligned with the DPACLK channel, en-
abling deMUXing of multiplexed analog-to-digital
converters. The FUNC pin provides either the regener-
ated input from the phase-locked loop (PLL) divider
chain output or a re-synchronized and sharpened input
HSYNC.
The advanced PLL uses either its internal program-
mable feedback divider or an external divider and is
programmed by a standard I
2
C-busTM serial interface.
I
2
C-bus is a trademark of Philips Corporation.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
Applications
Generic Frequency Synthesis
LCD Monitors and Projectors
Genlocking Multiple Video Systems
HSYNC
OSC
I C
2
DPACLK+/-
FUNC
DPACLK
Loop
Filter
CLK+/-
CLK
Pin Configuration
24 Pin 300-mil SOIC
IC
S
1
5
2
4
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDDD
VSSD
SDA
SCL
PDEN
EXTFB
HSYNC
EXTFIL
XFILRET
VDDA
VSSA
OSC
IREF
CLK+ (PECL)
C
VSSQ
VDDQ
CLK (SSTL)
CLK (SSTL)
FUNC (SSTL)
LOCK/REF (SSTL)
I CADR
LK (PECL)
DPACLK+ (PECL)
DPACLK (PECL)
DPA
2
ICS1524
2
ICS1524 Rev C 01/31/2003
Document Revision History
Rev A
ICS1523 Rev T Datasheet used as a starting template
New Block Diagram substituted for old 1523 one
Removed reference to CLK / 2 Functionality
Created a set of clock outputs that bypass the DPA
External PDEN is now the IN-SEL MUX control bit
Text descriptions changed to support new 1524 block diagram
Rev B
Replaced page 15 "Layout Guidelines"
Replaced SIOC Package diagram on page 22
"Advanced Status" removed
Redrew front page graphics for clairity
Rev C
Corrected Chip Revision and Chip Version values on page 5
Changed Title on Page 1
Minor format changes to pages 8 and 21
Corrected pin names on page 10
3
ICS
1
5
2
4
ICS1524 Rev C 01/31/2003
Block Diagram
ICS1524 Block Diagram
June 25, 2001
Charge
Pump
Phase/
Freq
Detector
VCO
Post-
Scaler
Divider
EXTFIL (8)
Ref_Pol
Reg 0:2
HSYNC
(7)
EXTFB
(6)
MUX
Fbk_Sel
Reg 0:4
DPACLK+ (21)
DPACLK (20)
DPACLK (17)
FUNC (15)
I
2
C
Interface
Power-
On
Reset
SCL
(4)
SDA
(3)
CLK+ (23)
CLK (22)
MUX
Func_Sel
Reg 0:5
CLK (16)
MUX
OSC
(12)
Osc
Divider
XFILRET (9)
I
2
CADR
(13)
Lock
Logic
PECL
Bias
IREF
(24)
Int Filter
LOCK/REF (14)
Filter
Select
DPA_Lock
Reg 12:0
PFD
Reg 1:0-2
PLL_Lock
Reg 12:1
En_DLS
Reg 0:7
En_PLS
Reg 0:6
PD_Pol
Reg 0:1
Osc_Div
Reg 7:0-6
PSD
Reg 1:4-5
Fil_Sel
Reg 4:7
DPA_OS
Reg 4:0-5
Reg
OE_F
Reg 6:4
6
:
OE_P2
Reg 2
Reg
OE_T2
6:3
OE-Pck
Reg 6:0
OE_Tck
Reg 6:1
Feedback
Divider
FDB0
2:0-7
FDB1
Reg: 3:0-3
Fbk_Pol
Reg 0:3
DPA_Res
Reg 5:0-1
0
1
0
1
0
1
+
+
Dynamic
Phase
Adjust
PDEN (5)
Ck2_Inv
Reg 6:5
MUX
0
1
Output
Scaler
Out_Scl
Reg 6:6-7
PDen
Reg 0:0
ICS1524
4
ICS1524 Rev C 01/31/2003
Pin Descriptions
Notes:
1. These LVTTL inputs are 5 V-tolerant.
2. Connect to ground if unused.
.
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5
ICS1524
ICS1524 Rev C 01/31/2003
I
2
C Register Map Summary
Register
Index
Name
Access
Bit Name
Bit #
Reset
Value
Description
0h
Input Control
R / W
PDen
0
1
Phase Detector Enable (0=Disable 1=Enable)
PD_Pol
1
0
Phase Detector Input Select
Ref_Pol
2
0
External Reference Polarity (0=Positive Edge, 1=Negative Edge)
Fbk_Pol
3
0
External Feedback Polarity (0=Positive Edge, 1=Negative Edge)
Fbk_Sel
4
0
External Feedback Select (0=Internal Feedback, 1=External)
Func_Sel
5
0
Function Out Select (0=Recovered HSYNC, 1=Input HSYNC)
EnPLS
6
1
Enable PLL Lock/Ref Status Output (0=Disable 1=Enable)
EnDLS
7
0
Enable DPA Lock/Ref Status Output (0=Disable 1=Enable)
1h
Loop Control
R / W *
PFD0-2
0-2
0
Phase Detector Gain
Reserved
3
0
Reserved
PSD0-1
4-5
0
Post-Scaler Divider (0 = /2, 1 = /4, 2 = /8, 3 = /16)
Reserved
6-7
0
Reserved
2h
FdBk Div 0
R / W *
FBD0-7
0-7
FF
PLL FeedBack Divider LSBs (bits 0-7) *
3h
FdBk Div 1
R / W *
FBD8-11
0-3
F
PLL Feedback Divider MSBs (bits 8-11) *
Reserved
4-7
0
Reserved
4h
DPA Offset
R / W
DPA_OS0-5
0-5
0
Dynamic Phase Aligner Offset
Reserved
6
0
Reserved
Fil_Sel
7
1
Loop Filter Select (0=External, 1=Internal)
5h
DPA Control
R / W ** DPA_Res0-1
0-1
3
DPA Resolution (0=16 delay elements, 1=32, 2=Reserved, 3=64)
Metal_Rev
2-7
0
Metal Mask Revision Number
6h
Output Enables
R / W
OE_Pck
0
1
Output Enable for PECL DPACLK ( 0=High Z, 1=Enabled)
OE_Tck
1
1
Output Enable for STTL_3 DPACLK ( 0=High Z, 1=Enabled)
OE_P2
2
1
Output Enable for PECL CLK ( 0=High Z, 1=Enabled)
OE_T2
3
1
Output Enable for STTL_3 CLK ( 0=High Z, 1=Enabled)
OE_F
4
1
Output Enable for STTL_3 FUNC ( 0=High Z, 1=Enabled)
Ck2_Inv
5
0
Select non-delayed CLK (1) or DPA delayed CLK/2 (0) on CLKx pins
Out_Scl
6-7
0
SSTL DPACLK (Pin 17) Scaler (0 = 1, 1 = 2, 2 = 4, 3 = 8)
7h
Osc_Div
R / W
Osc_Div 0-6
0-6
0
Osc Divider modulus
In-Sel
7
1
RESERVED
8h
Reset
Write
DPA
0-3
x
Writing xA hex resets DPA and loads working register 5
PLL
4-7
x
Writing 5x hex resets PLL and loads working registers 1-3
10h
Chip Ver
Read
Chip Ver
0-7
18
Chip Version 17 hex
11h
Chip Rev
Read
Chip Rev
0-7
01
Chip Revision C2 hex
12h
Rd_Reg
Read
DPA_Lock
0
N/A
DPA Lock Status (0=Unlocked, 1=Locked)
PLL_Lock
1
N/A
PLL Lock Status (0=Unlocked, 1=Locked)
Reserved
2-7
0
Reserved
* Identifies double-buffered registers. Working registers are loaded during software PLL reset.
** Identifies double-buffered register. Working registers are loaded during software DPA reset.
ICS1524
6
ICS1524 Rev C 01/31/2003
Detailed Register Description
Name:
Input Control
Register:
0 h
Index:
Read / Write
Bit
Name
Description
0
PDen
RESERVED
1
PD_Pol
Input MUX Control
2
Ref_Pol
Phase/Frequency Detector External Reference Polarity --
Edge of input signal on which Phase Detector triggers.
0 = Rising Edge (default)
1 = Falling Edge
3
Fbk_Pol
External Reference Feedback Polarity -- Edge of EXTFB (pin 6) signal on which
Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1).
0 = Positive Edge (default)
1 = Negative Edge
4
Fbk_Sel
External Feedback Select
0 = Internal Feedback (default)
1 = External Feedback
5
Func_Sel
Function Output Select -- Selects re-clocked output to FUNC (pin 15).
0 = Recovered HSYNC (default). Regenerated HSYNC output.
1 = External HSYNC. Schmitt-trigger conditioned input from HSYNC (pin 7).
6
EnPLS
Enable LOCK/REF (pin14) Output
7
EnDLS
Bit Name Bit # Reset Value Description
PDen
0
1
Phase detector Enable
PD_Pol
1
0
Phase/Frequency Detector Input MUX Control
Ref_Pol
2
0
Phase/Frequency Detector External Reference Polarity
Fbk_Pol
3
0
External Reference Feedback Polarity
Fbk_Sel
4
0
External Feedback Select
Func_Sel
5
0
Function Output Select
EnPLS
6
1
Enable PLL Lock Status Output on LOCK/REF pin
EnDLS
7
0
Enable DPA Lock Status Output on LOCK/REF pin
L
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P
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1
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7
ICS1524
ICS1524 Rev C 01/31/2003
Name:
Loop Control Register
Register:
1h
Index:
Read / Write*
Bit Name Bit # Reset Value Description
PFD0-2
0 - 2
0
Phase Frequency Detector Gain
Reserved
3
0
Reserved
PSD 0-1
4 - 5
0
Post-Scaler Divider
Reserved
6 -7
0
Reserved
Bit
Name
Description
0-2
PFD0-2
Phase/Frequency Detector Gain
3
Reserved
4-5
PSD 0-1
Post-Scaler Divider -- Divides the output of the VCO to the DPA and Feedback Divider.
6-7
Reserved
*
Double-buffered register. Actual working registers are loaded during software PLL reset.
See register 8h for details.
2
t
i
B
1
t
i
B
0
t
i
B
2
/
A
(
n
i
a
G
D
F
P
)
d
a
r
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
6
1
1
0
1
2
3
1
1
0
4
6
1
1
1
8
2
1
5
t
i
B
4
t
i
B
r
e
d
i
v
i
D
D
S
P
0
0
)
t
l
u
a
f
e
d
(
2
0
1
4
1
0
8
1
1
6
1
ICS1524
8
ICS1524 Rev C 01/31/2003
Name:
Feedback Divider 0 Register / Feedback Divider 1 Register
Register:
2h, 3h
Index:
Read / Write*
Bit Name
Index
Bit #
Reset Value
Description
FBD 0-7
2
0 -7
FF
PLL Feedback Divider LSBs (0 -7).* When Bit 0 = 0, then the total
number of clocks per line is even. When Bit 0 = 1, then the total
number of clocks is odd.
FBD 8 -11
3
0 -3
F
PLL Feedback Divider MSBs (8 -11)*
Reserved
3
4 -7
Reserved
Feedback Divider Modulus
=
*
Double-buffered registers. Actual working registers are loaded during software PLL reset.
See Register 8h for details.
Name:
DPA Offset Register
Register:
4h
Index:
Read / Write
Bit Name
Bit # Reset Value
Description
DPA_OS0-5
0 - 5
0
Dynamic Phase Adjust Offset
Reserved
6
0
Reserved
Fil_Sel
7
0
Loop Filter Select
Bit
Name
Description
0-5
DPA_OS0-5
Dynamic Phase Adjust Offset.
Selects clock edge offset in discrete steps from zero to one clock period minus one step.
Resolution (number of delay elements per clock cycle) is selected by DPA_Res0-1 (Reg 5:0-1).
Note: Offsets equal to or greater than one clock period are neither recommended nor supported.
Example: For DPA_Res0-1=01H, the clock can be delayed from 0 to 31 steps.
7
Fil_Sel
Selects external loop filter (0) or internal loop filter (1).
The use of an external loop filter is strongly recommended for all designs. Typical loop filter
values are 6.8K Ohms for the series resistor, 3300 pF RF-type capacitor for the series capacitor,
and 33 pF for the shunt capacitor.
12
Feedback Divider Modulus
4103
The value that is programmed into these two registers, plus a value of 8, defines the total number of clock periods that the ICS
1524 generates between HSYNCs. Program these registers with the total number of horizontal clocks per line minus 8.
3
g
e
R
2
g
e
R
3
2
1
0
7
6
5
4
3
2
1
0
+8
9
ICS1524
ICS1524 Rev C 01/31/2003
Name:
DPA Control Register
Register:
5h
Index:
Read / Write*
Bit Name
Bit # Reset Value
Description
DPA_Res 0-1
0 - 1
3
Dynamic Phase Adjust Resolution Select.
Metal_Rev
2- 7
0
Metal Mask Revision Number.
Bit
Name
Description
0-1
DPA_Res 0 -1
Dynamic Phase Adjust (DPA) Resolution Select.
It is not recommended to use the DPA above 160 MHz.
2-7
Metal_Rev
Metal Mask Revision Number.
After power-up, register bits 7:2 must be written with 111111. After this write,
a read indicates the metal mask revision, as below.
*
Double-buffered register. Actual working registers are loaded during software DPA reset.
See register 8h for details.
Bit 1
Bit 0
Delay Elements
0
0
16
48
160
0
1
32
24
80
1
0
Reserved
1
1
64
12
40
CLK Range, MHz
n
o
i
s
i
v
e
R
7
t
i
B
6
t
i
B
5
t
i
B
4
t
i
B
3
t
i
B
2
t
i
B
A
1
1
1
1
1
1
B
0
1
1
1
1
1
1
C
1
0
1
1
1
1
2
C
0
0
1
1
1
1
D
1
1
0
1
1
1
E
1
1
1
0
1
1
F
1
1
1
1
0
1
G
1
1
1
1
1
0
ICS1524
10
ICS1524 Rev C 01/31/2003
Name:
Output Enable Register
Register:
6 h
Index:
Read / Write
Bit Name Bit # Reset Value Description
OE_Pck
0
0
Output Enable for DPACLK Outputs (PECL, Pins 21, 20 )
OE_Tck
1
0
Output Enable for DPACLK Output (SSTL_3 Pin 17)
OE_P2
2
0
Output Enable for CLK Outputs (PECL, Pins 23, 22)
OE_T2
3
0
Output Enable for CLK Output (SSTL_3, Pin 16)
OE_F
4
0
Output Enable for FUNC Output (SSTL_3, Pin 15)
Sel_1X
5
0
Select CLK Output Source (Pins 23, 22, 16)
Out_Scl
6-7
0
CLK Output Scaler (SSTL_3, Pin 16)
Bit
Name
Description
0
OE_Pck
Output Enable for DPACLK Outputs (PECL)
0 = High Z
1 = Enabled
1
OE_Tck
Output Enable for DPACLK Output (SSTL_3)
0 = High Z
1 = Enabled
2
OE_P2
Output Enable for CLK Outputs (PECL)
0 = High Z
1 = Enabled
3
OE_T2
Output Enable for CLK Output (SSTL_3)
0 = High Z
1 = Enabled
4
OE_F
Output Enable for FUNC Output (SSTL_3)
0 = High Z
1 = Enabled
5
Ck2_Inv
Select CLK Output Source (Pins 23, 22, 16)
0 = Half Speed DPA Delayed clock to CLK outputs
1 = Full Speed non-DPA Delayed clock to CLK outputs
6 -7
Out_Scl
Clock (CLK, pin 16) Scaler
7
t
i
B
6
t
i
B
r
e
d
i
v
i
D
K
L
C
0
0
1
0
1
2
1
0
4
1
1
8
11
ICS1524
ICS1524 Rev C 01/31/2003
Name:
Oscillator Divider Register
Register:
7h
Index:
Read / Write
Bit Name
Bit #
Reset Value
Description
Osc_Div 0-6
0-6
0
Osc Divider Modulus
In_Sel
7
1
Input Select
Bit
Name
Description
0 - 6
Osc_Div 0-6
Oscillator Divider Modulus.
Divides the input from OSC (pin 12) by the set modulus.
The modulus equals the programmed value, plus 2.
Therefore, the modulus range is from 3 to 129.
7
In_Sel
Input Select -- Selects the input to the Phase/Frequency Detector
0 = HSYNC
1 = Osc Divider
Name:
RESET Register
Register:
8 h
Index:
Write
Bit Name
Bit #
Reset Value
Description
DPA Reset
0 -3
x
Writing xAh to this register resets DPA working register 5
PLL Reset
4 -7
x
Writing 5xh to this register resets PLL working registers 1-3
Bit
Name
Description
0 - 3
DPA
Writing xAh to this register resets DPA working register 5
4 -7
PLL
Writing 5xh to this register resets PLL working registers 1-3
e
u
l
a
V
s
t
e
s
e
R
A
x
A
P
D
x
5
L
L
P
A
5
L
L
P
d
n
a
A
P
D
ICS1524
12
ICS1524 Rev C 01/31/2003
Name:
Chip Version Register
Register:
10 h
Index:
Read
Bit Name
Bit #
Reset Value
Description
Chip Ver
0-7
17
Chip Version 24 (18h )
Name:
Chip Revision Register
Register:
11h
Index:
Read
Bit Name
Bit #
Reset Value
Description
Chip Rev
0 -7
01+
Initial value 01h.
+Value increments with each all-layer change.
Name:
Status Register
Register:
12 h
Index:
Read
Bit Name
Bit # Reset Value
Description
DPA_Lock
0
N/A
DPA Lock Status
PLL_Lock
1
N/A
PLL Lock Status
Reserved
2 -7
0
Reserved
Bit
Name
Description
0
DPA_Lock
DPA Lock Status. (Refer to Register 0h, bits 6 and 7.)
0 = Unlocked
1 = Locked
1
PLL_Lock
PLL Lock Status. (Refer to Register 0h, bits 6 and 7.)
0 = Unlocked
1 = Locked
2 -7
Reserved
13
ICS1524
ICS1524 Rev C 01/31/2003
I
2
C Data Characteristics
Bit transfer on the I
2
C-bus
START and STOP conditions
Acknowledge on the I
2
C-bus
These waveforms are from "The I
2
C-bus and how to use it," published by Philips Semiconductor.
The document can be obtained from http://www-us2.semiconductors.philips.com/acrobat/various/i2c_bus_specification_1995.pdf
ICS1524
14
ICS1524 Rev C 01/31/2003
I
2
C Data Format
RANDOM REGISTER WRITE PROCEDURE
S 0 1 0 0 1 1 x W A
A
A P
7 bit address
register address
data
Acknowledge
Acknowledge
STOP condition
START condition
WRITE command
Acknowledge
RANDOM REGISTER READ PROCEDURE
S 0 1 0 0 1 1 X W A
A S 0 1 0 0 1 1 X R A
A P
7 bit address
register address
7 bit address
data
Acknowledge
Repeat START
Acknowledge
STOP condition
START condition
WRITE command
Acknowledge
READ command
NO Acknowledge
SEQUENTIAL REGISTER WRITE PROCEDURE
S 0 1 0 0 1 1 X W A
A
A
A
A P
7 bit address
register address
data
data
Acknowledge
Acknowledge
Acknowledge
Acknowledge Acknowledge
START condition
WRITE command
STOP condition
SEQUENTIAL REGISTER READ PROCEDURE
S 0 1 0 0 1 1 X W A
A S 0 1 0 0 1 1 X R A
A
A P
7 bit address
register address
7 bit address
data
data
Acknowledge
Repeat START
Acknowledge
NO Acknowledge
START condition
WRITE command
Acknowledge
READ command
Acknowledge STOP condition
Direction:
From bus host to device
From device to bus host
Note:
1. All values are transmitted with the most-significant bit first and the least-significant bit last.
2. The value of the X bit equals the logic state of pin 13 (I
2
CADR).
3. R = READ = 1 and W = WRITE = 0
15
ICS1524
ICS1524 Rev C 01/31/2003
.
Specific Layout Guidelines
1. Digital Supply (VDD) Bypass pin 1 (VDD) to pin 2 (VSS) a 0.1-F capacitor, located as close as possible to the pins. A
0.01-F capacitor may be added for additional high frequency rejection.
2. External Loop Filter Strongly recommended in All Designs. Locate loop filter components as close to pins 8 and 9
(EXTFIL and EXTFILRET) as possible with minimum length traces. Typical loop filter values are 6.8K Ohms for the series
resistor, 3300 pF RF-type capacitor for the series capacitor, and 33 pF for the shunt capacitor. (For details, see the Frequently
Asked Questions part of the ICS1523 Applications Guide, FAQ2 and FAQ3.) A ground isolated, surface trace can be useful to
isolate this section from the rest of the board.
3. Analog PLL Supply (VDDA) Decouple main VDD from pin 10 (VDDA) with a series ferrite bead. Bypass the supply end of
the bead with 4.7-F. Bypass pin 10 to pin 11 (VSSA) with a 0.1-F capacitor. A 0.01-F capacitor may be added for additional
high frequency rejection. Locate these components as close as possible to the pins.
4. PECL Current Set Resistor Locate PECL current-set resistor as close as possible to pin 24 (IREF). Bypass pin 24 to
ground with a 0.1 -F capacitor.
5. PECL Outputs Implement these outputs as microstrip transmission lines. The trace widths shown are for 75 Ohm charac-
teristic impedance. Locate any optional series "snubbing" resistors as close as possible to the source pins. If the termination
resistors are included on-board, locate them as close as possible to the load and connect directly to the power and ground
planes.
[These termination resistors are omitted if the load device implements them internally. For details, see the ICS application
note on microstrip and striplines (1572AN1) and within the ICS1523 Applications Guide, the application note on Designing
a Custom Interface for the ICS1523 (1523AN4.)]
6. Output Driver Supply Bypass pin 18 (VDDQ) to pin 19 (VSSQ) with a 0.1-F capacitor, located as close as possible to the
pins. A 0.01-F capacitor may be added for additional high frequency rejection.
7. SSTL_3 Outputs SSTL_3 outputs can be used like conventional CMOS rail-to-rail logic or as a terminated transmission
line system at higher-output frequencies. With terminated outputs, the considerations of item 5, "PECL Outputs" apply. See
JEDEC documents JESD8-A and JESD8-8.
General Layout Guidelines
Use a PC board with at least four layers: one power, one ground, and two signal.
Use at least one 4.7 uF Tantalum (or similar) capacitor for global VDD bulk decoupling.
All supply voltages must be supplied from a common source and must ramp together.
Any flux or other board surface debris can degrade the performance of the external loop filter.
Ensure that the 1524 area of the board is free of contaminants.
ICS1524
16
ICS1524 Rev C 01/31/2003
PECL Outputs
For information on using the ICS1524's PECL output pins, please refer to Application Note 4: Designing a Custom
PECL Interface for the ICS1523
SSTL_3 Outputs
Unterminated Outputs
In the ICS1524, unterminated SSTL_3 output pins display exponential transitions similar to those of rectangular
pulses presented to RC loads. The 10-90% rise time is typically 1.6 ns, and the corresponding fall time is typically
700 ps. In turn, this asymmetry contributes to duty cycle asymmetry at higher output frequencies. In the absence of
significant load capacitance (which can further increase rise and fall time), this asymmetry is the dominant factor
determining high-frequency performance of these single-ended outputs. Typically, no termination is required either
for the LOCK/REF, FUNC, and CLK/2 outputs or for CLK outputs up to approximately 135 MHz.
Terminated Outputs
SSTL_3 outputs are intended to terminate in low impedances to reduce the effect of external circuit capacitance.
Use of transmission line techniques enables use of longer traces between source and driver without increasing ring-
ing due to reflections. Where external capacitance is minimal and substantial voltage swing is required to meet
LVTTL V
IH
and V
OL
requirements, the intrinsic rise and fall times of ICS1524 SSTL outputs are only slightly improved
by termination in a low impedance.
The ICS1524 SSTL output source impedance is typically less than 60 Ohms. Termination impedance of 100 Ohms
reduces output swing by less than 30% which is more than enough to drive a single load of LVTTL inputs.
For more information on using the ICS1524's SSTL output pins, please refer to Application Note 3: Using SSTL_3
Outputs with CMOS or LVTTL Inputs
ICS1524
VDD
SSTL-3 Output
330
150
Single
LVTTL
Load
17
ICS1524
ICS1524 Rev C 01/31/2003
Absolute Maximum Ratings
VDD, VDDA, VDDQ (measured to VSS) . . . . . . . . . . . . . . . . . . 4.3 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS 0.3 V to 5.5 V
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSSA 0.3 V to VDDA +0.3 V
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSSQ 0.3 V to VDDQ +0.3 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175C
Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
ESD Susceptibility* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 KV
(*Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.)
Power Supply Considerations
The ICS1524 incorporates special internal power-on reset circuitry that requires no external reset signal connection. The sup-
ply voltage (VDD) must remain within the recommended operating conditions during normal operation. To reset the ICS1524,
the supply voltage at the part must be reduced below the threshold voltage (V
th
) of the power-on reset circuit. The supply volt-
age must remain below that threshold voltage such that board power conditioning capacitors are drained and the proper reset
state is latched. The amount of time (t
d
) to hold the voltage in a reset state varies with the design. However, a typical value of
10 ms should be sufficient.
Supply
Voltage
t
d
V = 1.8V
th
V
min
ICS1524
18
ICS1524 Rev C 01/31/2003
Recommended Operating Conditions
VDD, VDDQ, VDDA (measured to VSS) . 3.0 to 3.6 V
Operating Temperature (Ambient) . . . . . . 0 to +70C
t
n
e
r
r
u
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19
ICS1524
ICS1524 Rev C 01/31/2003
VCO Output Frequency and Intrinsic Jitter
0
100
200
300
400
500
600
700
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
VCO Voltage
V
C
O
Fr
equency (
M
H
z
)
0
100
200
300
400
500
600
700
J
i
tte
r (p
s
)
Frequency (Slow: 3.0V @ 70C)
Frequency (Nominal: 3.3V @ 30C)
Frequency (Fast: 3.6V @ 0C)
Jitter (3.0V @ 70C)
Jitter (3.3V @ 30C)
Jitter (3.6V @ 0C)
Frequency
Jitter
Note: Measured with an Externally Forced Filter Voltage
ICS1524
20
ICS1524 Rev C 01/31/2003
DPA Delay-16 Element Resolution
0
2
4
6
8
10
12
14
16
18
20
0
4
8
12
DPA Setting
ns Delay
50 MHz - SVGA @ 72 Hz
157.5 MHz - SXGA @ 85 Hz
DPA Delay - 32 Element Resolution
0
5
10
15
20
25
30
35
40
45
0
4
8
12
16
20
24
28
DPA Setting
ns
De
la
y
25.175 MHz - VGA @ 60 Hz
78.75 MHz - XGA @ 75 Hz
16
DPA Delay - 64 Element Resolution
0
10
20
30
40
50
60
70
80
90
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
DPA Setting
n
s
Delay
12.27 MHz - NTSC
39.8 MHz - SVGA @ 60
32
64
Note:
Maximum number of data points used for this graph.
21
ICS1524
ICS1524 Rev C 01/31/2003
Output T
iming Diagram
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%
*Note: Measured at 3.6V 0C, 135-MHz output frequency, PECL clock lines to 75
termination, SSTL_3 clock lines
unterminated, 20-pF load. Transition times vary based on termination.
Typical Transition Times*
Output Timing*
REF
HSYNC
PECL CLK-
PECL CLK+
SSTL-CLK
FUNC_OUT
t
0
t
R
t
S
t
F
t
5
t
4
t
8
t
9
t
1
t
2
t
3
t
p
PECL DPACLK-
PECL DPACLK+
SSTL-DPACLK
FUNC
t
DPA
t
8
t
9
t
S
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F
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4
t
1
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2
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3
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n
ICS1524
22
ICS1524 Rev C 01/31/2003
24-Pin SOIC (wide body)
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
n
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S
M
4
2
5
1
S
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4
2
5
1
S
C
I
4
2
-
C
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I
S
s
e
b
u
T
T
M
4
2
5
1
S
C
I
M
4
2
5
1
S
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4
2
-
C
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R
d
n
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p
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T
23
ICS1524
ICS1524 Rev C 01/31/2003
NOTES
ICS1524
24
ICS1524 Rev C 01/31/2003
Corporate Headquarters:
2435 Boulevard of the Generals
P.O. Box 968
Valley Forge, PA 19482-0968
Telephone:
610-630-5300
Fax: 610-630-5399
San Jose Operations:
525 Race Street
San Jose, CA 95126-3448
Telephone:
408-297-1201
Fax:
408-925-9460
Web Site:
http://www.icst.com
Integrated Circuit Systems, Inc.