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Электронный компонент: SH7708

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SH7708 Series
SH7708, SH7708S, SH7708R
Hardware Manual
ADE-602-105E
Rev.6.0
5/5/99
Hitachi, Ltd.
Cautions
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patent, copyright, trademark, or other intellectual property rights for information contained in
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contained in this document.
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have received the latest product standards or specifications before final design, purchase or use.
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However, contact Hitachi's sales office before using the product in an application that demands
especially high quality and reliability or where its failure or malfunction may directly threaten
human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power,
combustion control, transportation, traffic, safety equipment or medical equipment for life
support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider
normally foreseeable failure rates or failure modes in semiconductor devices and employ
systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does
not cause bodily injury, fire or other consequential damage due to operation of the Hitachi
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semiconductor products.
Preface
The SH7708, SH7708S, and SH7708R(SH7708 Series) use a RISC (reduced instruction set
computer) type CPU to achieve high-performance computational processing. Also incorporating
the peripheral functions required for system configuration plus power-down features essential for
microcontroller application systems, the SH7708 Series is a new-generation RISC microcontroller
(SuperH RISC engine).
The SH7708 Series have a RISC type instruction set, with basic instructions executed in one
state, offering a drastic improvement in instruction execution speed. It also has an on-chip 32-bit
multiplier (producing a 64-bit result) capable of high-speed multiply-and-accumulate operations.
The SH7708 Series's instructions are upward-compatible with those of the SH-1 and SH-2,
facilitating migration from these series to the SH7708 Series.
SH7708R is completely pin compatible with the SH7708S. On-chip supporting modules that
enable a user system to be configured with a minimum of components include oscillation circuits,
an interrupt controller (INTC), timers, a realtime clock (RTC), and a serial communication
interface (SCI). A user break controller (UBC) is provided as an on-chip module supporting
program development, allowing easy configuration of a simple debugger.
On-chip cache memory improves CPU processing performance, and a built-in memory
management unit (MMU) performs address translation between a 4-gigabyte virtual space and
physical space. An on-chip bus state controller (BSC) provides more efficient external memory
access, and enables direct connection to synchronous DRAM, DRAM, and pseudo-SRAM without
the need for glue logic.
This hardware manual describes the hardware of the SH7708 Series. Details of instructions can be
found in the programming manual.
Related Manuals
SH7708Series instructions
SH-3/SH-3E/SH3-DSP Programming Manual
Please consult your Hitachi sales representative for details of development environment system.
1
Contents
Section 1 Overview and Pin Functions............................................... 1
1.1 SH7708 Series Features ........................................................................................1
1.2 Block Diagram ....................................................................................................6
1.3 Pin Description ...................................................................................................7
1.3.1 Pin Arrangement ......................................................................................7
1.3.2 SH7708 Series Pin Functions.....................................................................8
Section 2 CPU .......................................................................... 13
2.1 Register Configuration..........................................................................................13
2.1.1 Privileged Mode and Banks.........................................................................13
2.1.2 General Registers .....................................................................................16
2.1.3 System Registers .....................................................................................17
2.1.4 Control Registers .....................................................................................17
2.2 Data Formats ......................................................................................................19
2.2.1 Data Format in Registers ...........................................................................19
2.2.2 Data Format in Memory ............................................................................19
2.3 Instruction Features ..............................................................................................20
2.3.1 Execution Environment .............................................................................20
2.3.2 Addressing Modes.....................................................................................22
2.3.3 Instruction Formats ..................................................................................26
2.4 Instruction Set.....................................................................................................29
2.4.1 Instruction Set Classified by Function..........................................................29
2.4.2 Instruction Code Map................................................................................45
2.5 Processor States and Processor Modes......................................................................48
2.5.1 Processor States .......................................................................................48
2.5.2 Processor Modes ......................................................................................49
Section 3 Memory Management Unit (MMU)....................................... 51
3.1 Overview............................................................................................................51
3.1.1 Features..................................................................................................51
3.1.2 Role of MMU .........................................................................................51
3.1.3 SH7708 Series MMU ...............................................................................54
3.1.4 Register Configuration ..............................................................................57
3.2 Register Description .............................................................................................58
3.3 TLB Functions ....................................................................................................60
3.3.1 Configuration of the TLB ..........................................................................60
3.3.2 TLB Indexing ..........................................................................................62
3.3.3 TLB Address Comparison ..........................................................................63
3.3.4 Page Management Information....................................................................65