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Электронный компонент: HN58C256A

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HN58C256A Series
HN58C257A Series
256k EEPROM (32-kword
8-bit)
Ready/
Busy and RES function (HN58C257A)
ADE-203-410D (Z)
Rev. 4.0
Oct. 24, 1997
Description
The Hitachi HN58C256A and HN58C257A are electrically erasable and programmable ROMs organized as
32768-word
8-bit. They have realized high speed low power consumption and high reliability by
employing advanced MNOS memory technology and CMOS process and circuitry technology. They also
have a 64-byte page programming function to make their write operations faster.
Features
Single 5 V supply: 5 V 10%
Access time: 85 ns/100 ns (max)
Power dissipation
Active: 20 mW/MHz, (typ)
Standby: 110 W (max)
On-chip latches: address, data,
CE, OE, WE
Automatic byte write: 10 ms max
Automatic page write (64 bytes): 10 ms max
Ready/
Busy (only the HN58C257A series)
Data polling and Toggle bit
Data protection circuit on power on/off
Conforms to JEDEC byte-wide standard
Reliable CMOS with MNOS cell technology
10
5
erase/write cycles (in page mode)
10 years data retention
Software data protection
Write protection by
RES pin (only the HN58C257A series)
Industrial versions (Temperatur range: 20 to 85C and 40 to 85C) are also available.
HN58C256A Series, HN58C257A Series
2
Ordering Information
Type No.
Access time
Package
HN58C256AP-85
HN58C256AP-10
85 ns
100 ns
600 mil 28-pin plastic DIP (DP-28)
HN58C256AFP-85
HN58C256AFP-10
85 ns
100 ns
400 mil 28-pin plastic SOP (FP-28D)
HN58C256AT-85
HN58C256AT-10
85 ns
100 ns
28-pin plastic TSOP (TFP-28DB)
HN58C257AT-85
HN58C257AT-10
85 ns
100 ns
8
14 mm
2
32-pin plastic TSOP (TFP-32DA)
Pin Arrangement
HN58C256AP/AFP Series
HN58C256AT Series
HN58C257AT Series
(Top view)
(Top view)
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
A3
A4
A5
A6
A7
A12
A14
V
CC
WE
A13
A8
A9
A11
OE
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
A3
A4
A5
A6
A7
A12
A14
V
CC
WE
A13
A8
A9
A11
OE
17
18
19
20
21
22
23
24
25
26
27
28
29
30
16
15
14
13
12
11
10
9
8
7
6
5
4
3
31
32
2
1
NC
NC
RES
RDY/
Busy
HN58C256A Series, HN58C257A Series
3
Pin Description
Pin name
Function
A0 to A14
Address input
I/O0 to I/O7
Data input/output
OE
Output enable
CE
Chip enable
WE
Write enable
V
CC
Power supply
V
SS
Ground
RDY/
Busy
*
1
Ready busy
RES
*
1
Reset
NC
No connection
Note:
1. This function is supported by only the HN58C257A series.
Block Diagram
Note:
This function is supported by only the HN58C257A series.
V
V
OE
CE
A5
A0
A6
A14
WE
CC
SS
I/O0
I/O7
High voltage generator
Control logic and timing
Y decoder
X decoder
Address
buffer and
latch
I/O buffer
and
input latch
Y gating
Memory array
Data latch
RES
RDY/
Busy
RES
*
1
*
1
*
1
to
to
to
HN58C256A Series, HN58C257A Series
4
Operation Table
Operation
CE
OE
WE
RES
*
3
RDY/
Busy
*
3
I/O
Read
V
IL
V
IL
V
IH
V
H
*
1
High-Z
Dout
Standby
V
IH
*
2
High-Z
High-Z
Write
V
IL
V
IH
V
IL
V
H
High-Z to V
OL
Din
Deselect
V
IL
V
IH
V
IH
V
H
High-Z
High-Z
Write inhibit
V
IH
--
--
V
IL
--
--
Data
polling
V
IL
V
IL
V
IH
V
H
V
OL
Dout (I/O7)
Program reset
V
IL
High-Z
High-Z
Notes: 1. Refer to the recommended DC operating condition.
2.
: Don't care
3. This function is supported by only the HN58C257A series.
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage rerative to V
SS
V
CC
0.6 to +7.0
V
Input voltage rerative to V
SS
Vin
0.5*
1
to +7.0*
3
V
Operationg temperature range*
2
Topr
0 to +70
C
Storage temperature range
Tstg
55 to +125
C
Notes: 1. Vin min = 3.0 V for pulse width
50 ns
2. Including electrical characteristics and data retention
3. Should not exceed V
CC
+ 1 V.
HN58C256A Series, HN58C257A Series
5
Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
4.5
5.0
5.5
V
V
SS
0
0
0
V
Input voltage
V
IL
0.3*
1
--
0.8
V
V
IH
2.2
--
V
CC
+ 0.3*
2
V
V
H
*
3
V
CC
0.5
--
V
CC
+ 1.0
V
Operating temperature
Topr
0
--
70
C
Notes: 1. V
IL
min: 1.0 V for pulse width
50 ns.
2. V
IH
max: V
CC
+ 1.0 V for pulse width
50 ns.
3. This function is supported by only the HN58C257A series.
DC Characteristics (Ta = 0 to +70C, V
CC
= 5.0 V10%)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input leakage current
I
LI
--
--
2*
1
A
V
CC
= 5.5 V, Vin = 5.5 V
Output leakage current
I
LO
--
--
2
A
V
CC
= 5.5 V, Vout = 5.5/0.4 V
Standby V
CC
current
I
CC1
--
--
20
A
CE
= V
CC
I
CC2
--
--
1
mA
CE
= V
IH
Operating V
CC
current
I
CC3
--
--
12
mA
Iout = 0 mA, Duty = 100%,
Cycle = 1
s at V
CC
= 5.5 V
--
--
30
mA
Iout = 0 mA, Duty = 100%,
Cycle = 85 ns at V
CC
= 5.5 V
Output low voltage
V
OL
--
--
0.4
V
I
OL
= 2.1 mA
Output high voltage
V
OH
2.4
--
--
V
I
OH
= 400
A
Note:
1. I
LI
on
RES
= 100
A max (only the HN58C257A series)
Capacitance (Ta = +25C, f = 1 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input capacitance*
1
Cin
--
--
6
pF
Vin = 0 V
Output capacitance*
1
Cout
--
--
12
pF
Vout = 0 V
Note:
1. This parameter is periodically sampled and not 100% tested.
HN58C256A Series, HN58C257A Series
6
AC Characteristics (Ta = 0 to +70C, V
CC
= 5 V10%)
Test Conditions
Input pulse levels: 0.4 V to 3.0 V
0 V to V
CC
(
RES pin*
2
)
Input rise and fall time:
5 ns
Input timing reference levels: 0.8, 2.0 V
Output load: 1TTL Gate +100 pF
Output reference levels: 1.5 V, 1.5 V
Read Cycle
HN58C256A/HN58C257A
-85
-10
Parameter
Symbol Min
Max
Min
Max
Unit
Test conditions
Address to output delay
t
ACC
--
85
--
100
ns
CE
=
OE
= V
IL
,
WE
= V
IH
CE
to output delay
t
CE
--
85
--
100
ns
OE
= V
IL
,
WE
= V
IH
OE
to output delay
t
OE
10
40
10
50
ns
CE
= V
IL
,
WE
= V
IH
Address to output hold
t
OH
0
--
0
--
ns
CE
=
OE
= V
IL
,
WE
= V
IH
OE
(
CE
) high to output float*
1
t
DF
0
40
0
40
ns
CE
= V
IL
,
WE
= V
IH
RES
low to output float*
1, 2
t
DFR
0
350
0
350
ns
CE
=
OE
= V
IL
,
WE
= V
IH
RES
to output delay*
2
t
RR
0
450
0
450
ns
CE
=
OE
= V
IL
,
WE
= V
IH
HN58C256A Series, HN58C257A Series
7
Write Cycle
Parameter
Symbol
Min*
3
Typ
Max
Unit
Test conditions
Address setup time
t
AS
0
--
--
ns
Address hold time
t
AH
50
--
--
ns
CE
to write setup time (
WE
controlled)
t
CS
0
--
--
ns
CE
hold time (
WE
controlled)
t
CH
0
--
--
ns
WE
to write setup time (
CE
controlled)
t
WS
0
--
--
ns
WE
hold time (
CE
controlled)
t
WH
0
--
--
ns
OE
to write setup time
t
OES
0
--
--
ns
OE
hold time
t
OEH
0
--
--
ns
Data setup time
t
DS
50
--
--
ns
Data hold time
t
DH
0
--
--
ns
WE
pulse width (
WE
controlled)
t
WP
100
--
--
ns
CE
pulse width (
CE
controlled)
t
CW
100
--
--
ns
Data latch time
t
DL
50
--
--
ns
Byte load cycle
t
BLC
0.2
--
30
s
Byte load window
t
BL
100
--
--
s
Write cycle time
t
WC
--
--
10*
4
ms
Time to device busy
t
DB
120
--
--
ns
Write start time
t
DW
0*
5
--
--
ns
Reset protect time*
2
t
RP
100
--
--
s
Reset high time*
2, 6
t
RES
1
--
--
s
Notes: 1. t
DF
and t
DFR
are defined as the time at which the outputs achieve the open circuit conditions and are
no longer driven.
2. This function is supported by only the HN58C257A series.
3. Use this device in longer cycle than this value.
4. t
WC
must be longer than this value unless polling techniques or RDY/
Busy
(only the HN58C257A
series) are used. This device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after t
DW
if polling techniques or RDY/
Busy
(only the
HN58C257A series) are used.
6. This parameter is sampled and not 100% tested.
7. A6 through A14 are page address and these addresses are latched at the first falling edge of
WE
.
8. A6 through A14 are page address and these addresses are latched at the first falling edge of
CE
.
9. See AC read characteristics.
HN58C256A Series, HN58C257A Series
8
Read Timing Waveform
Address
CE
OE
WE
Data Out
High
Data out valid
t
ACC
t
CE
t
OE
t
OH
t
DF
t
RR
t
DFR
RES
*
2
HN58C256A Series, HN58C257A Series
9
Byte Write Timing Waveform (1) (
WE Controlled)
Address
CE
WE
OE
Din
RDY/
Busy
*
2
t
WC
t
CH
t
AH
t
CS
t
AS
t
WP
t
OEH
t
BL
t
OES
t
DS
t
DH
t
DB
t
RP
RES
*
2
V
CC
t
RES
High-Z
High-Z
t
DW
HN58C256A Series, HN58C257A Series
10
Byte Write Timing Waveform (2) (
CE Controlled)
Address
CE
WE
OE
Din
RDY/
Busy
*
2
t
WC
t
AH
t
WS
t
AS
t
OEH
t
WH
t
OES
t
DS
t
DH
t
DB
t
RP
RES
*
2
V
CC
t
CW
t
BL
t
DW
t
RES
High-Z
High-Z
HN58C256A Series, HN58C257A Series
11
Page Write Timing Waveform (1) (
WE Controlled)
Address
A0 to A14
WE
CE
OE
Din
RDY/
Busy
*
2
t
AS
t
AH
t
BL
t
WC
t
OEH
t
DH
t
DB
t
OES
t
RP
t
RES
RES
*
2
V
CC
t
CH
t
CS
t
WP
t
DL
t
BLC
t
DS
t
DW
High-Z
High-Z
*7
HN58C256A Series, HN58C257A Series
12
Page Write Timing Waveform (2) (
CE Controlled)
Address
A0 to A14
WE
CE
OE
Din
RDY/
Busy
*
2
t
AS
t
AH
t
BL
t
WC
t
OEH
t
DH
t
DB
t
OES
t
RP
t
RES
RES
*
2
V
CC
t
WH
t
WS
t
CW
t
DL
t
BLC
t
DS
t
DW
High-Z
High-Z
*8
HN58C256A Series, HN58C257A Series
13
Data Polling Timing Waveform
t
CE
t
OEH
t
WC
t
DW
t
OES
Address
CE
WE
OE
I/O7
t
OE
Din X
An
An
Dout
X
Dout X
*9
*9
An
HN58C256A Series, HN58C257A Series
14
Toggle bit
This device provide another function to determine the internal programming cycle. If the EEPROM is set to
read mode during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for each read.
When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible
for next read or program.
Toggle bit Waveform
Notes: 1. I/O6 beginning state is "1".
2. I/O6 ending state will vary.
3. See AC read characteristics.
4. Any address location can be used, but the address must be fixed.
WE
t
OES
OE
CE
Dout
I/O6
Dout
Dout
Dout
Next mode
t
OE
t
CE
t
DW
t
WC
t
OEH
*1
*2
*2
Address
*3
*3
*4
Din
HN58C256A Series, HN58C257A Series
15
Software Data Protection Timing Waveform (1) (in protection mode)
V
CE
WE
Address
Data
5555
AA
2AAA
55
5555
A0
t
BLC
t
WC
CC
Write address
Write data
Software Data Protection Timing Waveform (2) (in non-protection mode)
V
CE
WE
Address
Data
t
WC
CC
Normal active
mode
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
20
HN58C256A Series, HN58C257A Series
16
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 s from the preceding falling edge of
WE or CE. When
CE or WE is high for 100 s after data input, the EEPROM enters write mode automatically and the input
data are written into the EEPROM.
Data Polling
Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode
during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is
performing a write operation.
RDY/
Busy Signal (only the HN58C257A series)
RDY/
Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to V
OL
after the first write signal. At the end of a write cycle,
the RDY/
Busy signal changes state to high impedance.
RES Signal (only the HN58C257A series)
When
RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping
RES low when V
CC
is switched.
RES should be high during read and programming because it doesn't provide
a latch function.
V
Program inhibit
CC
RES
Program inhibit
Read inhibit
Read inhibit
HN58C256A Series, HN58C257A Series
17
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of
WE or CE, and data is latched by the rising
edge of
WE or CE.
Write/Erase Endurance and Data Retention Time
The endurance is 10
5
cycles in case of the page programming and 10
4
cycles in case of the byte programming
(1% cumulative failure rate). The data retention time is more than 10 years when a device is page-
programmed less than 10
4
cycles.
Data Protection
1. Data Protection against Noise on Control Pins (
CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake.
To prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns
or less.
Be careful not to allow noise of a width of more than 20 ns on the control pins.
WE
CE
OE
V
0 V
V
0 V
20 ns max
IH
IH
HN58C256A Series, HN58C257A Series
18
2. Data Protection at V
CC
On/Off
When V
CC
is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a
trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the
EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state.
Note:
The EEPROM shoud be kept in unprogrammable state during V
CC
on/off by using CPU RESET
signal.
V
CC
CPU
RESET
Unprogrammable
Unprogrammable
*
*
(1) Protection by
CE, OE, WE
To realize the unprogrammable state, the input level of control pins must be held as shown in the table below.
CE
V
CC
OE
V
SS
WE
V
CC
: Don't care.
V
CC
: Pull-up to V
CC
level.
V
SS
: Pull-down to V
SS
level.
HN58C256A Series, HN58C257A Series
19
(2) Protection by
RES (only the HN58C257A series)
The unprogrammable state can be realized by that the CPU's reset signal inputs directly to the EEPROM's
RES pin. RES should be kept V
SS
level during V
CC
on/off.
The EEPROM breaks off programming operation when
RES becomes low, programming operation doesn't
finish correctly in case that
RES falls low during programming operation. RES should be kept high for 10 ms
after the last data input.
V
CC
RES
WE
or
CE
100
s min
10 ms min
1
s min
Program inhibit
Program inhibit
HN58C256A Series, HN58C257A Series
20
3. Software data protection
To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is
enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is
input. To program data in the SDP enable mode, 3 bytes code must be input before write data.
Data
AA
55
A0
Write data }
Address
5555
2AAA
5555
Write address
Normal data input
The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP
disable cycle, data can not be written.
Data
AA
55
80
AA
55
20
Address
5555
2AAA
5555
5555
2AAA
5555
The software data protection is not enabled at the shipment.
Note:
There are some differences between Hitachi's and other company's for enable/disable sequence of
software data protection. If there are any questions , please contact with Hitachi sales offices.
HN58C256A Series, HN58C257A Series
21
Package Dimensions
HN58C256AP Series (DP-28)
0.51 Min
2.54 Min
0.25
+ 0.11
0.05
2.54
0.25
0.48
0.10
0
15
15.24
1.2
35.6
36.5 Max
13.4
14.6 Max
1
14
15
28
5.70 Max
1.9 Max
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
DP-28
--
Conforms
4.6 g
Unit: mm
HN58C256A Series, HN58C257A Series
22
Package Dimensions (cont.)
HN58C256AFP Series (FP-28D)
0
8
0.17
0.05
1.0
0.2
0.20
0.10
2.50 Max
8.4
18.3
18.8 Max
1.12 Max
28
15
1
14
11.8
0.3
1.7
0.20
0.15
M
1.27
0.40
0.08
0.38
0.06
0.15
0.04
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-28D
Conforms
--
0.7 g
Unit: mm
Dimension including the plating thickness
Base material dimension
HN58C256A Series, HN58C257A Series
23
Package Dimensions (cont.)
HN58C256AT Series (TFP-28DB)
0.10
M
0.55
8.00
0.22
0.08
13.40
0.30
0.17
0.05
0.13
1.20 Max
11.80
0
5
28
1
14
15
8.20 Max
0.10
+0.07 0.08
0.50
0.10
0.80
0.45 Max
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TFP-28DB
--
--
0.23 g
0.20
0.06
0.15
0.04
Unit: mm
Dimension including the plating thickness
Base material dimension
HN58C256A Series, HN58C257A Series
24
Package Dimensions (cont.)
HN58C257AT Series (TFP-32DA)
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TFP-32DA
Conforms
Conforms
0.26 g
0.10
0.08
M
0.50
8.00
0.22
0.08
14.00
0.20
1.20 Max
12.40
32
1
16
17
0.17
0.05
0.13
0.05
0
5
8.20 Max
0.45 Max
0.50
0.10
0.80
0.20
0.06
0.125
0.04
Unit: mm
Dimension including the plating thickness
Base material dimension
HN58C256A Series, HN58C257A Series
25
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