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Электронный компонент: HD74HC292

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HD74HC292/HD74HC294
Programmable Frequency Divider/Digital Timer
Description
This device divides the incoming clock frequency by a number (a power of 2) that is preset by the
Programming inputs. It has two Clock inputs, either of which may be used as a clock inhibit. The device
also has an active-low Reset, which initializes the internal flip-flop states. Test Point outputs (TP1, TP2,
TP3) are provided with HD74HC292 to facilitate incoming inspections.
Test Point output is provided with HD74HC294 to facilitate incoming inspections.
Features
High Speed Operation: t
pd
(Clock to Q) = 16 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 A max
Low Quiescent Supply Current: I
CC
(static) = 4 A max (Ta = 25C)
Function Table
CLR
CLK1
CLK2
Q Output Mode
L
X
X
Cleared to L
H
L
Count
H
L
Count
H
H
X
Inhibit
H
X
H
Inhibit
HD74HC292/HD74HC294
2
HD74HC292
Programming
Inputs
Frequency Division
Q Out
TP1
TP2
TP3
E
D C B
A Binary Decimal
Binary Decimal
Binary Decimal
Binary Decimal
L
L
L
L
L
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
L
L
L
L
H
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
Inhibit
L
L
L
H
L
2
2
4
2
9
512
2
17
131,072
2
24
16,777,216
L
L
L
H
H
2
3
8
2
9
512
2
17
131,072
2
24
16,777,216
L
L
H L
L
2
4
16
2
9
512
2
17
131,072
2
24
16,777,216
L
L
H L
H
2
5
32
2
9
512
2
17
131,072
2
24
16,777,216
L
L
H H
L
2
6
64
2
9
512
2
17
131,072
2
24
16,777,216
L
L
H H
H
2
7
128
2
9
512
2
17
131,072
2
24
16,777,216
L
H L
L
L
2
8
256
2
9
512
2
17
131,072
2
2
4
L
H L
L
H
2
9
512
2
9
512
2
17
131,072
2
2
4
L
H L
H
L
2
10
1,024
2
9
512
2
17
131,072
2
4
16
L
H L
H
H
2
11
2,048
2
9
512
2
17
131,072
2
4
16
L
H H L
L
2
12
4,096
2
9
512
2
17
131,072
2
6
64
L
H H L
H
2
13
8,192
2
9
512
2
17
131,072
2
6
64
L
H H H
L
2
14
16,384
2
9
512
Disabled LOW
2
8
256
L
H H H
H
2
15
32,768
2
9
512
Disabled LOW
2
8
256
H
L
L
L
L
2
16
65,536
2
9
512
2
3
8
2
10
1,024
H
L
L
L
H
2
17
131,072
2
9
512
2
3
8
2
10
1,024
H
L
L
H
L
2
18
262,144
2
9
512
2
5
32
2
12
4,096
H
L
L
H
H
2
19
524,288
2
9
512
2
5
32
2
12
4,096
H
L
H L
L
2
20
1,048,576
2
9
512
2
7
128
2
14
16,384
H
L
H L
H
2
21
2,097,152
2
9
512
2
7
128
2
14
16,384
H
L
H H
L
2
22
4,194,304
Disabled LOW
2
9
512
2
16
65,536
H
L
H H
H
2
23
8,388,608
Disabled LOW
2
9
512
2
16
65,536
H
H L
L
L
2
24
16,777,216
2
3
8
2
11
2,048
2
18
262,144
H
H L
L
H
2
25
33,554,432
2
3
8
2
11
2,048
2
18
262,144
H
H L
H
L
2
26
67,108,864
2
5
32
2
13
8,192
2
20
1,048,576
H
H L
H
H
2
27
134,217,728
2
5
32
2
13
8,192
2
20
1,048,576
H
H H L
L
2
28
268,435,456
2
7
128
2
15
32,768
2
22
4,194,304
H
H H L
H
2
29
536,870,912
2
7
128
2
15
32,768
2
22
4,194,304
H
H H H
L
2
30
1,073,741,824
2
9
512
2
17
131,072
2
24
16,777,216
H
H H H
H
2
31
2,147,483,648
2
9
512
2
17
131,072
2
24
16,777,216
HD74HC292/HD74HC294
3
HD74HC294
Programming Inputs
Frequency Division
Q Output
TP Output
D
C
B
A
Binary
Decimal
Binary
Decimal
L
L
L
L
Inhibit
Inhibit
Inhibit
Inhibit
L
L
L
H
Inhibit
Inhibit
Inhibit
Inhibit
L
L
H
L
2
2
4
2
9
512
L
L
H
H
2
3
8
2
9
512
L
H
L
L
2
4
16
2
9
512
L
H
L
H
2
5
32
2
9
512
L
H
H
L
2
6
64
2
9
512
L
H
H
H
2
7
128
Disabled LOW
H
L
L
L
2
8
256
2
2
4
H
L
L
H
2
9
512
2
3
8
H
L
H
L
2
10
1,024
2
4
16
H
L
H
H
2
11
2,048
2
5
32
H
H
L
L
2
12
4,096
2
6
64
H
H
L
H
2
13
8,192
2
7
128
H
H
H
L
2
14
16,384
2
8
256
H
H
H
H
2
15
32,768
2
9
512
HD74HC292/HD74HC294
4
Pin Arrangement
HD74HC292
1
2
3
4
5
6
7
8
B
E
TP1
CLK1
CLK2
TP2
Q
GND
V
CC
C
D
TP3
NC
CLR
A
NC
16
15
14
13
12
11
10
9
(Top view)
HD74HC294
1
2
3
4
5
6
7
8
B
A
TP
CLK1
CLK2
NC
Q
GND
V
CC
C
D
NC
NC
CLR
NC
NC
16
15
14
13
12
11
10
9
(Top view)
HD74HC292/HD74HC294
5
Logic Diagram
HD74HC292
R
R
R
D
D
D
MC
CK
R
R
R
R
D
D
D
MC
CK
R
R
D
D
D
MC
CK
R
D
R
D
MC
CK
R
R
CK
R
R
R
D
D
R
R
TP
1
TP
2
TP
3
Q
A
CLR
CLK1
CLK2
E
D
C
B
6
8
4
2
0
1
14
13
12
11
10
9
8
7
6
5
4
3
2