Document Outline

Cover
Cautions
List of Items Revised or Added for This Version
Preface
Contents
Section 1 Overview
- 1.1 Overview
- 1.2 Internal Block Diagram
- 1.3 Pin Arrangement and Functions
  - 1.3.1 Pin Arrangement
  - 1.3.2 Pin Functions
Section 2 CPU
- 2.1 Overview
  - 2.1.1 Features
  - 2.1.2 Address Space
  - 2.1.3 Register Configuration
- 2.2 Register Descriptions
  - 2.2.1 General Registers
  - 2.2.2 Control Registers
  - 2.2.3 Initial Register Values
- 2.3 Data Formats
  - 2.3.1 Data Formats in General Registers
  - 2.3.2 Memory Data Formats
- 2.4 Addressing Modes
  - 2.4.1 Addressing Modes
  - 2.4.2 Effective Address Calculation
- 2.5 Instruction Set
  - 2.5.1 Data Transfer Instructions
  - 2.5.2 Arithmetic Operations
  - 2.5.3 Logic Operations
  - 2.5.4 Shift Operations
  - 2.5.5 Bit Manipulations
  - 2.5.6 Branching Instructions
  - 2.5.7 System Control Instructions
  - 2.5.8 Block Data Transfer Instruction
- 2.6 Basic Operational Timing
  - 2.6.1 Access to On-Chip Memory (RAM, ROM)
  - 2.6.2 Access to On-Chip Peripheral Modules
- 2.7 CPU States
  - 2.7.1 Overview
  - 2.7.2 Program Execution State
  - 2.7.3 Program Halt State
  - 2.7.4 Exception-Handling State
- 2.8 Memory Map
  - 2.8.1 Memory Map
- 2.9 Application Notes
  - 2.9.1 Notes on Data Access
  - 2.9.2 Notes on Bit Manipulation
  - 2.9.3 Notes on Use of the EEPMOV Instruction
Section 3 Exception Handling
- 3.1 Overview
- 3.2 Reset
  - 3.2.1 Overview
  - 3.2.2 Reset Sequence
  - 3.2.3 Interrupt Immediately after Reset
- 3.2.3 Interrupt Immediately after Reset
- 3.3 Interrupts
  - 3.3.1 Overview
  - 3.3.2 Interrupt Control Registers
  - 3.3.3 External Interrupts
  - 3.3.4 Internal Interrupts
  - 3.3.5 Interrupt Operations
  - 3.3.6 Interrupt Response Time
- 3.4 Application Notes
  - 3.4.1 Notes on Stack Area Use
  - 3.4.2 Notes on Rewriting Port Mode Registers
  - 3.4.3 Interrupt Request Flag Clearing Method
Section 4 Clock Pulse Generators
- 4.1 Overview
  - 4.1.1 Block Diagram
  - 4.1.2 System Clock and Subclock
- 4.2 System Clock Generator
- 4.3 Subclock Generator
- 4.4 Prescalers
- 4.5 Note on Oscillators
  - 4.5.1 Definition of Oscillation Settling Standby Time
  - 4.5.2 Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
Section 5 Power-Down Modes
- 5.1 Overview
  - 5.1.1 System Control Registers
- 5.2 Sleep Mode
  - 5.2.1 Transition to Sleep Mode
  - 5.2.2 Clearing Sleep Mode
  - 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode
- 5.3 Standby Mode
  - 5.3.1 Transition to Standby Mode
  - 5.3.2 Clearing Standby Mode
  - 5.3.3 Oscillator Settling Time after Standby Mode is Cleared
  - 5.3.4 Standby Mode Transition and Pin States
  - 5.3.5 Notes on External Input Signal Changes before/after Standby Mode
- 5.4 Watch Mode
  - 5.4.1 Transition to Watch Mode
  - 5.4.2 Clearing Watch Mode
  - 5.4.3 Oscillator Settling Time after Watch Mode is Cleared
  - 5.4.4 Notes on External Input Signal Changes before/after Watch Mode
- 5.5 Subsleep Mode
  - 5.5.1 Transition to Subsleep Mode
  - 5.5.2 Clearing Subsleep Mode
- 5.6 Subactive Mode
  - 5.6.1 Transition to Subactive Mode
  - 5.6.2 Clearing Subactive Mode
  - 5.6.3 Operating Frequency in Subactive Mode
- 5.7 Active (Medium-Speed) Mode
  - 5.7.1 Transition to Active (Medium-Speed) Mode
  - 5.7.2 Clearing Active (Medium-Speed) Mode
  - 5.7.3 Operating Frequency in Active (Medium-Speed) Mode
- 5.8 Direct Transfer
  - 5.8.1 Overview of Direct Transfer
  - 5.8.2 Direct Transition Times
  - 5.8.3 Notes on External Input Signal Changes before/after Direct Transition
- 5.9 Module Standby Mode
  - 5.9.1 Setting Module Standby Mode
  - 5.9.2 Clearing Module Standby Mode
Section 6 ROM
- 6.1 Overview
  - 6.1.1 Block Diagram
- 6.2 H8/3802 PROM Mode
  - 6.2.1 Setting to PROM Mode
  - 6.2.2 Socket Adapter Pin Arrangement and Memory Map
- 6.3 H8/3802 Programming
  - 6.3.1 Writing and Verifying
  - 6.3.2 Programming Precautions
- 6.4 Reliability of Programmed Data
Section 7 RAM
- 7.1 Overview
  - 7.1.1 Block Diagram
Section 8 I/O Ports
- 8.1 Overview
- 8.2 Port 3
  - 8.2.1 Overview
  - 8.2.2 Register Configuration and Description
  - 8.2.3 Pin Functions
  - 8.2.4 Pin States
  - 8.2.5 MOS Input Pull-Up
- 8.3 Port 4
  - 8.3.1 Overview
  - 8.3.2 Register Configuration and Description
  - 8.3.3 Pin Functions
  - 8.3.4 Pin States
- 8.4 Port 5
  - 8.4.1 Overview
  - 8.4.2 Register Configuration and Description
  - 8.4.3 Pin Functions
  - 8.4.4 Pin States
  - 8.4.5 MOS Input Pull-Up
- 8.5 Port 6
  - 8.5.1 Overview
  - 8.5.2 Register Configuration and Description
  - 8.5.3 Pin Functions
  - 8.5.4 Pin States
  - 8.5.5 MOS Input Pull-Up
- 8.6 Port 7
  - 8.6.1 Overview
  - 8.6.2 Register Configuration and Description
  - 8.6.3 Pin Functions
  - 8.6.4 Pin States
- 8.7 Port 8
  - 8.7.1 Overview
  - 8.7.2 Register Configuration and Description
  - 8.7.3 Pin Functions
  - 8.7.4 Pin States
- 8.8 Port 9
  - 8.8.1 Overview
  - 8.8.2 Register Configuration and Description
  - 8.8.3 Pin Functions
  - 8.8.4 Pin States
- 8.9 Port A
  - 8.9.1 Overview
  - 8.9.2 Register Configuration and Description
  - 8.9.3 Pin Functions
  - 8.9.4 Pin States
- 8.10 Port B
  - 8.10.1 Overview
  - 8.10.2 Register Configuration and Description
  - 8.10.3 Pin Functions
- 8.11 Input/Output Data Inversion Function
  - 8.11.1 Overview
  - 8.11.2 Register Configuration and Descriptions
  - 8.11.3 Note on Modification of Serial Port Control Register
- 8.12 Application Note
  - 8.12.1 How to Handle an Unused Pin
Section 9 Timers
- 9.1 Overview
- 9.2 Timer A
  - 9.2.1 Overview
  - 9.2.2 Register Descriptions
  - 9.2.3 Timer Operation
  - 9.2.4 Timer A Operation States
  - 9.2.5 Application Note
- 9.3 Timer F
  - 9.3.1 Overview
  - 9.3.2 Register Descriptions
  - 9.3.3 CPU Interface
  - 9.3.4 Operation
  - 9.3.5 Application Notes
- 9.4 Asynchronous Event Counter (AEC)
  - 9.4.1 Overview
  - 9.4.2 Register Configurations
  - 9.4.3 Operation
  - 9.4.4 Asynchronous Event Counter Operation Modes
  - 9.4.5 Application Notes
Section 10 Serial Communication Interface
- 10.1 Overview
  - 10.1.1 Features
  - 10.1.2 Block diagram
  - 10.1.3 Pin configuration
  - 10.1.4 Register configuration
- 10.2 Register Descriptions
  - 10.2.1 Receive shift register (RSR)
  - 10.2.2 Receive data register (RDR)
  - 10.2.3 Transmit shift register (TSR)
  - 10.2.4 Transmit data register (TDR)
  - 10.2.5 Serial mode register (SMR)
  - 10.2.6 Serial control register 3 (SCR3)
  - 10.2.7 Serial status register (SSR)
  - 10.2.8 Bit rate register (BRR)
  - 10.2.9 Clock stop register 1 (CKSTPR1)
  - 10.2.10 Serial Port Control Register (SPCR)
- 10.3 Operation
  - 10.3.1 Overview
  - 10.3.2 Operation in Asynchronous Mode
  - 10.3.3 Operation in Synchronous Mode
  - 10.3.4 Multiprocessor Communication Function
- 10.4 Interrupts
- 10.5 Application Notes
Section 11 10-Bit PWM
- 11.1 Overview
  - 11.1.1 Features
  - 11.1.2 Block Diagram
  - 11.1.3 Pin Configuration
  - 11.1.4 Register Configuration
- 11.2 Register Descriptions
  - 11.2.1 PWM Control Register (PWCRm)
  - 11.2.2 PWM Data Registers U and L (PWDRUm, PWDRLm)
  - 11.2.3 Clock Stop Register 2 (CKSTPR2)
- 11.3 Operation
  - 11.3.1 Operation
  - 11.3.2 PWM Operation Modes
Section 12 A/D Converter
- 12.1 Overview
  - 12.1.1 Features
  - 12.1.2 Block Diagram
  - 12.1.3 Pin Configuration
  - 12.1.4 Register Configuration
- 12.2 Register Descriptions
  - 12.2.1 A/D Result Registers (ADRRH, ADRRL)
  - 12.2.2 A/D Mode Register (AMR)
  - 12.2.3 A/D Start Register (ADSR)
  - 12.2.4 Clock Stop Register 1 (CKSTPR1)
- 12.3 Operation
  - 12.3.1 A/D Conversion Operation
  - 12.3.2 A/D Converter Operation Modes
- 12.4 Interrupts
- 12.5 Typical Use
- 12.6 Application Notes
Section 13 LCD Controller/Driver
- 13.1 Overview
  - 13.1.1 Features
  - 13.1.2 Block Diagram
  - 13.1.3 Pin Configuration
  - 13.1.4 Register Configuration
- 13.2 Register Descriptions
  - 13.2.1 LCD Port Control Register (LPCR)
  - 13.2.2 LCD Control Register (LCR)
  - 13.2.3 LCD Control Register 2 (LCR2)
  - 13.2.4 Clock Stop Register 2 (CKSTPR2)
- 13.3 Operation
  - 13.3.1 Settings up to LCD Display
  - 13.3.2 Relationship between LCD RAM and Display
  - 13.3.3 Operation in Power-Down Modes
  - 13.3.4 Boosting the LCD Drive Power Supply
Section 14 Electrical Characteristics
- 14.1 H8/3802 Series Absolute Maximum Ratings
- 14.2 H8/3802 Series Electrical Characteristics
  - 14.2.1 Power Supply Voltage and Operating Range
  - 14.2.2 DC Characteristics
  - 14.2.3 AC Characteristics
  - 14.2.4 A/D Converter Characteristics
  - 14.2.5 LCD Characteristics
- 14.3 Operation Timing
- 14.4 Output Load Circuit
- 14.5 Resonator Equivalent Circuit
- 14.6 Usage Note
Appendix A CPU Instruction Set
- A.1 Instructions
- A.2 Operation Code Map
- A.3 Number of Execution States
Appendix B Internal I/O Registers
- B.1 Addresses
- B.2 Functions
Appendix C I/O Port Block Diagrams
- C.1 Block Diagrams of Port 3
- C.2 Block Diagrams of Port 4
- C.3 Block Diagram of Port 5
- C.4 Block Diagram of Port 6
- C.5 Block Diagram of Port 7
- C.6 Block Diagrams of Port 8
- C.7 Block Diagrams of Port 9
- C.8 Block Diagram of Port A
- C.9 Block Diagram of Port B
Appendix D Port States in the Different Processing States
Appendix E List of Product Codes
Appendix F Package Dimensions
Colophon

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's

patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party's
rights, including intellectual property rights, in connection with use of the information
contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or
use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi's sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi

semiconductor products.

Section

Page

Item

Description

5.5.2 Clearing
Subsleep Mode

108

� Clearing by interrupt

Description amended

5.6 Subactive Mode

109

5.6.1 Transition to Subactive Mode Description amended

6.3.1 Writing and
Verifying

122

Figure 6.4 High-Speed,High-
Reliability Programming Flow Chart

Write time t

OPW

amended

8.1 Overview

131, 132

Table 8.1 Port Functions

Other function of port 3
and description of port 9
amended

8.2.2 Register
Configuration and
Description

133

Table 8.2 Port 3 Registers

Amended and register
added

134

1. Port data register 3 (PDR3)

Bit 0 and description
amended

2. Port control register 3 (PCR3)

Bit 0 and description
amended

3. Port pull-up control register 3
(PUCR3)

Bit 0 and description
amended

135, 136

4. Port mode register 3 (PMR3)

Bits 5 to 3 and 0, and
description amended

136

5. Port mode register 2 (PMR2)

Added

8.3.2 Register
Configuration and
Description

139

Table 8.5 Port 4 Register

Initial value amended

140, 141

3. Port mode register 2 (PMR2)

Bits 2 and 1, and
description amended

8.3.3 Pin Functions

141

Table 8.6 Port 4 Pin Functions

Description amended

8.7.2 Register
Configuration and
Description

155

Table 8.17 Port 8 Registers

Initial value amended

156

1. Port data register 8 (PDR8)

Bits 7 to 1 amended

2. Port control register 8 (PCR8)

Bits 7 to 1 amended

8.8 Port 9

158

8.8.1 Overview

Description amended

8.8.2 Register
Configuration and
Description

Table 8.20 Port 9 Registers

Initial value amended

159

2. Port mode register 9 (PMR9)

Bit 2 amended, description
added, and Note changed

8.10.2 Register
Configuration and
Description

165

Table 8.26 Port B Register

Initial values added

Section

Page

Item

Description

8.11.2 Register
Configuration and
Descriptions

168, 169

Serial Port Control Register
(SPCR)

Bits 4, 1, and 0, and
description amended

8.12 Application Note

170

8.12.1 How to Handle an Unused
Pin

Description added

9.1 Overview

171

Table 9.1 Timer Functions

Internal clock of
asynchronous event
counter amended

9.2.1 Overview

174

Table 9.2 Timer A Registers

Initial value amended

9.2.2 Register
Descriptions

174

1. Timer mode register A (TMA)

Bits 7 to 5 amended

9.2.5 Application Note

178

9.2.5 Application Note

Description added

9.3.4 Operation

192

1. Timer F operation

a. Operation in 16-bit timer mode

Description amended

9.3.5 Application Note

196, 197

3. Clear timer FH, timer FL
interrupt request flags (IRRTFH,
IRRTFL), timer overflow flags H, L
(OVFH, OVFL) and compare match
flags H, L (CMFH, CMFL)

4. Timer counter (TCF) read/write

Description added

9.4.2 Register
Configurations

202

5. Input pin edge selection register
(AEGSR)

Bit name amended

204

6. Event counter control register
(ECCR)

Bit name, R/W form, and
description amended

205

7. Event counter control/status
register (ECCSR)

Bit name, R/W form, and
description amended

10.1.4 Register
Configuration

220

Table 10.2 Registers

Initial value of serial port
control register amended

10.2 Register
Descriptions

227

10.2.6 Serial control register 3
(SCR3)

Description of bit 5
amended

240

10.2.10 Serial Port Control
Register (SPCR)

Bits 4, 1, and 0, and
description amended

12.2 Register
Descriptions

286, 287

12.2.2 A/D Mode Register (AMR)

Bit 6 amended

12.6 Application Notes 294

12.6 Application Notes

4th note added

13.1.4 Register
Configuration

297

Table 13.2 LCD Controller/Driver
Registers

Initial values amended

Электронный компонент: HD6433800

Document Outline