HD151012
8-bit Binary Programmable Counter with Synchronous Preset
Enable
ADE-205-132 (Z)
Preliminary
1st. Edition
Mar. 1996
Description
The HD151012 has 8-bit binary down counter and D-type Flip Flop. The counter can set up to max 256
counts and synchronous preset (
SPE) input can preset the data. When the count value is 0, the next clock
pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose
data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid crystal
and general-use divider.
Features
High speed operation
tpd (CLK or
CLK to Q) = 35 ns (typ)
High output current
Fanout of 10 LS TTL Loads
Wide operating voltage
V
CC
= 2 to 6 V
Low supply current (Ta = 25C)
I
CC
(Static) = 4 A (max)
HD151012
2
Function Table
Control Inputs
CLR
PR
SPE
Mode
Operation Description
H
H
H
Generally count
Down count at the rise edge of clock (CLK)
Down count at the fall edge of clock (CLK)
X
X
L
Synchronous preset
Jn data is preset at the rise of clock (CLK), the fall
of clock (CLK)
L
H
--
Initialize of Q output
Initialize of Q = "L"
H
L
--
Initialize of Q output
Initialize of Q = "H"
Notes: 1. Synchronous preset (
SPE
) input can set max 256 down counts.
2. When the count value is 0, the next clock pulse presets the data to invert the output.
3. CLR and PR inputs initialize output state.
H :
High level
L
:
Low level
X :
Immaterial
-- :
Irrespective of condition
Pin Arrangement
11
12
13
14
V
CC
1
2
3
4
5
6
7
10
GND
(Top view)
8
9
15
16
J 0
J 1
J 2
J 3
J 4
J 5
J 6
CLK
CLK
Q
PR
SPE
CLR
J 7
HD151012
3
Pin Description
Pin Name
Pin Description
Input pins
J0 to J7
Count data input for option
CLK,
CLK
Clock inputs
CLK : Rise edge trigger
CLK
: Fall edge trigger
SPE
Preset input for Jn data
PR
Preset input for D-type Flip Flop (Initialize "L" at Q output)
CLR
Clear input for D-type Flip Flop (Initialize "H" at Q output)
Output pins
Q
Output for D-type Flip Flop
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
V
CC
0.5 to 7.0
V
Input / output voltage
V
IN
/V
OUT
0.5 to V
CC
+0.5
V
VCC, GND current
I
CC
, IGND
50
mA
Output current / pin
I
OUT
25
mA
Power dissipation
P
T
500
mW
Storage temperature
Tstg
65 to 150
C
Input diode current
I
IK
20
mA
Output diode current
I
OK
20
mA
Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
2. All voltage values except for differential input voltage are with respect to network ground
terminal.
HD151012
4
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
2
--
6
V
Input/output voltage
V
IN
/
OUT
0
--
V
CC
V
Operating temperature
Topr
40
--
+85
C
Input rise/fall time*
1
V
CC
= 2.5 V
t
r
, t
f
0
--
1000
ns
V
CC
= 4.5 V
0
--
500
V
CC
= 5.5 V
0
--
400
Note:
1. This item guarantees maximum limit when one input switches.
Logic Diagram
CLK
CLK
CLK
8-bit binary counter
SPE
PR
CLR
PR
D
CK
Q
Q
CLR
Q
CO
SPE
J0
J0
J1
J1
J2
J2
J3
J3
J4
J4
J5
J5
J6
J6
J7
J7
HD151012
5
Electrical Characteristics
Ta = 25
C
Ta =
40 to 85
C
Item
Symbol
V
CC
Min
Typ
Max
Min
Max
Unit
Test Conditions
High level input
V
IH
2.0
1.5
--
--
1.5
--
V
J0 to J7
voltage
4.5
3.15
--
--
3.15
--
SPE
6.0
4.2
--
--
4.2
--
PR, CLR
2.0
1.5
--
--
1.5
--
CLK
, CLK
4.5
3.15
--
--
3.15
--
6.0
4.2
--
--
4.2
--
Low level input
V
IL
2.0
--
--
0.5
--
0.5
V
J0 to J7
voltage
4.5
--
--
1.35
--
1.35
SPE
6.0
--
--
1.8
--
1.8
PR, CLR
2.0
--
--
0.5
--
0.5
CLK
, CLK
4.5
--
--
1.35
--
1.35
6.0
--
--
1.8
--
1.8
High level output
V
OH
2.0
1.9
2.0
--
1.9
--
V
V
IN
=
I
OH
= 20 mA
voltage
4.5
4.4
4.5
--
4.4
--
V
IH
or V
IL
6.0
5.9
6.0
--
5.9
--
4.5
4.18
4.31
--
4.13
--
I
OH
= 4 mA
6.0
5.68
5.80
--
5.63
--
I
OH
= 5.2 mA
Low level output
V
OL
2.0
--
0.0
0.1
--
0.1
V
V
IN
=
I
OL
= 20 mA
voltage
4.5
--
0.0
0.1
--
0.1
V
IH
or V
IL
6.0
--
0.0
0.1
--
0.1
4.5
--
0.17
0.26
--
0.33
I
OL
= 4 mA
6.0
--
0.18
0.26
--
0.33
I
OL
= 5.2 mA
Input capacitance
I
IN
6.0
--
--
0.1
--
1.0
mA
V
IN
= V
CC
or GND
Supply current
I
CC
6.0
--
--
4.0
--
40.0
mA
V
IN
= V
CC
or GND
PDF 
ZIP