S E M I C O N D U C T O R
8-49
August 1997
ICL232
+5V Powered, Dual RS-232 Transmitter/Receiver
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1997
File Number
3020.5
Features
Meets All RS-232C and V.28 Specifications
Requires Only Single +5V Power Supply
Onboard Voltage Doubler/Inverter
Low Power Consumption
2 Drivers
-
9V Output Swing for +5V lnput
- 300
Power-off Source Impedance
- Output Current Limiting
- TTL/CMOS Compatible
- 30V/
s Maximum Slew Rate
2 Receivers
-
30V Input Voltage Range
- 3k
to 7k
Input Impedance
- 0.5V Hysteresis to Improve Noise Rejection
All Critical Parameters are Guaranteed Over the Entire
Commercial, Industrial and Military Temperature Ranges
Applications
Any System Requiring RS-232 Communications Port
- Computer - Portable and Mainframe
- Peripheral - Printers and Terminals
- Portable Instrumentation
- Modems
Dataloggers
Description
The ICL232 is a dual RS-232 transmitter/receiver interface
circuit that meets all ElA RS-232C and V.28 specifications. It
requires a single +5V power supply, and features two
onboard charge pump voltage converters which generate
+10V and -10V supplies from the 5V supply.
The drivers feature true TTL/CMOS input compatibility, slew-
rate-limited output, and 300
power-off source impedance.
The receivers can handle up to +30V, and have a 3k
to 7k
input impedance. The receivers also have hysteresis to
improve noise rejection.
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
ICL232CPE
0 to 70
16 Ld PDIP
E16.3
ICL232CBE
0 to 70
16 Ld SOIC
M16.3
ICL232lPE
-40 to 85
16 Ld PDIP
E16.3
ICL232lJE
-40 to 85
16 Ld CERDIP
F16.3
ICL232lBE
-40 to 85
16 Ld SOIC
M16.3
ICL232MJE
-55 to 125
16 Ld CERDIP
F16.3
Pinout
ICL232 (PDIP, CERDIP, SOIC)
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
C1+
V+
C1-
C2+
C2-
V-
R2
IN
T2
OUT
V
CC
T1
OUT
R1
IN
R1
OUT
T1
IN
T2
IN
R2
OUT
GND
+5V
2
16
T1
OUT
T2
OUT
T1
IN
T2
IN
11
10
14
7
R1
OUT
R1
IN
13
12
R2
OUT
R2
IN
8
9
1
F
6
+
1
F
4
5
+
1
F
1
3
+
1
F
+
+
1.0
F
15
V
CC
V+
T1
T2
+5V
400k
+5V
400k
R1
5k
R2
5k
+10V TO -10V
VOLTAGE INVERTER
V-
C2+
C2-
+5V TO 10V
VOLTAGE INVERTER
C1+
C1-
8-50
Absolute Maximum Ratings
Thermal Information
V
CC
to Ground . . . . . . . . . . . . . . . . . . . . . .(GND -0.3V) < V
CC
< 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . (V
CC
-0.3V) < V+ < 12V
V- to Ground . . . . . . . . . . . . . . . . . . . . . . . -12V < V- < (GND +0.3V)
Input Voltages
T1
IN
, T2
IN
. . . . . . . . . . . . . . . . . . . . (V- -0.3V) < V
IN
< (V+ +0.3V)
R1
IN
, R2
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30V
Output Voltages
T1
OUT
, T2
OUT
. . . . . . . . . . . . (V- -0.3V) < V
TXOUT
< (V+ +0.3V)
R1
OUT
, R2
OUT
. . . . . . . . .(GND -0.3V) < V
RXOUT
< (V
CC
+0.3V)
Short Circuit Duration
T1
OUT
, T2
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
R1
OUT
, R2
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Operating Conditions
Temperature Ranges
ICL232C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to 70
o
C
ICL232I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
ICL232M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
JC
(
o
C/W)
CERDIP Package . . . . . . . . . . . . . . . .
80
18
PDIP Package . . . . . . . . . . . . . . . . . . .
100
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
100
N/A
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Test Conditions: V
CC
= +5V
10%, T
A
= Operating Temperature Range. Test Circuit as in Figure 8
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Transmitter Output Voltage Swing, T
OUT
T1
OUT
and T2
OUT
Loaded with 3k
to Ground
5
9
10
V
Power Supply Current, I
CC
Outputs Unloaded, T
A
= 25
o
C
-
5
10
mA
T
IN
, Input Logic Low, V
lL
-
-
0.8
V
T
IN
, Input Logic High, V
lH
2.0
-
-
V
Logic Pullup Current, I
P
T1
IN
, T2
IN
= 0V
-
15
200
A
RS-232 Input Voltage Range, V
IN
-30
-
+30
V
Receiver Input Impedance, R
IN
V
IN
=
3V
3.0
5.0
7.0
k
Receiver Input Low Threshold, V
lN
(H-L)
V
CC
= 5V, T
A
= 25
o
C
0.8
1.2
-
V
Receiver Input High Threshold, V
IN
(L-H)
V
CC
= 5V, T
A
= 25
o
C
-
1.7
2.4
V
Receiver Input Hysteresis, V
HYST
0.2
0.5
1.0
V
TTL/CMOS Receiver Output Voltage Low, V
OL
I
OUT
= 3.2mA
-
0.1
0.4
V
TTL/CMOS Receiver Output Voltage High, V
OH
I
OUT
= -1.0mA
3.5
4.6
-
V
Propagation Delay, t
PD
RS-232 to TTL
-
0.5
-
s
Instantaneous Slew Rate, SR
C
L
= 10pF, R
L
= 3k
, T
A
= 25
o
C
(Notes 2, 3)
-
-
30
V/
s
Transition Region Slew Rate, SR
T
R
L
= 3k
, C
L
= 2500pF Measured
from +3V to -3V or -3V to +3V
-
3
-
V/
s
Output Resistance, R
OUT
V
CC
= V+ = V- = 0V, V
OUT
=
2V
300
-
-
RS-232 Output Short Circuit Current, I
SC
T1
OUT
or T2
OUT
Shorted to GND
-
10
-
mA
NOTES:
2. Guaranteed by design.
3. See Figure 4 for definition.
ICL232
8-51
Test Circuits
FIGURE 1. GENERAL TEST CIRCUIT
FIGURE 2. POWER-OFF SOURCE RESISTANCE
CONFIGURATION
Typical Performance Curves
FIGURE 3. V+, V- OUTPUT IMPEDANCES vs V
CC
FIGURE 4. V+, V- OUTPUT VOLTAGES vs LOAD CURRENT
Pin Descriptions
PDIP, CERDIP
SOIC
PIN NAME
DESCRIPTION
1
1
C1+
External capacitor "+" for internal voltage doubler.
2
2
V+
Internally generated +10V (typical) supply.
3
3
C1-
External capacitor "-" for internal voltage doubler.
4
4
C2+
External capacitor "+" internal voltage inverter.
5
5
C2-
External capacitor "-" internal voltage inverter.
6
6
V-
Internally generated -10V (typical) supply.
7
7
T2
OUT
RS-232 Transmitter 2 output
10V (typical).
8
8
R2
IN
RS-232 Receiver 2 input, with internal 5K pulldown resistor to GND.
9
9
R2out
Receiver 2 TTL/CMOS output.
10
10
T2
IN
Transmitter 2 TTL/CMOS input, with internal 400K pullup resistor to V
CC
.
11
11
T1
IN
Transmitter 1 TTL/CMOS input, with internal 400K pullup resistor to V
CC
.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
C1+
V+
C1-
C2+
C2-
V-
R2
IN
T2
OUT
V
CC
T1
OUT
R1
IN
R1
OUT
T1
IN
T2
IN
R2
OUT
GND
+4.5V TO
+5.5V INPUT
3k
T1 OUTPUT
RS-232
30V INPUT
TTL/CMOS
OUTPUT
TTL/CMOS
INPUT
TTL/CMOS
INPUT
TTL/CMOS
OUTPUT
+
-
1
F
C3
+
-
1
F
C1
+
-
1
F
C2
+
-
1
F C4
3k
T2 OUTPUT
RS-232
30V INPUT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
C1+
V+
C1-
C2+
C2-
V-
R2
IN
T2
OUT
V
CC
T1
OUT
R1
IN
R1
OUT
T1
IN
T2
IN
R2
OUT
GND
T2
OUT
T1
OUT
V
IN
=
2V
A
R
OUT
= V
IN
/I
550
500
450
400
350
300
250
200
150
3
4
5
6
INPUT SUPPLY VOLTAGE V
CC
(V)
V- SUPPLY
V+ SUPPLY
OPERATING
RANGE
GUARANTEED
T
A
= 25
o
C
EXTERNAL SUPPLY LOAD
1k
BETWEEN V+ + GND
OR V- + GND
TRANSMITTER OUTPUT
OPEN CIRCUIT
V+, V
-
SUPPL
Y IMPED
ANCES (
)
10
|I
LOAD
| (mA)
V+ (V
CC
= 4.5V)
V+ (V
CC
= 5V)
V- (V
CC
= 5V)
V- (V
CC
= 4.5V)
T
A
= 25
o
C
TRANSMITTER OUTPUTS
OPEN CIRCUIT
9
8
7
6
5
4
3
2
1
0
OUTPUT V
O
L
T
A
GE (|
V
|
)
3
10
9
8
7
6
5
4
ICL232
8-52
Detailed Description
The ICL232 is a dual RS-232 transmitter/receiver powered by
a single +5V power supply which meets all ElA RS232C spec-
ifications and features low power consumption. The functional
diagram illustrates the major elements of the ICL232. The cir-
cuit is divided into three sections: a voltage doubler/inverter,
dual transmitters, and dual receivers Voltage Converter.
An equivalent circuit of the dual charge pump is illustrated in
Figure 5.
The voltage quadrupler contains two charge pumps which use
two phases of an internally generated clock to generate +10V
and -10V. The nominal clock frequency is 16kHz. During
phase one of the clock, capacitor C1 is charged to V
CC
.
During phase two, the voltage on C1 is added to V
CC
,
producing a signal across C2 equal to twice V
CC
. At the same
time, C3 is also charged to 2V
CC
, and then during phase one,
it is inverted with respect to ground to produce a signal across
C4 equal to -2V
CC
. The voltage converter accepts input
voltages up to 5.5V. The output impedance of the doubler (V+)
is approximately 200
, and the output impedance of the
inverter (V-) is approximately 450
. Typical graphs are
presented which show the voltage converters output vs input
voltage and output voltages vs load characteristics. The test
circuit (Figure 3) uses 1
F capacitors for C1-C4, however, the
value is not critical. Increasing the values of C1 and C2 will
lower the output impedance of the voltage doubler and
inverter, and increasing the values of the reservoir capacitors,
C3 and C4, lowers the ripple on the V+ and V- supplies.
Transmitters
The transmitters are TTL/CMOS compatible inverters which
translate the inputs to RS-232 outputs. The input logic thresh-
old is about 26% of V
CC
, or 1.3V for V
CC
= 5V. A logic 1 at
the input results in a voltage of between -5V and V- at the out-
put, and a logic 0 results in a voltage between +5V and (V+
- 0.6V). Each transmitter input has an internal 400k
pullup
resistor so any unused input can be left unconnected and its
output remains in its low state. The output voltage swing
meets the RS-232C specification of
5V minimum with the
worst case conditions of: both transmitters driving 3k
mini-
mum load impedance, V
CC
= 4.5V, and maximum allowable
operating temperature. The transmitters have an internally
limited output slew rate which is less than 30V/
s. The outputs
are short circuit protected and can be shorted to ground indef-
initely. The powered down output impedance is a minimum of
300
with
2V applied to the outputs and V
CC
= 0V.
Receivers
The receiver inputs accept up to
30V while presenting the
required 3k
to 7k
input impedance even it the power is off
(V
CC
= 0V). The receivers have a typical input threshold of
1.3V which is within the
3V limits, known as the transition
region, of the RS-232 specification. The receiver output is
0V to V
CC
. The output will be low whenever the input is
greater than 2.4V and high whenever the input is floating or
driven between +0.8V and -30V. The receivers feature 0.5V
hysteresis to improve noise rejection.
12
12
R1
OUT
Receiver 1 TTL/CMOS output.
13
13
R1
IN
RS-232 Receiver 1 input, with internal 5K pulldown resistor to GND.
14
14
T1
OUT
RS-232 Transmitter 1 output
10V (typical).
15
15
GND
Supply Ground.
16
16
V
CC
Positive Power Supply +5V
10%
Pin Descriptions
(Continued)
PDIP, CERDIP
SOIC
PIN NAME
DESCRIPTION
+
-
C1
+
-
C3
+
-
C2
+
-
C4
S1
S2
S5
S6
S3
S4
S7
S8
V
CC
GND
RC
OSCILLATOR
V
CC
GND
V+ = 2V
CC
GND
V- = -(V+)
C1
+
C1
-
C2
-
C2
+
VOLTAGE INVERTER
VOLTAGE DOUBLER
FIGURE 5. DUAL CHARGE PUMP
T1
IN
, T2
IN
T1
OUT
, T2
OUT
V
OH
V
OL
t
r
t
f
90%
10%
Instantaneous
Slew Rate (SR)
=
(0.8) (V
OH
- V
OL
)
t
r
or
(0.8) (V
OL
- V
OH
)
t
f
FIGURE 6. SLEW RATE DEFINITION
T
OUT
V- < V
TOUT
< V+
300
400k
T
XIN
GND < T
XIN
< V
CC
V-
V+
V
CC
FIGURE 7. TRANSMITTER
ICL232
8-53
Applications
The ICL232 may be used for all RS-232 data terminal and
communication links. It is particularly useful in applications
where
12V power supplies are not available for conven-
tional RS-232 interface circuits. The applications presented
represent typical interface configurations.
A simple duplex RS-232 port with CTS/RTS handshaking is
illustrated in Figure 10. Fixed output signals such as DTR
(data terminal ready) and DSRS (data signaling rate select)
is generated by driving them through a 5k
resistor
connected to V+.
In applications requiring four RS-232 inputs and outputs
(Figure 11), note that each circuit requires two charge pump
capacitors (C1 and C2) but can share common reservoir
capacitors (C3 and C4). The benefit of sharing common res-
ervoir capacitors is the elimination of two capacitors and the
reduction of the charge pump source impedance which
effectively increases the output swing of the transmitters.
R
OUT
GND < V
ROUT
< V
CC
5k
R
XIN
-30V < R
XIN
< +30V
GND
V
CC
FIGURE 8. RECEIVER
T1
IN
, T2
IN
V
OH
V
OL
t
PLH
t
PHL
Average Propagation Delay =
t
PHL +
t
PLH
2
OR
R1
IN
, R2
IN
T1
OUT
, T2
OUT
OR
R1
OUT
, R2
OUT
FIGURE 9. PROPAGATION DELAY DEFINITION
-
+
-
+
-
+
CTR (20) DATA
TERMINAL READY
DSRS (24) DATA
SIGNALING RATE
RS-232
INPUTS AND OUTPUTS
TD (2) TRANSMIT DATA
RTS (4) REQUEST TO SEND
RD (3) RECEIVE DATA
CTS (5) CLEAR TO SEND
SIGNAL GROUND (7)
15
8
13
7
14
16
-
+
6
R2
R1
T2
T1
9
12
10
11
4
5
3
1
ICL232
C1
1
F
C2
1
F
TD
RTS
RD
CTS
SELECT
+5V
INPUTS
OUTPUTS
TTL/CMOS
C3
1
F
C4
1
F
2
5k
5k
FIGURE 10. SIMPLE DUPLEX RS-232 PORT WITH CTS/RTS
HANDSHAKING
-
+
RS-232
INPUTS AND
DTR (20) DATA TERMINAL
DSRS (24) DATA SIGNALING
DCD (8) DATA CARRIER
R1 (22) RING INDICATOR
SIGNAL GROUND (7)
15
8
13
7
14
2
-
+
4
R2
R1
T2
T1
9
12
10
11
3
1
ICL232
C1
1
F
DTR
DSRS
DCD
R1
+5V
INPUTS
OUTPUTS
TTL/CMOS
-
+
-
+
TD (2) TRANSMIT DATA
RTS (4) REQUEST TO SEND
RD (3) RECEIVE DATA
CTS (5) CLEAR TO SEND
8
13
7
14
15
R2
R1
T2
T1
9
12
10
11
4
5
3
1
ICL232
C1
1
F
C2
1
F
TD
RTS
RD
CTS
INPUTS
OUTPUTS
TTL/CMOS
-
+
5
C2
1
F
16
C3
2
6
2
6
V-
V+
-
+
C4
2
F
OUTPUTS
RATE SELECT
READY
DETECT
FIGURE 11. COMBINING TWO ICL232s FOR 4 PAIRS OF RS-232 INPUTS AND OUTPUTS
F
ICL232
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